From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 836C1A04B7; Sun, 4 Oct 2020 11:24:29 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6380C1B96F; Sun, 4 Oct 2020 11:24:27 +0200 (CEST) Received: from hqnvemgate24.nvidia.com (hqnvemgate24.nvidia.com [216.228.121.143]) by dpdk.org (Postfix) with ESMTP id 162FD1B878 for ; Sun, 4 Oct 2020 11:24:24 +0200 (CEST) Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 04 Oct 2020 02:22:38 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 4 Oct 2020 09:22:07 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.172) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 4 Oct 2020 09:22:07 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BRlKLXExQ7gp7BtHgEDVmOllSvMWiwcHfYc9hXa9eQbyG1Bxk7/O1r6cD27d6D3NxXplf9FSoT+4f0d4/zTjFwnPfruB3sHO4aNbfR4THOphxOZMkuqO57YNA3qJkyOtzDuucNVAoGAjA56KltQpR6ze/eE0uk7L3v8ahy+eMw7aen7XmgD6H2lAoA77XFRhOPfRQO0XeHDROqJmtLRw+PLOtcRMr1jynvT69cBB3t2Ut7SnykngypPE0OZwHw1SfbZ7ht+RpJU1JKJUu37cJPRwcGaJ1bsm9rw1VDkBGT8XbKWLWqEFn5a1Ns9X+LhNwQTdfCWs3XjHVQVv+UB7zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oBySnYneFlPdLhJTxTT8IpWt8HG5DH362EWxv6QdTmQ=; b=f1rjJGHCOpKgXmJvggjgZVQsL3119dsSVuFaIZxx3ehQVb6ja8IDa+jDuL5mfO05uA++46SBRKSMVRKm+2RK4idL0yciJCoxea36T31Ia1zTiMjVMjOP9R61A9a1eHF2pDDV22tQuKTcFhHHZNXd9DGo7Z2KqCF4fn8pjtvM/dOtMCpRaA57HTLYHpasfIgH1g2K+KLHyisQ0eWkuf6nnXDuRWUr5WldMwD4hEsCKuyOWaG8+rS3fnLRvbhZlRRfhOCujD0SYMX6GMXBrcYh/Q/cRn6VCo/BtRAiVkX052o6VVZgCbSJfWs0JjCBG7ccnCKCrGMm2q9TNjaid12Tug== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from MN2PR12MB4286.namprd12.prod.outlook.com (2603:10b6:208:199::22) by MN2PR12MB4637.namprd12.prod.outlook.com (2603:10b6:208:3e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.37; Sun, 4 Oct 2020 09:22:06 +0000 Received: from MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f]) by MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f%8]) with mapi id 15.20.3433.042; Sun, 4 Oct 2020 09:22:06 +0000 From: Ori Kam To: Bing Zhao , NBU-Contact-Thomas Monjalon , "ferruh.yigit@intel.com" , "arybchenko@solarflare.com" , "mdr@ashroe.eu" , "nhorman@tuxdriver.com" , "bernard.iremonger@intel.com" , "beilei.xing@intel.com" , "wenzhuo.lu@intel.com" CC: "dev@dpdk.org" Thread-Topic: [PATCH 2/4] ethdev: add new attributes to hairpin config Thread-Index: AQHWl4mKolKESgOFwUGUlT1VdJT8BqmHMA3Q Date: Sun, 4 Oct 2020 09:22:05 +0000 Message-ID: References: <1600012140-70151-1-git-send-email-bingz@nvidia.com> <1601511962-21532-1-git-send-email-bingz@nvidia.com> <1601511962-21532-3-git-send-email-bingz@nvidia.com> In-Reply-To: <1601511962-21532-3-git-send-email-bingz@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [147.236.152.129] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4d26c6d7-4ebb-40be-e8d7-08d86846f62c x-ms-traffictypediagnostic: MN2PR12MB4637: x-ld-processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: TuITnglZ+s4Z5d1pWL6T/gEHPBFqiuauPcL1UgXUV03IvVtiW7QDVOeQTJzJ2/3VNOn8CYyhDfiI/Sbe6W2QkRNDBfbdZphVJQWovAB/LnaEiK3slG2nKgCuwxOt5wd/mPzJnqPK9EF3pmkitEYsTYbQ2kcX1stz0jWY/CEJp/+f2QcIuDsD87hL7fFd8P6Jf2N+U9pKWgR9OcvDZfLjIrGHNvUKAQ4PB10QjstW33wKuIrEVrALE1aWS7yOGZPNJO2OEuuPs+8YQUF8sdWsTFbtleFFOt7/K5QNZ1YGNuLngRoFmgyqIziU983eezia x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MN2PR12MB4286.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(396003)(136003)(376002)(39850400004)(346002)(55016002)(8676002)(8936002)(478600001)(33656002)(186003)(26005)(2906002)(83380400001)(9686003)(110136005)(5660300002)(52536014)(316002)(7696005)(53546011)(71200400001)(4326008)(66476007)(66556008)(66446008)(64756008)(86362001)(66946007)(76116006)(6506007); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: e5JwNFrxVIMOUc/IXx/LSqz4suJk1OmCwChZAUIr5TQTdkrybqExWaQEwzGB08Ve9f7LWx6Cvcur3VmNH/3PWW200uwF2B0Py33o7dWD1LvUt7D3mCQq1c4saWWUrkbnEGnaKXVbnuli4d8VILCuKRhNgmhSaOY90VDYtWEHZNKT056NTwMS9yGFDIOmjwfcHt8A3R/surLKcuDGWbZ/tbr7HE/ATANlc70l6C9ajHkEoEuvU30vKcJO/R8C28EjRaEdUhQAE1fpVoVPUNsu6l8si7S8iLSDWTvZelx33BwptK90/nC1jT/S9p/Cnpnjc3DN3Fe9X9KA5Z1ZoVIKpaEAcJJLkNCl8LA020Ya1rIEUeTL8zFGiLFTAQQjIyJcngrarqOPLA9QVv4WKNFC5kcGS9WCxpSVGl5kRpHv4DrOw4ExI/POhemAVYAtt0KpYBV6aGY1/5AB3jcQjjN5xNK3DtD4Vik1cuERmAHJcCWg4fV0xK3SY0Vf/QjTyBYbnAYMiWDB4s9ZcUSys1j+l42fxMkZvqneZbdyTi4p95LOHXR+5H+ZwfxPY0/h6ufnoTmvUsttX7fwJMC+5Hspgu3mgWqC4olghvq0BU1dW5gA0z2BHjG3gPIvqOiZp8ESw0TSt9YgzZPXB/KSUp71SA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4d26c6d7-4ebb-40be-e8d7-08d86846f62c X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Oct 2020 09:22:05.9236 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: K2UOIQ+6jqEX1FgpnuH5orEKDRZIT7R9NmiPB8xATkUyBCf4jXLRWjNjI95iNWjNYMnDcXtvMtetqx5Js+CvXA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4637 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1601803358; bh=oBySnYneFlPdLhJTxTT8IpWt8HG5DH362EWxv6QdTmQ=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To: CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References: In-Reply-To:Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ld-processed: x-ms-exchange-transport-forked:x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers:x-ms-exchange-senderadcheck: x-microsoft-antispam:x-microsoft-antispam-message-info: x-forefront-antispam-report:x-ms-exchange-antispam-messagedata: Content-Type:Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=KcD7yNEZ9AVkBBzLB2uKdQEWtLrz6QvwG+zW90QaI1OU/Sd2VFf/RUKcCIZa9xv6W Z9S6ERzJ3H2AGNIk7ZJ5ibpGsCFnVfmMaTZEP7UKn02FuVFv/E0wotWORLN/xJhxHu j1LQeo4LTMTnwwMh0L7CVYFidmDxh1VsSstaifXzXKibYczfaqRps5cKxQeRIKnuDk vQAUDpNhRjYnI3M5Nd4/vrft1VBhk3nbln+I80D4DAxnFzAoLXxwJImr1NVPzLZiYI eSXBIwA5WC915Qj0GObXZv6kcFA1mx64u/uBkxJF1jOF9dRK74z8jiRHkcO63FDH0c rgUbm116BZnyQ== Subject: Re: [dpdk-dev] [PATCH 2/4] ethdev: add new attributes to hairpin config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Bing, PSB, Best, Ori > -----Original Message----- > From: Bing Zhao > Sent: Thursday, October 1, 2020 3:26 AM > Subject: [PATCH 2/4] ethdev: add new attributes to hairpin config >=20 > To support two ports hairpin mode and keep the backward compatibility > for the application, two new attribute members of hairpin queue > config structure are added. >=20 > `tx_explicit` means if the application itself will insert the TX part > flow rules. If not set, PMD will insert the rules implicitly. > `manual_bind` means if the hairpin TX queue and peer RX queue will be > bound automatically during device start stage. >=20 > Different TX and RX queue pairs could have different values, but it > is highly recommend that all paired queues between one egress and its > peer ingress ports have the same values, in order not to bring any > chaos to the system. The actual support of these attribute parameters > will be checked and decided by the PMD driver. >=20 > In a single port hairpin, if both are zero without any setting, the > behavior will remain the same as before. It means no bind API needs > to be called and no TX flow rules need to be inserted manually by > the application. >=20 > Signed-off-by: Bing Zhao > --- > lib/librte_ethdev/rte_ethdev.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) >=20 > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethde= v.h > index c3fb684..0cabff0 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -1027,6 +1027,21 @@ struct rte_eth_hairpin_cap { >=20 > #define RTE_ETH_MAX_HAIRPIN_PEERS 32 >=20 > +/* > + * Hairpin queue attribute parameters. > + * Each TX queue and peer RX queue should have the same value. > + * Default value 0 is for backward-compatibility, the same behaviors sho= uld > + * remain if the value is not set (0). > + */ > +/**< Hairpin queues will be bound automatically */ > +#define RTE_ETH_HAIRPIN_BIND_AUTO (0) > +/**< Hairpin queues will be bound manually with bind API */ > +#define RTE_ETH_HAIRPIN_BIND_MANUAL (1) > +/**< Hairpin TX part flow rule will be inserted implicitly by PMD */ > +#define RTE_ETH_HAIRPIN_TXRULE_IMPLICIT (0) > +/**< Hairpin TX part flow rule will be inserted explicitly by APP */ > +#define RTE_ETH_HAIRPIN_TXRULE_EXPLICIT (1) > + Why do you need those defines if you are using bit fields? > /** > * @warning > * @b EXPERIMENTAL: this API may change, or be removed, without prior > notice > @@ -1046,6 +1061,9 @@ struct rte_eth_hairpin_peer { > */ > struct rte_eth_hairpin_conf { > uint16_t peer_count; /**< The number of peers. */ > + uint32_t reserved : 30; /**< Reserved bits. */ > + uint32_t tx_explicit : 1; /**< Explicit TX flow rule mode. */ > + uint32_t manual_bind : 1; /**< Manually bind hairpin queues. */ Why not place the new bits at the end? Also why do you place the reserved first? > struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS]; > }; >=20 > -- > 2.5.5