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mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from MN2PR12MB4286.namprd12.prod.outlook.com (2603:10b6:208:199::22) by MN2PR12MB4830.namprd12.prod.outlook.com (2603:10b6:208:1bc::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.36; Thu, 1 Oct 2020 08:13:37 +0000 Received: from MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f]) by MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f%8]) with mapi id 15.20.3433.035; Thu, 1 Oct 2020 08:13:37 +0000 From: Ori Kam To: Li Zhang , Dekel Peled , "Slava Ovsiienko" , Matan Azrad CC: "dev@dpdk.org" , NBU-Contact-Thomas Monjalon , Raslan Darawsheh Thread-Topic: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP identifier fields Thread-Index: AQHWl0l3vDLWudK0v0GDTgEsCcIk0amCZUHg Date: Thu, 1 Oct 2020 08:13:37 +0000 Message-ID: References: <20200928033813.22112-1-lizh@nvidia.com> <20200930164734.23675-1-lizh@nvidia.com> In-Reply-To: <20200930164734.23675-1-lizh@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; 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b=IBzo+WgecXgDPLCWN4WTTQ4mfOYqdtshqNLktEq1P1LSz6PgH2vIFL/aWZD7tMQjO 8zm5nCT0ps2iu3apGUzX7QFKew+3S3mtoF6Kvj7EJ5IpekD+xAJzRtCBdVbn70InMM j667dY8QZi+vXRr85fSaqprSGaUgqKrdcke2+twUu3wTHd4vf0X+6NvNTmqWQPlyZl S7iPCfHO8dWQj1tYE0T/qCy4Y++M4Nylo6r9MING63sKTCdrJngTxajXvhaYdCgHro HQd+csPevTrE/aTsrlRuWXtfVy3YnyjdV3LHj9999WQZqsIrsv/kUsKP6VOBv/DF+Q eqmiDIYWkyF3w== Subject: Re: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP identifier fields X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi=20 Sorry I didn't see that you sent V3 and responded on V2 So just rewriting my comments. Best, Ori > -----Original Message----- > From: dev On Behalf Of Li Zhang > Subject: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP identifie= r > fields >=20 > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > Update ICMP mask parameter with ICMP identifier and sequence number > fields. > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set= . > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. >=20 > Signed-off-by: Li Zhang > --- > doc/guides/nics/mlx5.rst | 4 ++-- > doc/guides/rel_notes/release_20_11.rst | 2 +- > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > drivers/net/mlx5/mlx5_flow_dv.c | 16 +++++++++++++++- > 4 files changed, 26 insertions(+), 6 deletions(-) >=20 > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst > index 211c0c5a6c..576dbe5efd 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -288,7 +288,7 @@ Limitations > - The input buffer, providing the removal size, is not validated. > - The buffer size must match the length of the headers to be removed. >=20 > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching= , > IP-in-IP and MPLS flow matching are all > mutually exclusive features which cannot be supported together > (see :ref:`mlx5_firmware_config`). >=20 > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. >=20 > FLEX_PARSER_PROFILE_ENABLE=3D1 >=20 > -- enable ICMP/ICMP6 code/type fields matching:: > +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > fields matching:: >=20 > FLEX_PARSER_PROFILE_ENABLE=3D2 >=20 > diff --git a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index c6642f5f94..791f133d8f 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -73,7 +73,7 @@ New Features > * Added flag action. > * Added raw encap/decap actions. > * Added VXLAN encap/decap actions. > - * Added ICMP and ICMP6 matching items. > + * Added ICMP(code/type/identifier/sequence number) and > ICMP6(code/type) matching items. > * Added option to set port mask for insertion/deletion: > ``--portmask=3DN`` > where N represents the hexadecimal bitmask of ports used. > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index 416505f1c8..3cabfd4627 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > struct rte_flow_error *error) > { > const struct rte_flow_item_icmp *mask =3D item->mask; > + const struct rte_flow_item_icmp nic_mask =3D { > + .hdr.icmp_type =3D 0xff, > + .hdr.icmp_code =3D 0xff, > + .hdr.icmp_ident =3D RTE_BE16(0xffff), > + .hdr.icmp_seq_nb =3D RTE_BE16(0xffff), > + }; > const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > @@ -1325,10 +1331,10 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "multiple L4 layers not supported"); > if (!mask) > - mask =3D &rte_flow_item_icmp_mask; > + mask =3D &nic_mask; > ret =3D mlx5_flow_item_acceptable > (item, (const uint8_t *)mask, > - (const uint8_t *)&rte_flow_item_icmp_mask, > + (const uint8_t *)&nic_mask, > sizeof(struct rte_flow_item_icmp), error); > if (ret < 0) > return ret; > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c > index 3819cdb266..b5d6455067 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > { > const struct rte_flow_item_icmp *icmp_m =3D item->mask; > const struct rte_flow_item_icmp *icmp_v =3D item->spec; > + uint32_t icmp_header_data_m =3D 0; > + uint32_t icmp_header_data_v =3D 0; > void *headers_m; > void *headers_v; > void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > @@ -7396,8 +7398,14 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMP); > if (!icmp_v) > return; > - if (!icmp_m) > + if (!icmp_m) { > icmp_m =3D &rte_flow_item_icmp_mask; > + icmp_header_data_m =3D RTE_BE32(UINT32_MAX); > + } else { > + icmp_header_data_m =3D rte_cpu_to_be_16(icmp_m- > >hdr.icmp_seq_nb); > + icmp_header_data_m |=3D > + rte_cpu_to_be_16(icmp_m->hdr.icmp_ident) << 16; > + } Yes but there is no need to add new fields to the mask, it will break exist= ing applications. So please remove it. > /* > * Force flow only to match the non-fragmented IPv4 ICMP packets. > * If only the protocol is specified, no need to match the frag. > @@ -7412,6 +7420,12 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > icmp_m->hdr.icmp_code); > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > + icmp_header_data_v =3D rte_cpu_to_be_16(icmp_v->hdr.icmp_seq_nb); > + icmp_header_data_v |=3D rte_cpu_to_be_16(icmp_v->hdr.icmp_ident) > << 16; Why is it not BE? From the structure definition: struct rte_icmp_hdr { uint8_t icmp_type; /* ICMP packet type. */ uint8_t icmp_code; /* ICMP packet code. */ rte_be16_t icmp_cksum; /* ICMP packet checksum. */ rte_be16_t icmp_ident; /* ICMP packet identifier. */ rte_be16_t icmp_seq_nb; /* ICMP packet sequence number. */ } __rte_packed; Also you are setting cpu value with BE. Maybe you want to rte_be_to_cpu? > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, > + icmp_header_data_m); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, > + icmp_header_data_v & icmp_header_data_m); > } >=20 > /** > -- > 2.21.0