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Sun, 26 May 2019 05:33:13 +0000 Received: from MN2PR18MB2398.namprd18.prod.outlook.com ([fe80::8c4e:13f8:a804:d2ac]) by MN2PR18MB2398.namprd18.prod.outlook.com ([fe80::8c4e:13f8:a804:d2ac%5]) with mapi id 15.20.1922.021; Sun, 26 May 2019 05:33:13 +0000 From: Liron Himi To: "Ruifeng Wang (Arm Technology China)" , "thomas@monjalon.net" CC: "dev@dpdk.org" , nd , Liron Himi Thread-Topic: [dpdk-dev] [PATCH 1/2] mk: add Marvell ARMADA architecture based on armv8-a Thread-Index: AQHVEgVzyEuRFn01YUSDHSSW1OGrmaZ848LQ Date: Sun, 26 May 2019 05:33:13 +0000 Message-ID: References: <1558128867-15941-1-git-send-email-lironh@marvell.com> <1558128867-15941-2-git-send-email-lironh@marvell.com> In-Reply-To: Accept-Language: he-IL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [46.116.38.53] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f995f027-fe77-4a98-1869-08d6e19ba5b9 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f995f027-fe77-4a98-1869-08d6e19ba5b9 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 May 2019 05:33:13.4756 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lironh@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2542 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-26_03:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH 1/2] mk: add Marvell ARMADA architecture based on armv8-a X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Regards, Liron -----Original Message----- From: Ruifeng Wang (Arm Technology China) =20 Sent: Friday, May 24, 2019 10:51 To: Liron Himi ; thomas@monjalon.net Cc: dev@dpdk.org; nd Subject: [EXT] RE: [dpdk-dev] [PATCH 1/2] mk: add Marvell ARMADA architectu= re based on armv8-a External Email ---------------------------------------------------------------------- Hi, > -----Original Message----- > From: dev On Behalf Of lironh@marvell.com > Sent: Saturday, May 18, 2019 05:34 > To: thomas@monjalon.net > Cc: dev@dpdk.org; Liron Himi > Subject: [dpdk-dev] [PATCH 1/2] mk: add Marvell ARMADA architecture=20 > based on armv8-a >=20 > From: Liron Himi >=20 > This patch introduces armada target to address difference in number of=20 > cores, no numa support >=20 > Signed-off-by: Liron Himi > Reviewed-by: Alan Winkowski > Tested-by: Liron Himi > --- > config/defconfig_arm64-armada-linux-gcc | 24 > ++++++++++++++++++++++++ > config/defconfig_arm64-armada-linuxapp-gcc | 24 > ++++++++++++++++++++++++ > 2 files changed, 48 insertions(+) > create mode 100644 config/defconfig_arm64-armada-linux-gcc > create mode 100644 config/defconfig_arm64-armada-linuxapp-gcc >=20 > diff --git a/config/defconfig_arm64-armada-linux-gcc > b/config/defconfig_arm64-armada-linux-gcc > new file mode 100644 > index 0000000..573b278 > --- /dev/null > +++ b/config/defconfig_arm64-armada-linux-gcc > @@ -0,0 +1,24 @@ > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell=20 > +International Ltd # > + > +#include "defconfig_arm64-armv8a-linux-gcc" > + > +CONFIG_RTE_LIBRTE_MVEP_COMMON=3Dy > +CONFIG_RTE_LIBRTE_MVPP2_PMD=3Dy > +CONFIG_RTE_LIBRTE_MVNETA_PMD=3Dy > +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=3Dy > + > +# > +# Compile Environment Abstraction Layer # > +CONFIG_RTE_MAX_LCORE=3D16 > +CONFIG_RTE_MAX_NUMA_NODES=3D1 > +CONFIG_RTE_CACHE_LINE_SIZE=3D64 > + > +# Disable NXP as it is conflict with MUSDK > CONFIG_RTE_LIBRTE_DPAA_BUS=3Dn > + > +# Doesn't support NUMA > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > +CONFIG_RTE_LIBRTE_VHOST_NUMA=3Dn > diff --git a/config/defconfig_arm64-armada-linuxapp-gcc > b/config/defconfig_arm64-armada-linuxapp-gcc > new file mode 100644 > index 0000000..573b278 > --- /dev/null > +++ b/config/defconfig_arm64-armada-linuxapp-gcc > @@ -0,0 +1,24 @@ > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell=20 > +International Ltd # > + > +#include "defconfig_arm64-armv8a-linux-gcc" > + Maybe CONFIG_RTE_MACHINE and CONFIG_RTE_ARCH_ARM_TUNE can be added as well. [L.H.] currently we are not using special machine flags, just the defaults = ones. As for the TUNE, this config file support two platforms which have differen= t arm cores, in this moment I don't want to split it to two config files just for this parameter.=20 I referred to defconfig_arm64-dpaa2-linuxapp-gcc. > +CONFIG_RTE_LIBRTE_MVEP_COMMON=3Dy > +CONFIG_RTE_LIBRTE_MVPP2_PMD=3Dy > +CONFIG_RTE_LIBRTE_MVNETA_PMD=3Dy > +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=3Dy > + > +# > +# Compile Environment Abstraction Layer # > +CONFIG_RTE_MAX_LCORE=3D16 > +CONFIG_RTE_MAX_NUMA_NODES=3D1 > +CONFIG_RTE_CACHE_LINE_SIZE=3D64 > + > +# Disable NXP as it is conflict with MUSDK > CONFIG_RTE_LIBRTE_DPAA_BUS=3Dn > + > +# Doesn't support NUMA > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > +CONFIG_RTE_LIBRTE_VHOST_NUMA=3Dn > -- > 2.7.4