RE: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change

["Namburu, Chandu-babu" <chandu@amd.com>]

[Public]

Acked-by: Chandubabu Namburu <chandu@amd.com>

-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com> 
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change

From: Selwin Sebastian <selwin.sebastian@amd.com>

For each rate change command submission, the FW has to do a phy power off sequence internally. For this to happen correctly, the PLL re-initialization control setting has to be turned off before sending mailbox commands and re-enabled once the command submission is complete. Without the PLL control setting, the link up takes longer time in a fixed phy configuration.

Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
 drivers/net/axgbe/axgbe_common.h   |  9 +++++++++
 drivers/net/axgbe/axgbe_phy_impl.c | 22 ++++++++++++++++++++--
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
 #define MDIO_VEND2_PMA_CDR_CONTROL	0x8056
 #endif
 
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0	0x8090
+#endif
+
+
 #ifndef MDIO_CTRL1_SPEED1G
 #define MDIO_CTRL1_SPEED1G		(MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
 #endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
 	return (addr >> 32) & 0x0ffffffff;
 }
 
+#define XGBE_PMA_PLL_CTRL_MASK         BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET          BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR                0x0000
+
 /*END*/
 
 /* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 72104f8a3f..08d3484a11 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
 	axgbe_phy_put_comm_ownership(pdata);
 }
 
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
+	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+			XGBE_PMA_PLL_CTRL_MASK,
+			enable ? XGBE_PMA_PLL_CTRL_SET
+			: XGBE_PMA_PLL_CTRL_CLEAR);
+
+	/* Wait for command to complete */
+	rte_delay_us(150);
+}
+
 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)  {
+	/* Clear the PLL so that it helps in power down sequence */
+	axgbe_phy_pll_ctrl(pdata, false);
+
 	/* Log if a previous command did not complete */
 	if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
 		PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); @@ -1213,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
 	wait = AXGBE_RATECHANGE_COUNT;
 	while (wait--) {
 		if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
-			return;
-
+			goto reenable_pll;
 		rte_delay_us(1500);
 	}
+
+reenable_pll:
+	 /* Re-enable the PLL control */
+	axgbe_phy_pll_ctrl(pdata, true);
+
 	PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");  }
 
--
2.25.1