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Sat, 8 May 2021 12:13:26 +0000 From: Akhil Goyal To: Matan Azrad , "dev@dpdk.org" CC: "suanmingm@nvidia.com" , Thomas Monjalon , Shiri Kuzin Thread-Topic: [EXT] [PATCH v3 15/15] crypto/mlx5: set feature flags and capabilities Thread-Index: AQHXQSnWsvz25MKtdkqt23wDGjSfNKrZdQEA Date: Sat, 8 May 2021 12:13:25 +0000 Message-ID: References: <20210429154712.2820159-1-matan@nvidia.com> <20210504210857.3398397-1-matan@nvidia.com> <20210504210857.3398397-16-matan@nvidia.com> In-Reply-To: <20210504210857.3398397-16-matan@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=marvell.com; x-originating-ip: [171.48.51.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a95b7e2c-a22a-4725-135c-08d9121aaee2 x-ms-traffictypediagnostic: MW2PR18MB2282: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW2PR18MB2284.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a95b7e2c-a22a-4725-135c-08d9121aaee2 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 May 2021 12:13:25.9248 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oVnFH4nnWCYVEdZUtsIa2ZiVo0M+Pf3/5547KnjuLVYvvqLY9uqyTkJHNA9aoR8kTG5xauk1gnlWcb5nxOfwBQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR18MB2282 X-Proofpoint-ORIG-GUID: Ka-UZU5grDQjT47zqRKtx81O8_1lPzgO X-Proofpoint-GUID: Ka-UZU5grDQjT47zqRKtx81O8_1lPzgO X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-08_06:2021-05-06, 2021-05-08 signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 15/15] crypto/mlx5: set feature flags and capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > + > +Overview > +-------- > + > +The device can provide disk encryption services, allowing data encryptio= n > +and decryption towards a disk. Having all encryption/decryption > +operations done in a single device can reduce cost and overheads of the > related > +FIPS certification, as ConnectX-6 is FIPS 140-2 level-2 ready. > +The encryption cipher is AES-XTS of 256/512 key size. 256/512 bit key size > + > +MKEY is a memory region object in the hardware, that holds address > translation information and > +attributes per memory area. Its ID must be tied to addresses provided to > the hardware. > +The encryption operations are performed with MKEY read\write read/write > transactions, when > +the MKEY is configured to perform crypto operations. > + > +The encryption does not require text to be aligned to the AES block size > (128b). > + > +In order to move the device to crypto operational mode, credential and K= EK > +(Key Encrypting Key) should be set as the first step. > +The credential will be used by the software in order to perform crypto l= ogin, > and the KEK is > +the AES Key Wrap Algorithm (rfc3394) key that will be used for sensitive > data > +wrapping. > +The credential and the AES-XTS keys should be provided to the hardware, = as > ciphertext > +encrypted by the KEK. > + > +A keytag (64 bits) should be appended to the AES-XTS keys (before > wrapping), > +and will be validated when the hardware attempts to access it. > + > +For security reasons and to increase robustness, this driver only deals = with > virtual > +memory addresses. The way resources allocations are handled by the > kernel, > +combined with hardware specifications that allow handling virtual memory > +addresses directly, ensure that DPDK applications cannot access random > +physical memory (or memory that does not belong to the current process). > + > +The PMD uses libibverbs and libmlx5 to access the device firmware or to > +access the hardware components directly. > +There are different levels of objects and bypassing abilities. > +To get the best performances: > + > +- Verbs is a complete high-level generic API. > +- Direct Verbs is a device-specific API. > +- DevX allows to access firmware objects. > + > +Enabling librte_crypto_mlx5 causes DPDK applications to be linked agains= t > +libibverbs. > + > +Mellanox mlx5 PCI device can be probed by a number of different PCI > devices, such as > +net / vDPA / RegEx. To select the crypto PMD, ``class=3Dcrypto`` > +should be specified as a device parameter. The crypto device can be prob= ed > and > +used with other Mellanox classes by adding more options in the class. > +For example: ``class=3Dnet:crypto`` will probe both the net PMD and the > crypto > +PMD. > + > +When crypto engines are defined to work in wrapped import method, they > come out > +of the factory in Commissioning mode, and thus, cannot be used for crypt= o > operations > +yet. A dedicated tool is used for changing the mode from Commissioning t= o > +Operational, while setting the first import_KEK and credential in plaint= ext. > +The mlxreg dedicated tool should be used as follows: > + > +- Set CRYPTO_OPERATIONAL register to set the device in crypto operationa= l > mode. > + > + The input to this tool is: > + The first credential in plaintext, 40B. > + The first import_KEK in plaintext: kek size 0 for 16B or 1 for 32B, = kek data. > + > + Example: > + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL - > -get > + > + The "wrapped_crypto_operational" value will be "0x00000000". > + The command to set the register should be executed only once, and all = the > + values mentioned above should be specified in the same command. > + > + Example: > + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL > + --set "credential[0]=3D0x10000000, credential[1]=3D0x10000000, > kek[0]=3D0x00000000" > + > + All values not specified will remain 0. > + "wrapped_crypto_going_to_commissioning" and > "wrapped_crypto_operational" > + should not be specified. > + > + All the device ports should set it in order to move to operational mod= e. > + > +- Query CRYPTO_OPERATIONAL register to make sure the device is in > Operational > + mode. > + > + Example: > + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL - > -get > + The "wrapped_crypto_operational" value will be "0x00000001" if the > mode was > + successfully changed to operational mode. > + > + > +Driver options > +-------------- > + > +- ``class`` parameter [string] > + > + Select the class of the driver that should probe the device. > + `crypto` for the mlx5 crypto driver. > + > +- ``wcs_file`` parameter [string] - mandatory > + > + File path including only the wrapped credential in string format of > hexadecimal > + numbers, represent 48 bytes (8 bytes IV added by the AES key wrap > algorithm). > + > +- ``import_kek_id`` parameter [int] > + > + The identifier of the KEK, default value is 0 represents the operation= al > + register import_kek.. > + > +- ``credential_id`` parameter [int] > + > + The identifier of the credential, default value is 0 represents the > operational > + register credential. > + > +- ``max_segs_num`` parameter [int] > + > + Maximum number of mbuf chain segments(src or dest), default value is 8= . > + > +- ``keytag`` parameter [int] > + > + The plaintext of the keytag appanded to the AES-XTS keys, default valu= e is > 0. > + > + > +Limitations > +----------- > + > +- AES-XTS keys provided in Xform must include keytag and should be > wrappend. > +- The supported data-unit lengths are: 512B, 1KB, 1MB. In case the > `dataunit_len` > + is not provided in the cipher Xform, the OP length is limitted to the = above Xform should be xform Spell check - limited > values. > + > + > +Supported NICs > +-------------- > + > +* Mellanox\ |reg| ConnectX\ |reg|-6 200G MCX654106A-HCAT (2x200G) > + > +Prerequisites > +------------- > + > +- Mellanox OFED version: **5.3** > + see :doc:`../../nics/mlx5` guide for more Mellanox OFED details. Since the driver is by default compiled off due to the dependency on extern= al Libraries, I would recommend to add few lines here as well for compilation. Like to compile rdma-core and set PKG_CONFIG_LIBDIR. And I do not see any updates to the test application for testing this drive= r. Is this driver really tested or is it work in progress? If it is work in pr= ogress, We should defer this PMD to next release. > diff --git a/doc/guides/rel_notes/release_21_05.rst > b/doc/guides/rel_notes/release_21_05.rst > index 0970a2331a..9030fd8b98 100644 > --- a/doc/guides/rel_notes/release_21_05.rst > +++ b/doc/guides/rel_notes/release_21_05.rst > @@ -275,6 +275,11 @@ New Features > * Added support for crypto adapter forward mode in octeontx2 event and > crypto > device driver. >=20 > +* **Added support for Nvidia crypto device driver.** > + > + * Added mlx5 crypto driver to support AES-XTS cipher operations. > + the first device to support it is ConnectX-6. 'The'=20 > + >=20 > Removed Items > ------------- > diff --git a/drivers/crypto/mlx5/mlx5_crypto.c > b/drivers/crypto/mlx5/mlx5_crypto.c > index 896ca60866..f318ff4682 100644 > --- a/drivers/crypto/mlx5/mlx5_crypto.c > +++ b/drivers/crypto/mlx5/mlx5_crypto.c > @@ -22,6 +22,14 @@ > #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5 > #define MLX5_CRYPTO_MAX_QPS 1024 > #define MLX5_CRYPTO_MAX_SEGS 56 > +#define MLX5_CRYPTO_FEATURE_FLAGS \ > + (RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | > RTE_CRYPTODEV_FF_HW_ACCELERATED | \ > + RTE_CRYPTODEV_FF_IN_PLACE_SGL | > RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | \ > + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | \ > + RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | \ > + RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | \ > + RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \ > + RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS) >=20 > TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = =3D >=20 > TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); > @@ -31,8 +39,32 @@ int mlx5_crypto_logtype; >=20 > uint8_t mlx5_crypto_driver_id; >=20 > -const struct rte_cryptodev_capabilities > - mlx5_crypto_caps[RTE_CRYPTO_OP_TYPE_UNDEFINED]; > +const struct rte_cryptodev_capabilities mlx5_crypto_caps[] =3D { > + { /* AES XTS */ > + .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC, > + {.sym =3D { > + .xform_type =3D RTE_CRYPTO_SYM_XFORM_CIPHER, > + {.cipher =3D { > + .algo =3D RTE_CRYPTO_CIPHER_AES_XTS, > + .block_size =3D 16, > + .key_size =3D { > + .min =3D 32, > + .max =3D 64, > + .increment =3D 32 > + }, > + .iv_size =3D { > + .min =3D 16, > + .max =3D 16, > + .increment =3D 0 > + }, > + .dataunit_set =3D > + > RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES | > + > RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES, > + }, } > + }, } > + }, > +}; > + >=20 > static const char mlx5_crypto_drv_name[] =3D > RTE_STR(MLX5_CRYPTO_DRIVER_NAME); >=20 > @@ -67,7 +99,7 @@ mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, > RTE_SET_USED(dev); > if (dev_info !=3D NULL) { > dev_info->driver_id =3D mlx5_crypto_driver_id; > - dev_info->feature_flags =3D 0; > + dev_info->feature_flags =3D MLX5_CRYPTO_FEATURE_FLAGS; > dev_info->capabilities =3D mlx5_crypto_caps; > dev_info->max_nb_queue_pairs =3D MLX5_CRYPTO_MAX_QPS; > dev_info->min_mbuf_headroom_req =3D 0; > @@ -954,6 +986,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver > *pci_drv, > crypto_dev->dev_ops =3D &mlx5_crypto_ops; > crypto_dev->dequeue_burst =3D mlx5_crypto_dequeue_burst; > crypto_dev->enqueue_burst =3D mlx5_crypto_enqueue_burst; > + crypto_dev->feature_flags =3D MLX5_CRYPTO_FEATURE_FLAGS; > crypto_dev->driver_id =3D mlx5_crypto_driver_id; > priv =3D crypto_dev->data->dev_private; > priv->ctx =3D ctx; > -- > 2.25.1