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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW3PR11MB4587.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2325dbc2-7eac-4633-6ed0-08db0362c09b X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jan 2023 08:11:27.5521 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Wr5Z4wHTvHZcNsYg2hn4dXuLU5kjF3gb9PvYVrw56vqmAN0x/FLeV7ds0MwtFPMqOSEPvKpv1EV6aMRNRtM2+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB8271 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > @@ -247,8 +247,21 @@ idpf_vport_init(struct idpf_vport *vport, > goto err_rss_lut; > } >=20 > + /* recv_vectors is used for VIRTCHNL2_OP_ALLOC_VECTORS response, > + * reserve maximum size for it now, may need optimization in future. > + */ > + vport->recv_vectors =3D rte_zmalloc("recv_vectors", IDPF_DFLT_MBX_BUF_S= IZE, 0); > + if (vport->recv_vectors =3D=3D NULL) { > + DRV_LOG(ERR, "Failed to allocate ecv_vectors"); ecv-> recv? > + ret =3D -ENOMEM; > + goto err_recv_vec; > + } > + > return 0; >=20 > +err_recv_vec: > + rte_free(vport->rss_lut); > + vport->rss_lut =3D NULL; > err_rss_lut: > vport->dev_data =3D NULL; > rte_free(vport->rss_key); > @@ -261,6 +274,8 @@ idpf_vport_init(struct idpf_vport *vport, > int > idpf_vport_deinit(struct idpf_vport *vport) > { > + rte_free(vport->recv_vectors); > + vport->recv_vectors =3D NULL; > rte_free(vport->rss_lut); > vport->rss_lut =3D NULL; >=20 > @@ -298,4 +313,88 @@ idpf_config_rss(struct idpf_vport *vport) >=20 > return ret; > } > + > +int > +idpf_config_irq_map(struct idpf_vport *vport, uint16_t nb_rx_queues) > +{ > + struct idpf_adapter *adapter =3D vport->adapter; > + struct virtchnl2_queue_vector *qv_map; > + struct idpf_hw *hw =3D &adapter->hw; > + uint32_t dynctl_val, itrn_val; > + uint32_t dynctl_reg_start; > + uint32_t itrn_reg_start; > + uint16_t i; > + > + qv_map =3D rte_zmalloc("qv_map", > + nb_rx_queues * > + sizeof(struct virtchnl2_queue_vector), 0); > + if (qv_map =3D=3D NULL) { > + DRV_LOG(ERR, "Failed to allocate %d queue-vector map", > + nb_rx_queues); > + goto qv_map_alloc_err; Use error code -ENOMEM instead of using -1? > + } > + > + /* Rx interrupt disabled, Map interrupt only for writeback */ > + > + /* The capability flags adapter->caps.other_caps should be > + * compared with bit VIRTCHNL2_CAP_WB_ON_ITR here. The if > + * condition should be updated when the FW can return the > + * correct flag bits. > + */ > + dynctl_reg_start =3D > + vport->recv_vectors->vchunks.vchunks->dynctl_reg_start; > + itrn_reg_start =3D > + vport->recv_vectors->vchunks.vchunks->itrn_reg_start; > + dynctl_val =3D IDPF_READ_REG(hw, dynctl_reg_start); > + DRV_LOG(DEBUG, "Value of dynctl_reg_start is 0x%x", dynctl_val); > + itrn_val =3D IDPF_READ_REG(hw, itrn_reg_start); > + DRV_LOG(DEBUG, "Value of itrn_reg_start is 0x%x", itrn_val); > + /* Force write-backs by setting WB_ON_ITR bit in DYN_CTL > + * register. WB_ON_ITR and INTENA are mutually exclusive > + * bits. Setting WB_ON_ITR bits means TX and RX Descs > + * are written back based on ITR expiration irrespective > + * of INTENA setting. > + */ > + /* TBD: need to tune INTERVAL value for better performance. */ > + itrn_val =3D (itrn_val =3D=3D 0) ? IDPF_DFLT_INTERVAL : itrn_val; > + dynctl_val =3D VIRTCHNL2_ITR_IDX_0 << > + PF_GLINT_DYN_CTL_ITR_INDX_S | > + PF_GLINT_DYN_CTL_WB_ON_ITR_M | > + itrn_val << PF_GLINT_DYN_CTL_INTERVAL_S; > + IDPF_WRITE_REG(hw, dynctl_reg_start, dynctl_val); > + > + for (i =3D 0; i < nb_rx_queues; i++) { > + /* map all queues to the same vector */ > + qv_map[i].queue_id =3D vport->chunks_info.rx_start_qid + i; > + qv_map[i].vector_id =3D > + vport->recv_vectors->vchunks.vchunks->start_vector_id; > + } > + vport->qv_map =3D qv_map; > + > + if (idpf_vc_config_irq_map_unmap(vport, nb_rx_queues, true) !=3D 0) { > + DRV_LOG(ERR, "config interrupt mapping failed"); > + goto config_irq_map_err; > + } > + > + return 0; > + > +config_irq_map_err: > + rte_free(vport->qv_map); > + vport->qv_map =3D NULL; > + > +qv_map_alloc_err: > + return -1; > +} > +