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Thu, 2 Jul 2020 20:30:28 +0000 From: "Carrillo, Erik G" <erik.g.carrillo@intel.com> To: Phil Yang <phil.yang@arm.com>, "dev@dpdk.org" <dev@dpdk.org> CC: "jerinj@marvell.com" <jerinj@marvell.com>, "Honnappa.Nagarahalli@arm.com" <Honnappa.Nagarahalli@arm.com>, "drc@linux.vnet.ibm.com" <drc@linux.vnet.ibm.com>, "Ruifeng.Wang@arm.com" <Ruifeng.Wang@arm.com>, "Dharmik.Thakkar@arm.com" <Dharmik.Thakkar@arm.com>, "nd@arm.com" <nd@arm.com> Thread-Topic: [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics Thread-Index: AQHWUDGr4gDsUEu8kkqWn/npY4B686j0voOg Date: Thu, 2 Jul 2020 20:30:28 +0000 Message-ID: <MWHPR1101MB21270BA4B7A707C909A29A9BB96D0@MWHPR1101MB2127.namprd11.prod.outlook.com> References: <1591960798-24024-1-git-send-email-phil.yang@arm.com> <1593667604-12029-1-git-send-email-phil.yang@arm.com> <1593667604-12029-4-git-send-email-phil.yang@arm.com> In-Reply-To: <1593667604-12029-4-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: arm.com; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(376002)(136003)(39860400002)(396003)(366004)(346002)(316002)(76116006)(71200400001)(9686003)(66946007)(52536014)(478600001)(7696005)(66556008)(66446008)(64756008)(66476007)(110136005)(86362001)(8936002)(2906002)(4326008)(54906003)(33656002)(26005)(5660300002)(4744005)(55016002)(8676002)(83380400001)(186003)(53546011)(6506007); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: DLmVwZFS0jy866usKs7zuLFpNgCj9NuHlzIMOj0XEfCxL0JDTHqpcXfwDPO7U0ZfkisOhv8Cu5+AQRJiaU3VUY3AdXGFzNlQiLrYxWo+4Kz/r5FROLVbsFFtOQLeBqEiNyDRr1N8dG/o+WK9TCowbQxQRcZsGaLrdzcxhOEf+DILX7VHWoW2mxGrnJXXBi7bjmAdHLLsVJ3ccwaPwHbybSu6cUKp6Sma20UjXZyVE7RZhnCy3tY9PSk2UNhJqkCY1VSJFHNA03DFoUlqfc5CLreDUzG9v4hdfpNa2Zrb38coyHujMXJHWZVGuAPqz4+OJwKxUxSEA06jmv5bF38xwD9TG31S6Ywj1l5P+xw2yW+2srQJoXYBRHGLkDC2AOQWADvqoAnL+CABIpPjt8kLa5iSscortYAtTGnvl9UQL21j1wIM+RVpHZsqTEBRXV550HVSK82RXPY55WwQNZ/Wa3Q0UBXaMimR/pDF5pAsqIU= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR1101MB2127.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0741cc3-abcb-4e4a-d265-08d81ec6c26c X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jul 2020 20:30:28.5935 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PqVV3eC7ozvpg+/nWMahG1XhIZ7X3ZR9lRj3mqnDDltAvwAm/cfIx91tho/Ysyc/DqXQhtPa9GUwpW++0yeYfW+QrGBZ0LGSDsdyXpgLU94= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1343 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> > -----Original Message----- > From: Phil Yang <phil.yang@arm.com> > Sent: Thursday, July 2, 2020 12:27 AM > To: Carrillo, Erik G <erik.g.carrillo@intel.com>; dev@dpdk.org > Cc: jerinj@marvell.com; Honnappa.Nagarahalli@arm.com; > drc@linux.vnet.ibm.com; Ruifeng.Wang@arm.com; > Dharmik.Thakkar@arm.com; nd@arm.com > Subject: [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics >=20 > The implementation-specific opaque data is shared between arm and cancel > operations. The state flag acts as a guard variable to make sure the upda= te of > opaque data is synchronized. This patch uses c11 atomics with explicit on= e > way memory barrier instead of full barriers rte_smp_w/rmb() to synchroniz= e > the opaque data between timer arm and cancel threads. >=20 > Signed-off-by: Phil Yang <phil.yang@arm.com> > Reviewed-by: Dharmik Thakkar <dharmik.thakkar@arm.com> > Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Erik Gabriel Carrillo <erik.g.carrillo@intel.com>