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Thu, 2 Jul 2020 20:21:59 +0000 From: "Carrillo, Erik G" To: Phil Yang , "dev@dpdk.org" CC: "jerinj@marvell.com" , "Honnappa.Nagarahalli@arm.com" , "drc@linux.vnet.ibm.com" , "Ruifeng.Wang@arm.com" , "Dharmik.Thakkar@arm.com" , "nd@arm.com" Thread-Topic: [PATCH v2 2/4] eventdev: use c11 atomics for lcore timer armed flag Thread-Index: AQHWUDGmP72+cIW5MkKY2EurAeEoH6j0vDMA Date: Thu, 2 Jul 2020 20:21:59 +0000 Message-ID: References: <1591960798-24024-1-git-send-email-phil.yang@arm.com> <1593667604-12029-1-git-send-email-phil.yang@arm.com> <1593667604-12029-2-git-send-email-phil.yang@arm.com> In-Reply-To: <1593667604-12029-2-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.55.52.205] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ddde5393-b7f0-4bad-e8ee-08d81ec592f8 x-ms-traffictypediagnostic: MWHPR1101MB2079: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6108; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR1101MB2127.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ddde5393-b7f0-4bad-e8ee-08d81ec592f8 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jul 2020 20:21:59.4342 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Rtdtb94YpbvjOAt/Tk4JqeHncmA6hiumWGa0tni/C4yTYFHgigF1doWeoqBvGIxMS2n3ExqhBTrWzZPGEgFDNLyEV6UVZB0dLFEx1UtaFKs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1101MB2079 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 2/4] eventdev: use c11 atomics for lcore timer armed flag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Thursday, July 2, 2020 12:27 AM > To: Carrillo, Erik G ; dev@dpdk.org > Cc: jerinj@marvell.com; Honnappa.Nagarahalli@arm.com; > drc@linux.vnet.ibm.com; Ruifeng.Wang@arm.com; > Dharmik.Thakkar@arm.com; nd@arm.com > Subject: [PATCH v2 2/4] eventdev: use c11 atomics for lcore timer armed f= lag >=20 > The in_use flag is a per core variable which is not shared between lcores= in > the normal case and the access of this variable should be ordered on the > same core. However, if non-EAL thread pick the highest lcore to insert ti= mers > into, there is the possibility of conflicts on this flag between threads.= Then > the atomic CAS operation is needed. >=20 > Use the c11 atomic CAS instead of the generic rte_atomic operations to av= oid > the unnecessary barrier on aarch64. >=20 > Signed-off-by: Phil Yang > Reviewed-by: Dharmik Thakkar > Reviewed-by: Ruifeng Wang Acked-by: Erik Gabriel Carrillo