From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BA3AA04B5; Mon, 26 Oct 2020 10:30:26 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1EEBC2BAF; Mon, 26 Oct 2020 10:30:25 +0100 (CET) Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com [216.228.121.65]) by dpdk.org (Postfix) with ESMTP id C5ED02B9D for ; Mon, 26 Oct 2020 10:30:22 +0100 (CET) Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 26 Oct 2020 02:30:00 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 09:30:20 +0000 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.172) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 09:30:20 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ItJ3LZ1hMLQX4aPUeMMjV61FmivrkDMHiSPKyBw2+H8hxZxA0jBVpsI5Dc3gwc+ESk+zygqcwF1nqYzM8lLTKDd5y3TjbTFfrP1Gtw6yAzRB5h0qlwS+WotElwcAHCMsog88A4DioUoll+CF2BXQTKv0gEKGtp9APWN0S9kxBC7NATe1V3FmOiBy7nG19PdOagAPckEYdhys9VrxrHDH4cPOWq38aSsDX4FIEXmpJKcAQctlwErhffY9Ny7FO2tZVpxo2RrMbGlznczJ8EB9qPzGWzdfdINwcFUTNf4P8eML8+WRujZVCD/an6qREKKECZ4isy+i6WG13QYbYIDrLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b0j8gRL8jWRLbjYWYO0D5S01QiMJcWfjVDgW/cjQrZ8=; b=EhJx56ZIIVOWM9HA/54/dVZSVkjr6WSpxIX+gtGUOCiaIOK6wX51KgR12bG5tLQRUhs2UrcPZ34ScmxzxC2Xs6Ysp0AgybUd+DM4SMlyFNGGIWHKSSLU4AYKmsJr/lc+4fUZFYVQuuSVnO5YJ4EV8iuCbAJqhsPMpfgrefffSTt0vX4TfN81IRmdBz7Si54thAhehhF5R43ZpvLLzCyHaHeUc2VUS05huYydLv6/6uw7klhuH98ORaiOu/XjF/GWOe0O4UJSxlPQaMIbA4Q5KLOiCoWA37A4jqprj5Ov+2v0/Jof3rz8OoZJBeIeXqTKbvNdw65SBXDqH03z/LidsA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from MWHPR12MB1501.namprd12.prod.outlook.com (2603:10b6:301:f::18) by MWHPR1201MB0062.namprd12.prod.outlook.com (2603:10b6:301:54::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.21; Mon, 26 Oct 2020 09:30:19 +0000 Received: from MWHPR12MB1501.namprd12.prod.outlook.com ([fe80::3ce6:9a73:3c99:2f35]) by MWHPR12MB1501.namprd12.prod.outlook.com ([fe80::3ce6:9a73:3c99:2f35%12]) with mapi id 15.20.3477.028; Mon, 26 Oct 2020 09:30:19 +0000 From: Slava Ovsiienko To: Bing Zhao , "viacheslavo@mellanox.com" , "matan@mellanox.com" CC: "dev@dpdk.org" , Ori Kam , "Raslan Darawsheh" Thread-Topic: [PATCH v2 5/6] net/mlx5: change hairpin ingress flow validation Thread-Index: AQHWqHyicf+Gtuv6X0+nwwyz8f7LNqmppCMw Date: Mon, 26 Oct 2020 09:30:19 +0000 Message-ID: References: <1602166620-46303-1-git-send-email-bingz@nvidia.com> <1603375597-430528-1-git-send-email-bingz@nvidia.com> <1603375597-430528-6-git-send-email-bingz@nvidia.com> In-Reply-To: <1603375597-430528-6-git-send-email-bingz@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [95.164.10.10] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 311fa2b8-dcd5-4e12-aeff-08d87991c17d x-ms-traffictypediagnostic: MWHPR1201MB0062: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2449; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: kfCZ1N21oYKfWvk9m3MQLgj0h2qYdoGxInB1x6qBqZfsqFyUnIc5oBtvlBfRme8AmIyHb5AyXVpqob8tnQLk5nzcdnBLNQf7khwLiPg493LqeSiNwAUzP2R8AQSjC7VGv2sJPzJzOH6kg0HIdUW2PRwziiHroBGLhZLylsDFhio762CXygXg5Y0UupUz1PMFrYgw9kI/h9xoSbRdTZlWGkeKHBFkF/u14shnLKOAPy8Eyfggi/MBWIBi4dBrHsFuBfawUzVPCnvDde2MZhqZdcVzbYVDsVphqV4ZsMonnk8zPOApog1XkY8zfTQJmPsHxDLnzrJw0g2Ac8JY8SMXDABg/U7qeagyX4hzdL6glSYGIgbzzGb2EK5v7Fw4uuNJ x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MWHPR12MB1501.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(136003)(346002)(376002)(396003)(39860400002)(9686003)(8936002)(4326008)(6506007)(7696005)(316002)(86362001)(66446008)(83380400001)(53546011)(107886003)(8676002)(64756008)(33656002)(2906002)(66476007)(71200400001)(52536014)(478600001)(110136005)(54906003)(26005)(66556008)(66946007)(186003)(76116006)(55016002)(5660300002)(309714004); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: 9klCVePUeP4eIfsBoWUrpFOIEmtMphP5/TVzdTcTsSZtxe2gG9hG9rO874WXB+nMtpKsrsSYjiubp61UznUNKdcOjsWYZa5RDOc6f6XYng+Vs+ZP1d1IRarJLGsLzG6pWDnzIaeI38UH5TgVvdoMiQQwDNsmnyEWioeERPPiFw+zJCjC3WysxJGzdsu90hNct5Xj8GJXP5y3qUh1oz07p/Ry3eawuQcUNuCF8uOJotIUO8U6hANMEqhc8FjU7VCa53tB9b7PYv4LskSGzcR7xSpJyxp5hIG+DYqj+6hYrKIBnzxVMJamphisV1ulx3BTWmjHEJvxONyEFl6Rb/r2UaC8PTti+MpXxCGx9HbIPax7ReaBCmcs8O++dl9hapuhX94A2piSJOQZHEDNraBI9cKkmI9bSII8G7JPxmlLz+7JYSb5lPUf+e2t3nufMZdbtoDZp8opgsjtqGVXBwRQvsvKyhAO8UgnFfc2Eug6H1sKmu+9UTmgjfXl7C5SYy8ZmrDtAtNEJXT5wpE8WyYYVBeFNYebMbSSm5Q7h5MkzRn2McahTaCoN4ujPxuaLBln49oCuplszUxSN5ONmDFGgJ4oQIbs1FcsQoKpBqn2Co3MrWSX7Q/bw4KLYS4o6bUDSaCpviVFblUivM/5ujECgg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR12MB1501.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 311fa2b8-dcd5-4e12-aeff-08d87991c17d X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Oct 2020 09:30:19.4734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vHVEa3WZh7BxHeyXmhpyJTMOIATXQuA50Ng+7kQ4MvCXx4M0VRnOzXpjCAcmtYmszI2Ggq0VuTU6kVRiDeASkg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0062 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603704600; bh=b0j8gRL8jWRLbjYWYO0D5S01QiMJcWfjVDgW/cjQrZ8=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To: CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References: In-Reply-To:Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ms-exchange-transport-forked: x-microsoft-antispam-prvs:x-ms-oob-tlc-oobclassifiers: x-ms-exchange-senderadcheck:x-microsoft-antispam: x-microsoft-antispam-message-info:x-forefront-antispam-report: x-ms-exchange-antispam-messagedata:Content-Type: Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=arc4a4Sgc8oRg3F426ow4Ypk0LTtY26kVJZGHnXra0BVLNL5SCVdXiPOK8+aKfk1g fEi1paiTrzdtbP8h++sl9SGX0jtQbTq3DXO7tPSA+RlL9bQTVc8Iwm6D5LHPPVAp99 Y850cZt2nGmfopR6idvbVLTbbME5gNMSX+I+1BVAJQhdfD4V0BIVL4jdQm0I1VM7Kw vYkoj2BIVmVDKO/dKWGpF7mTiddcq1SiJadT0tsOJt8AUqA/eCvARgxVB36Hwk6xq/ Zz7/f8icTtolhkjaMWKfsUnX1dgfPnSSVD/04CHx9+pwQa/Mo5S9s1KzsKgt9No6zd 22YPMIFycSviQ== Subject: Re: [dpdk-dev] [PATCH v2 5/6] net/mlx5: change hairpin ingress flow validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Bing Zhao > Sent: Thursday, October 22, 2020 17:07 > To: viacheslavo@mellanox.com; matan@mellanox.com > Cc: dev@dpdk.org; Ori Kam ; Raslan Darawsheh > > Subject: [PATCH v2 5/6] net/mlx5: change hairpin ingress flow validation >=20 > In the current implementation of the single port hairpin, there is a impl= icit > splitting process for actions. When inserting a hairpin flow, all the act= ions will > be included with the ingress attribute. > The flow engine will check and decide which actions should be moved into = the > TX flow part, e.g., encapsulation, VLAN push. >=20 > In some NICs, some actions can only be done in one direction. Since the > hairpin flow will be split into two parts, such validation will be skippe= d. >=20 > With the hairpin explicit TX flow mode, no splitting is needed any more. = The > hairpin flow may have no big difference from a standard flow (except the > queue). The application should take full charge of the actions and the fl= ow > engine should validate the hairpin flow in the same way as other flows. >=20 > In the meanwhile, a new internal API is added to get the hairpin configur= ation. > This will bypass the useless atomic operation to save the CPU cycles. >=20 > Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow_dv.c | 15 ++++++++++++--- > drivers/net/mlx5/mlx5_rxq.c | 27 +++++++++++++++++++++++++++ > drivers/net/mlx5/mlx5_rxtx.h | 2 ++ > 3 files changed, 41 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 15cd34e..d5be6f0 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -6058,11 +6058,17 @@ struct field_modify_info modify_tcp[] =3D { > actions, > "no fate action is found"); > } > - /* Continue validation for Xcap and VLAN actions.*/ > + /* > + * Continue validation for Xcap and VLAN actions. > + * If hairpin is working in explicit TX rule mode, there is no actions > + * splitting and the validation of hairpin ingress flow should be the > + * same as other standard flows. > + */ > if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS | > MLX5_FLOW_VLAN_ACTIONS)) && > (queue_index =3D=3D 0xFFFF || > - mlx5_rxq_get_type(dev, queue_index) !=3D > MLX5_RXQ_TYPE_HAIRPIN)) { > + mlx5_rxq_get_type(dev, queue_index) !=3D > MLX5_RXQ_TYPE_HAIRPIN || > + !!mlx5_rxq_get_hairpin_conf(dev, queue_index)->tx_explicit)) { > if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) =3D=3D > MLX5_FLOW_XCAP_ACTIONS) > return rte_flow_error_set(error, ENOTSUP, @@ - > 6091,7 +6097,10 @@ struct field_modify_info modify_tcp[] =3D { > "multiple VLAN actions"); > } > } > - /* Hairpin flow will add one more TAG action. */ > + /* > + * Hairpin flow will add one more TAG action in TX implicit mode. > + * In TX explicit mode, there will be no hairpin flow ID. > + */ > if (hairpin > 0) > rw_act_num +=3D MLX5_ACT_NUM_SET_TAG; > /* extra metadata enabled: one more TAG action will be add. */ diff -- > git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index > 78e15e7..d328d4a 100644 > --- a/drivers/net/mlx5/mlx5_rxq.c > +++ b/drivers/net/mlx5/mlx5_rxq.c > @@ -1720,6 +1720,33 @@ enum mlx5_rxq_type > return MLX5_RXQ_TYPE_UNDEFINED; > } >=20 > +/* > + * Get a Rx hairpin queue configuration. > + * > + * @param dev > + * Pointer to Ethernet device. > + * @param idx > + * Rx queue index. > + * > + * @return > + * Pointer to the configuration if a hairpin RX queue, otherwise NULL. > + */ > +const struct rte_eth_hairpin_conf * > +mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) { > + struct mlx5_priv *priv =3D dev->data->dev_private; > + struct mlx5_rxq_ctrl *rxq_ctrl =3D NULL; > + > + if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) { > + rxq_ctrl =3D container_of((*priv->rxqs)[idx], > + struct mlx5_rxq_ctrl, > + rxq); > + if (rxq_ctrl->type =3D=3D MLX5_RXQ_TYPE_HAIRPIN) > + return &rxq_ctrl->hairpin_conf; > + } > + return NULL; > +} > + > /** > * Get an indirection table. > * > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h = index > b50b643..d91ed0f 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.h > +++ b/drivers/net/mlx5/mlx5_rxtx.h > @@ -344,6 +344,8 @@ uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, int > mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); int > mlx5_hrxq_verify(struct rte_eth_dev *dev); enum mlx5_rxq_type > mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); > +const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf > + (struct rte_eth_dev *dev, uint16_t idx); > struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); voi= d > mlx5_drop_action_destroy(struct rte_eth_dev *dev); uint64_t > mlx5_get_rx_port_offloads(void); > -- > 1.8.3.1