From: Chao CH Zhu <bjzhuc@cn.ibm.com>
To: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
Date: Thu, 16 Oct 2014 11:14:02 +0800 [thread overview]
Message-ID: <OFCD69120A.E4F3D7D4-ON48257D73.0011507B-48257D73.0011E4AC@cn.ibm.com> (raw)
In-Reply-To: <2601191342CEEE43887BDE71AB97725821393C8F@IRSMSX105.ger.corp.intel.com>
Konstantin,
In my understanding, compiler barrier is a kind of software barrier which
prevents the compiler from moving memory accesses across the barrier. This
should be architecture-independent. And the "sync" instruction is a
hardware barrier which depends on PowerPC architecture. So I think the
compiler barrier should be the same on x86 and PowerPC. Any comments?
Please correct me if I was wrong.
Thanks a lot!
Best Regards!
------------------------------
Chao Zhu
From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
Date: 2014/10/16 08:38
Subject: RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM
Power architecture
Hi,
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> Sent: Friday, September 26, 2014 10:36 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power
architecture
>
> The atomic operations implemented with assembly code in DPDK only
> support x86. This patch add architecture specific atomic operations for
> IBM Power architecture.
>
> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
> .../common/include/powerpc/arch/rte_atomic.h | 387
++++++++++++++++++++
> .../common/include/powerpc/arch/rte_atomic_arch.h | 318
++++++++++++++++
> 2 files changed, 705 insertions(+), 0 deletions(-)
> create mode 100644
lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> create mode 100644
lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
>
...
> +
> diff --git
a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> new file mode 100644
> index 0000000..fe5666e
> --- /dev/null
> +
...
>+#define rte_arch_rmb() asm volatile("sync" : : :
"memory")
>+
> +#define rte_arch_compiler_barrier() do { \
> + asm volatile ("" : : : "memory"); \
> +} while(0)
I don't know much about PPC architecture, but as I remember it uses a
weakly-ordering memory model.
Is that correct?
If so, then you probably need rte_arch_compiler_barrier() to be "sync"
instruction (like mb()s above) .
The reason is that IA has much stronger memory ordering model and there
are a lot of places in the code where it implies that ordering.
For example - ring enqueue/dequeue functions.
Konstantin
next prev parent reply other threads:[~2014-10-16 3:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-26 9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
2014-09-29 6:16 ` Hemant
2014-09-29 6:41 ` Chao CH Zhu
2014-10-16 0:39 ` Ananyev, Konstantin
2014-10-16 3:14 ` Chao CH Zhu [this message]
2014-10-16 9:42 ` Richardson, Bruce
2014-10-16 11:04 ` Ananyev, Konstantin
[not found] ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
2014-10-16 10:59 ` Ananyev, Konstantin
2014-09-26 9:36 ` [dpdk-dev] [PATCH 03/12] Add byte order " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 04/12] Add CPU cycle " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 05/12] Add prefetch operation " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 06/12] Add spinlock " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 07/12] Add vector memcpy " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 08/12] Add CPU flag checking " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
2014-10-06 22:03 ` Cyril Chemparathy
2014-10-07 14:46 ` Ananyev, Konstantin
2014-10-13 2:33 ` Chao CH Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
2014-09-29 6:21 ` Hemant
2014-09-26 9:36 ` [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture Chao Zhu
2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
2014-11-13 10:31 ` Chao Zhu
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