From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E3FD43C35; Thu, 29 Feb 2024 10:48:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1BB8C402BB; Thu, 29 Feb 2024 10:48:34 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by mails.dpdk.org (Postfix) with ESMTP id EA35E402B4 for ; Thu, 29 Feb 2024 10:48:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709200113; x=1740736113; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=hdD4P892AdLbrlp9bqBRSAmdC9p4X4h/0DybFEEqJFw=; b=dApN/IaQdENZAVsBXEi61zFaEUhaMz1JIZdQsiyWHL2bHCmS0/c5xeon V3xc2JxC2/lZrqy3GTHHXaAOW8jui03yOde+kxacM0rhQcvghnaYBFygK 4+7Ml6U208YBej8Z9fdYiyhKUKkNwjawRKLWb0C+AsUAzKqDg648xYPid VTwa+XsVTwdHjSM2RJ8nE/tzdOla1rrz4VnOohXrVj9251PAwDaspdllQ wbiRaHnTd4tdReiEZL6KUXwOff6+Fg0PIES1uOy7rq+K/WmVfJ6snYTBv DgGYxc0zSIqXgQotX9qRDTNj9Ygxd31OfFiimBz851BY83bzgY7ioq73I w==; X-IronPort-AV: E=McAfee;i="6600,9927,10998"; a="15099505" X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208,217";a="15099505" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Feb 2024 01:48:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208,217";a="12379583" Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16]) by fmviesa004.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 29 Feb 2024 01:48:32 -0800 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 29 Feb 2024 01:48:31 -0800 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 29 Feb 2024 01:48:31 -0800 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.169) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Thu, 29 Feb 2024 01:48:30 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gihr6sewL7afxOJC1iuCnUFOKbzBMFPyWH3ZXLptZIS7bJ0C7iVGv9rjuGwcHf77w/5U9ga3/H5Jj5Nhd8khch4gQMmbSUsbVAfR/fvajBJYa3HrOhBJiIJYv5XMmq4gjST72FY4b65vj4Xy8UaOSqOk7s1t2YMPMynJBcgDqzwKriqiPxlb78Azm5magdavJvVAW+jPqbI/tNQtVCEw5cXgviDM3m8NOkH13MuQ/XJJWTPDhfxD75cOmRZhZptI0yIBiV/OOCRtU1tioRUv20pmKKNmmYQlw/4KAxxNZL+rooNH2ll36uoBJAJ9g7sT93ayp8n+cIi6uPq76ZCtrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P/LA7gIypkBAGZI6CY0AptSfi0DToyRIkTqcQ/YCWBM=; b=k7Nu3BR2ES/gQWsDOzZO4u6/NdiBHvSjLVY6SVKiEW6lk9YqaFj95Rx2isZlMbNJdTjCKEaQ7thJilLCFEStuZ2BaxFwOfQ3/hTZxJcIJo9rTYK4C43XP+hXYb9TZDBBc0aazXD2eBR+HuKHsWIsMNOWBaXEQLfQZeOh+bg40u6sLSsILV4V5OvUk7dS3lWdrfYpp9zjzgvjqFt2FjNovC0+xY0DC5hfCclXT/QjI9hkr7Y0HHKWsDEOl79fc85bQAlWg2Im8sVMWXJRcA/bCH6yvHFwgg96HxPPbijXAZcBg8qd0SiffBHP2kry/qK8IL0xmhzOXF1E2onzKBo5jQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from PH0PR11MB5013.namprd11.prod.outlook.com (2603:10b6:510:30::21) by PH7PR11MB8121.namprd11.prod.outlook.com (2603:10b6:510:234::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.22; Thu, 29 Feb 2024 09:48:28 +0000 Received: from PH0PR11MB5013.namprd11.prod.outlook.com ([fe80::930a:d9e3:60ef:a659]) by PH0PR11MB5013.namprd11.prod.outlook.com ([fe80::930a:d9e3:60ef:a659%4]) with mapi id 15.20.7339.022; Thu, 29 Feb 2024 09:48:28 +0000 From: "Kusztal, ArkadiuszX" To: "Ji, Kai" , "Power, Ciara" , "dev@dpdk.org" CC: "gakhil@marvell.com" Subject: RE: [PATCH v2 0/4] add new QAT gen3 and gen5 Thread-Topic: [PATCH v2 0/4] add new QAT gen3 and gen5 Thread-Index: AQHaZmrSN26FtfebQ02V43HLvnI/B7Eco6MAgAR4VgA= Date: Thu, 29 Feb 2024 09:48:28 +0000 Message-ID: References: <20231219155124.4133385-1-ciara.power@intel.com> <20240223151255.3310490-1-ciara.power@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5013:EE_|PH7PR11MB8121:EE_ x-ms-office365-filtering-correlation-id: c2537637-b8ef-4111-15cb-08dc390b9500 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: lUx5i8MJSAkSN5mPaoPuME0YwIiCrgYqmNOmkaAgMtLjJB7qXlje6Rw4osna3S9iBGVijb4iNYozOuGH+a728q9DrFHig0E2MrHTi2BhCrlj3ZGiiLz+7Bn43xyYFRD9/65GYKMok4GEmDJ6xqyE1iRKRjp5Em+qCuloeAbGWJ0F3SZPwPKhclKlg2OSzX9TeBBtJbsYG8R4T+nMNgDQauIBvYl2WpBbViM6FTcN9/bLWhDqbPDB3jfOJyxnmNjm2ICd6Dlaf803N219XruRupjKIFuNJBVWK8cKJJZ7DfW1kXzNKYvqKkjuCPxrc/fsY4K66PfD/q0MohI9GL2sb3P9IUDX8SCfWiPDm9xzBnucHhqBsPy9cP9Ydz9n8k8o/9hr/2LPG/Hb2Gt7aZ0i2Mh080PKpyyNzSrvIN1R794oRoDyhZZY6U/OVdv3ky0qZtCrvqHbFPioHiY53qpKGi74rveWFargkxlSahkN4WeiAcFQpI/W1JGGB1wJdOR7nzk8nLGSHvVneIsNpK3S7MuhB8ogsfru+7bvntOfoTWPjoG2PbQ7Cju2c+nmBDRpaYlxSy1jEYzm80TKi+YnOb4KQqvhPd8SORp4jYlZpEItn9670sWxRONGCryMhIsXmr27JP17Az1G1KiRQ4dQ9J0VDtdH8xZt3+01vZ3r8LnBuJaFZhBJFvSLEiD3UE7Ik6pNqFiC3/792LrZdrkDO1TAz5VZP2BAPxaxWtgthy4= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PH0PR11MB5013.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(38070700009); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?ilzSq5BDAIPR+mFp3fGJ6xuVWjnM+IztYnXz6K9KqWXqNOmhFSDbhqQCiD+5?= =?us-ascii?Q?l87mMKlbfnM0blkToB6ubg5GWlXPdXWvx3W4x0t4Shy73tP6vZ09+0/aLv0s?= =?us-ascii?Q?o6QelWhVjYsidor6BBUSD3YH4k97HPeFLgs781zR29eOADhS7Lo/JEdRSCCI?= =?us-ascii?Q?bEZ8zwCGigXd2sLe/Am1F+arQYrTwulMJhhHRBZQr2dnyOrTaelx2J0v7gdl?= =?us-ascii?Q?q08Uincm5MmPXpWBHB04XR4+GCwHp5e64DfoJLz1HrO6ytcVZbig4wuZj9Fv?= =?us-ascii?Q?+AnRpBWfEjbh0eU1OrRJhyPOV1bQRnaZSAlVWJFgwgNilEYVXZpfBvbU68VO?= =?us-ascii?Q?1jPcK+rC58uUucLXWt9RJSGIBHWD7JBlxqHIdUIoOl3/kEN1KmXrcPzEtDIz?= =?us-ascii?Q?YBX8jlCoynkhct2lJa5q338iP3DpnqDZ0RviLb8w0JYp0YlM4NNiGzQ3kMxC?= =?us-ascii?Q?TNvZrqrv/FWbmBbi7lvc88YBAX16CrigNatLaonjTjalDCiWuVEicix+5XTq?= =?us-ascii?Q?fR7ysXsKgUEUmjDop3jR+0eI56dFc4KPPB8e3IElqSwAeXwOCWiXqkUtEfiG?= =?us-ascii?Q?WDh/4Mv8Pn7NygdUJrMmpl/AiMDSNiefqIACibd/OE8vs0WbTRIzTTHVE65p?= =?us-ascii?Q?cubcJE6RDnLplPO6rC59wOEk1zL7IgAurShzWiMcvmtQsDO9G816G9Fsn5S3?= =?us-ascii?Q?MrQ5BIgclHk7zUGeuD+cTEKzHMaBgVZCKsEr9tIbYEb6gWymifI1HHu4Tm4k?= =?us-ascii?Q?BhwbZzyS+mRPsNXcm6BlF4pfkLWfMEGRZcdBmpU/rSDF9oZD+a4Jy0VfWC0V?= =?us-ascii?Q?SOg/LDTb6wvCShN3dWYD77Qwka7WjIZnLbn0qN3vgFwkebtcIksh/FSzOVdi?= =?us-ascii?Q?K/AGV/bQrespHHuH94a87bUfaLCi0nxQih0poEW1+IZlfjKfWxjdz4ReQE/L?= =?us-ascii?Q?yhF1Ao9iqWn9bjwK1Zq0lPQxUjj2PwlK1cI9QKYedHWlJmU1zTZiO0j/l2hP?= =?us-ascii?Q?PTtw08zlGDzLgVy05DoD/lI5O5/varJm3XNKL+Se54LzELYBy28jr9yv1x5m?= =?us-ascii?Q?B97Gi+/2Fx2Hg6dIqn0sD4ajvE+IgczFN7c34BGkU08SMYfVEdXD8cE++6p7?= =?us-ascii?Q?uCWUSX5PYwjjudqUoTbjEoNhdFIkdoD5QzAFkqZLo+PLNWmLJdFZZRtrgkRI?= =?us-ascii?Q?c7qlBb8DNNfitlJpe5ayPGWumLPRS369i6w+DjYZ3DPssfpMB6aksuP+kJ7Y?= =?us-ascii?Q?CHe+PRkB5CNxjQgVl9WkT1rE6IxhzFKuRA/qOxumGm5TKLSCLh3boWaYBjL5?= =?us-ascii?Q?XiK9tKGTb2qjGv5TwkfWd8HvPy8s4L07JdducpXV9J9nc9jSEbzXmKyBi0N6?= =?us-ascii?Q?R0l3/4lAXCgZvEvhfieLARvitXP8XmiwvCi31uMSU8SO809dHtEv1T4xTWzS?= =?us-ascii?Q?9sN0bszspDw+RNCrQm7XCc+dXrcVNnzIL3PajySHY6VLtNJ8p6LlMG/7VDOt?= =?us-ascii?Q?k4so5ZvZoWVu1/kXV2d5JJEWVHUXvLQiq+NYvG/a4Mp0qDnIUeq/bsryrrIx?= =?us-ascii?Q?kUy3/o4/KzPspsh7SwjuZdGOvxFkQO0k9v3Hv++A4EWcxJfBxK6IJweRpUo4?= =?us-ascii?Q?Xg=3D=3D?= Content-Type: multipart/alternative; boundary="_000_PH0PR11MB50130743BB29394F20E4CAFB9F5F2PH0PR11MB5013namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5013.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c2537637-b8ef-4111-15cb-08dc390b9500 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Feb 2024 09:48:28.6491 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Yll51dS+heZjSuI6GcLDnf2Cm7nnztQKS6IOUKdfEMOqXgB2AuKgglf0+5s6negCEeZEnVCtofoIyTjuytqVrM3xNun6Zo/2Y97PKHDkNHs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB8121 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --_000_PH0PR11MB50130743BB29394F20E4CAFB9F5F2PH0PR11MB5013namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Series-acked-by: Arkadiusz Kusztal arkadiuszx.kusztal@intel.com Series-acked-by: Kai Ji > ________________________________ From: Power, Ciara > Sent: 23 February 2024 15:12 To: dev@dpdk.org > Cc: gakhil@marvell.com >; Ji, Kai >= ; Kusztal, ArkadiuszX >; Power, Ciara > Subject: [PATCH v2 0/4] add new QAT gen3 and gen5 This patchset adds support for two new QAT devices. A new GEN3 device, and a GEN5 device, both of which have wireless slice support for algorithms such as ZUC-256. Symmetric, asymmetric and compression are all supported for these devices. v2: - New patch added for gen5 device that reuses gen4 code, and new gen3 wireless slice changes. - Removed patch to disable asymmetric and compression. - Documentation updates added. - Fixed ZUC-256 IV modification for raw API path. - Fixed setting extended protocol flag bit position. - Added check for ZUC-256 wireless slice in slice map. Ciara Power (4): common/qat: add new gen3 device common/qat: add zuc256 wireless slice for gen3 common/qat: add new gen3 CMAC macros common/qat: add gen5 device doc/guides/compressdevs/qat_comp.rst | 1 + doc/guides/cryptodevs/qat.rst | 6 + doc/guides/rel_notes/release_24_03.rst | 7 + drivers/common/qat/dev/qat_dev_gen4.c | 31 ++- drivers/common/qat/dev/qat_dev_gen5.c | 51 ++++ drivers/common/qat/dev/qat_dev_gens.h | 54 ++++ drivers/common/qat/meson.build | 3 + drivers/common/qat/qat_adf/icp_qat_fw.h | 6 +- drivers/common/qat/qat_adf/icp_qat_fw_la.h | 24 ++ drivers/common/qat/qat_adf/icp_qat_hw.h | 26 +- drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 19 ++ drivers/common/qat/qat_device.h | 2 + drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 8 +- drivers/compress/qat/dev/qat_comp_pmd_gen5.c | 73 +++++ drivers/compress/qat/dev/qat_comp_pmd_gens.h | 14 + drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 7 +- drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 63 ++++- drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 4 +- drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 +++++++++++++++++++ drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 40 ++- drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 43 +++ drivers/crypto/qat/qat_sym_session.c | 177 ++++++++++-- drivers/crypto/qat/qat_sym_session.h | 2 + 24 files changed, 889 insertions(+), 51 deletions(-) create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c -- 2.25.1 --_000_PH0PR11MB50130743BB29394F20E4CAFB9F5F2PH0PR11MB5013namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Series-acked-by: Arkadiusz Kusztal arkadiuszx.kusztal@intel.com

 

Se= ries-acked-by: Kai Ji <kai.ji@intel.= com>

 

From: Power, Ciara <ciara.power@intel.com>
Sent: 23 February 2024 15:12
To: dev@dpdk.org <dev@dpdk.org>
Cc: gakhil@marvell.com <= ;gakhil@marvell.com>; Ji, Kai = <kai.ji@intel.com>; Kusztal, = ArkadiuszX <arkadiuszx.k= usztal@intel.com>; Power, Ciara <ciara.power@inte= l.com>
Subject: [PATCH v2 0/4] add new QAT gen3 and gen5 =

 

This patchset adds su= pport for two new QAT devices.
A new GEN3 device, and a GEN5 device, both of which have
wireless slice support for algorithms such as ZUC-256.

Symmetric, asymmetric and compression are all supported
for these devices.
 
v2:
  - New patch added for gen5 device that reuses gen4 code,
    and new gen3 wireless slice changes.
  - Removed patch to disable asymmetric and compression.
  - Documentation updates added.
  - Fixed ZUC-256 IV modification for raw API path.
  - Fixed setting extended protocol flag bit position.
  - Added check for ZUC-256 wireless slice in slice map.

Ciara Power (4):
  common/qat: add new gen3 device
  common/qat: add zuc256 wireless slice for gen3
  common/qat: add new gen3 CMAC macros
  common/qat: add gen5 device

 doc/guides/compressdevs/qat_comp.rst     &nb= sp;   |   1 +
 doc/guides/cryptodevs/qat.rst      &nbs= p;         |   6 +
 doc/guides/rel_notes/release_24_03.rst     &= nbsp; |   7 +
 drivers/common/qat/dev/qat_dev_gen4.c     &n= bsp;  |  31 ++-
 drivers/common/qat/dev/qat_dev_gen5.c     &n= bsp;  |  51 ++++
 drivers/common/qat/dev/qat_dev_gens.h     &n= bsp;  |  54 ++++
 drivers/common/qat/meson.build      &nb= sp;        |   3 +
 drivers/common/qat/qat_adf/icp_qat_fw.h     = |   6 +-
 drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  24 ++<= br>  drivers/common/qat/qat_adf/icp_qat_hw.h     = |  26 +-
 drivers/common/qat/qat_common.h      &n= bsp;       |   1 +
 drivers/common/qat/qat_device.c      &n= bsp;       |  19 ++
 drivers/common/qat/qat_device.h      &n= bsp;       |   2 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c |   8 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen5.c |  73 +++++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  14 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   7 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  63 ++++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |   4 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 ++++++++++++++++++= +
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  40 ++-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    |  4= 3 +++
 drivers/crypto/qat/qat_sym_session.c     &nb= sp;   | 177 ++++++++++--
 drivers/crypto/qat/qat_sym_session.h     &nb= sp;   |   2 +
 24 files changed, 889 insertions(+), 51 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c

--
2.25.1

--_000_PH0PR11MB50130743BB29394F20E4CAFB9F5F2PH0PR11MB5013namp_--