From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7457542BDA; Tue, 30 May 2023 05:30:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 03C4140F18; Tue, 30 May 2023 05:30:55 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 023B3406BC for ; Tue, 30 May 2023 05:30:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685417452; x=1716953452; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=UtjEjVma4hF2wv93PBo3horILTkfk74i8uoPxEIHMs8=; b=Y4xFxFLHmyi+tlOy8tXJ4b/8ijsQNIwdvOYw2x6WrBviHZ3iwJUU/ktq yit0EqkAGEWN+5diKmYNwrpQ7BWhL4B8pp5r769lh/MBpQC4mnx/1odWv ECEAcKLYoic540RYiIfx4uNjBwm1gUKxGefdyolT7xbXISpDVyBxrUvfx TtuerATMk0iXVXgLzAR8K9tQmlnz8Vq7ipHpip0hUJUD73hV6a+kDhBod GV7QengxxTYa5FNnp8GZUYIb1iUK+wE5Li3Vbi9CokPSanlArvYhDpZHa HMcxLb9VKwd3AuVGmA1VPs4rCFxt2o93Rg3cWwXjBDAz7VzeMZYJIlBBE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="357181750" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="357181750" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2023 20:30:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="739341935" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="739341935" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga001.jf.intel.com with ESMTP; 29 May 2023 20:30:49 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Mon, 29 May 2023 20:30:48 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 20:30:48 -0700 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.44) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.23; Mon, 29 May 2023 20:30:48 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=V01HkHxoZ44bja4Mfr0DzHOoJq1MYJg1ACQsoVvWMzfSrDW1+4MShQZQwumohMoQvyz2sDzVBmNQxb0hZkqFp0MJNqLDID+ECPmUOrOA9eWOb4Jq9knncTpg192PdPQe5IrvGt4lNKolUPSZE90NXjQBEyIyXHqqAT+u78yueY/WMXS6/RA8mH12cuwGi0rKhoJQw/Dji0thr3XV6cT051GKqTu45cgRSg2f7fgf5wBBQWziXLvoYYPxrpfLwM0xLe39Si6n6wG7iS8IBi4wC1zzr6bg1iil6D2wtER33CyGnbg1B6MvaachKRqirCGFe7KFthxKlav6K9Dedtb4KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CB+WB6zukMj0Qg/v6ulaG12yJKMMMhbEivgZHeA0rww=; b=SD7apU7dnhRllOt5kxBDgP3xXkTV9oS1tbI63cNYgxaTyth8Qk2sQXOj7CCcqDB2XpAQVnwNXM2N0vjfCDmsapitu4L64ijau9OBcjD+CHX1KMI200f9eBtqDBMW7932fTsLpbXnSCeicSsDtK1phODzRUo98dQJSP8bz/CO+aEjDPiAEQIDDeZISqRXDvv92IALMALQW86mW4qAWKoUeyEcZqcgoteANTNffgfUSiEh4gJzlrAhC9tIq0pXGyRRYbAYbtYiid1e6JQ0skpEi/MACB5hxpjgnVS/m6Q432ifYAHS0evxd+1HmxygHDsZ9nlFGi9pECImt2NnJ3xONQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from PH0PR11MB5877.namprd11.prod.outlook.com (2603:10b6:510:141::12) by DS0PR11MB7579.namprd11.prod.outlook.com (2603:10b6:8:14d::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.23; Tue, 30 May 2023 03:30:41 +0000 Received: from PH0PR11MB5877.namprd11.prod.outlook.com ([fe80::da1b:ee87:709:3174]) by PH0PR11MB5877.namprd11.prod.outlook.com ([fe80::da1b:ee87:709:3174%4]) with mapi id 15.20.6433.018; Tue, 30 May 2023 03:30:41 +0000 From: "Liu, Mingxia" To: "Xing, Beilei" , "Wu, Jingjing" CC: "dev@dpdk.org" , "Wang, Xiao W" Subject: RE: [PATCH v4 09/13] net/cpfl: support hairpin queue start/stop Thread-Topic: [PATCH v4 09/13] net/cpfl: support hairpin queue start/stop Thread-Index: AQHZj6h6amjkWFLDckuvkPqEMnW4ca9yKWlw Date: Tue, 30 May 2023 03:30:40 +0000 Message-ID: References: <20230519073116.56749-1-beilei.xing@intel.com> <20230526073850.101079-1-beilei.xing@intel.com> <20230526073850.101079-10-beilei.xing@intel.com> In-Reply-To: <20230526073850.101079-10-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5877:EE_|DS0PR11MB7579:EE_ x-ms-office365-filtering-correlation-id: cdd0e15c-1a83-4d41-733c-08db60be3e5b x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: cblH4TqinQ5hxxG2I7F2/WX91BCG/GPJANSbU/st684nas6CYzHnAPIX8LPzIM+pMTJYpj89qFODZqKDwrGS4Xr4RZjbnx4f0du/bDqbi6MxbXbiAFr873HR7aJ8lqdFR4whAHeRoRI/EHFueX+fo087DpIj1/nAaH3c/3kpi0KY1vK0gQ+Kb9snrEFBxzmGO4gOJf2S5i9ScX4cYodkpaKOC3iFrH7Df4CiXf74JTFgNutMe/7F1OpkMLxoiBpqB0rmycCEdICoTdNcelh1xD0r1C8aq+Bu60xC6UdgObuIUhAU6AlyAk20MI8jJxAwpcQAbLJNaIq2w6tlckt1GKmUy/hwhQNnfkG8+k28SuxLL5R2vCz9FbjIr4xOOjgixUdrfqBlp4p9RfLrlUeJeexgPWbyQ3HXdpq/DtVxkfQiEQAF79zRVC7It09nb0kGVbog2Zo3aa+Uc5KENkzM4WTrZqpId8OyTNCw3d/zQZL0fY2jfyQe1Le02PZZ4MM84SW20+ln1GQmQFpD5d8UhxrpNAquHYOBSuo6N3Nj0DaEiHOXGrdxipCeTuK5Ea1BtimhhpQ5BQci5zb/wyvmETlb/Sy9Mg3UZimw0Ap07zTdud7zBT20KJWSZ1Ijo98v x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PH0PR11MB5877.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230028)(376002)(396003)(39860400002)(346002)(136003)(366004)(451199021)(7696005)(86362001)(38070700005)(41300700001)(4326008)(55016003)(6636002)(316002)(71200400001)(33656002)(66446008)(66476007)(66556008)(64756008)(66946007)(76116006)(107886003)(52536014)(5660300002)(186003)(2906002)(30864003)(53546011)(9686003)(26005)(6506007)(83380400001)(38100700002)(478600001)(54906003)(8936002)(110136005)(8676002)(122000001)(82960400001); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?uOTuGdSlLgEIRbiKDhc2FnNmidqdFq9CfCqMuiYPlsqzEyjs3EjjkfoYMvKs?= =?us-ascii?Q?K0o5A76jvuvFB+FdgCc9WK/Witggwz/6QXIAv+v76a+3QCSgAW1G3fjDyaab?= =?us-ascii?Q?4iEki9+MZcPyQQswqzpavkk2JqCZXiHLIKyk45X6J1XqTRIcUkQVAKXUg6oU?= =?us-ascii?Q?9Wg1ZJZIK7xwcrXtdxTBR+XzJ/ak9jOSKObsTNS6Jme5h0zdAsD9efyUhaXl?= =?us-ascii?Q?FDNacEHiZoOwAzeMg8at5e2qBeYtrCpE3twnwhtuArxR8PM7WA7Q7lpOFlJl?= =?us-ascii?Q?FcPcD43731oo36KInG+gsOq7IuAG0a2vnTWO2rG3zWwGEqvQwJQgwKrJ21GT?= =?us-ascii?Q?t9ZWzreOmICuLWhCE4t1iwuiJcuFOLvYK+FfmUqA0PsNxzEvhcuMKWhiJB+X?= =?us-ascii?Q?0nOMsQWNYAiu3bn+2oHpRTGQMqQQsZHI8dOM1ZD5/hhYJI5How1eAX5VdYA2?= =?us-ascii?Q?rYYw4QkY0nc8KxuLcoIlrLDYjKSYWq2qDGcg3VFqyC6VP2AC0KcMI0LtItiO?= =?us-ascii?Q?IWJeC3nnoWbp4t0+du2UxmDEQqII+BynrVAmMIJAPVfKs426/VzIZcYSVKWw?= =?us-ascii?Q?Z3mC8N01WxEzm2q+Zvg9EvukR0ZcgkxnG/unQu5Mpt16JHcRIXtTG0ZkHt/M?= =?us-ascii?Q?HqXzBRZBH8zBpag1iXlqY1i/YBpFTdUgcIiapolYlSqrQ8kA8eBam1hXshLc?= =?us-ascii?Q?3Zt7eTtUVpGiZwWiegbtsfyqnTbnUBl5k2uwgfFRx/cYhK29SyzjPMNRSIqL?= =?us-ascii?Q?9ndlu6bljRsH5hJ3RvA0P2RX0eo483MOyqaba9cr89HW+87S43+uM3+mL4Al?= =?us-ascii?Q?SBEx7UPts1G6IiA5MyPP1scgD4R3rhCahajkwwTehHSVLQN9tXlDXNg5ewRM?= =?us-ascii?Q?Ai9Q/kZjD8MSrK7KiaVRh22rXtlCHrMhlT6YZp4o3btho/U1tJiOdF0tal/L?= =?us-ascii?Q?HFsEJ4rpixaH9qPbXqkcqkwdrTpIah5BQkIn5QNZZEVI7dJUhXlvBi3A6So6?= =?us-ascii?Q?kPNWK5kjSxrMzqkGCAuhE5tFJKVSiBVIdXKIAHaj3FuhK/uWyfo9gHQn5K3H?= =?us-ascii?Q?t47uvk5nws/YqOeRwwuXRINCsfM/jNi5Zp6PLyncnHG/X3HvQY1SQ8rmK6DQ?= =?us-ascii?Q?8vNcakN49SnCUB7/fXj6fr1Cjg4VNKpAtn+vGuKoJt42fWHvqCMbqLr2bQR3?= =?us-ascii?Q?xhkav+0QKQvR1coQqwNWJVRF+MHl+BysrrqiE5lQfEkL1XfSR8av/jy4IpX/?= =?us-ascii?Q?joZlEmDTNTvAGYhxiV1ss7u4LYZ7yu8XlrNu15g2A/heyX9AZos2hEp1Op5r?= =?us-ascii?Q?Ml535fflLL1+6tm1pHnhX9hvNezt6WslHWVnExI37DPu33nMpC8akisie3ob?= =?us-ascii?Q?Rr/TkY1dhEtnEXkkwC6qxn2kMMhnlwc7L5Jtm3dTLrpzWj3mgcYdDYYmwMWL?= =?us-ascii?Q?3VOHHqeIJZGQpB9my9hp624ZCpkXI1XVDIu7JT/f6UmyMwQoK+RbgzBXu90s?= =?us-ascii?Q?FIqaKinmL0QN/00Yv42hQgiUBqyW9wDiiUY/bcVO14ly3qmoGarkDZV5LNP1?= =?us-ascii?Q?d5mY5zk/ZzE84inq13PBp1b1ozalNQ9d7cbh7MlA?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5877.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cdd0e15c-1a83-4d41-733c-08db60be3e5b X-MS-Exchange-CrossTenant-originalarrivaltime: 30 May 2023 03:30:40.8956 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Q6THXugw5YNA/5pYVyTqwi9CNZAHkc6565hLJQ6J8tM8YXQtTO03TUdhN5lfCkTgRpgxKfKvE28xbwB9m3mfTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7579 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Xing, Beilei > Sent: Friday, May 26, 2023 3:39 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Liu, Mingxia ; Xing, Beilei > ; Wang, Xiao W > Subject: [PATCH v4 09/13] net/cpfl: support hairpin queue start/stop >=20 > From: Beilei Xing >=20 > This patch supports Rx/Tx hairpin queue start/stop. >=20 > Signed-off-by: Xiao Wang > Signed-off-by: Mingxia Liu > Signed-off-by: Beilei Xing > --- > drivers/net/cpfl/cpfl_ethdev.c | 41 +++++++++ > drivers/net/cpfl/cpfl_rxtx.c | 151 +++++++++++++++++++++++++++++---- > drivers/net/cpfl/cpfl_rxtx.h | 14 +++ > 3 files changed, 188 insertions(+), 18 deletions(-) >=20 > diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethde= v.c index > a06def06d0..8035878602 100644 > --- a/drivers/net/cpfl/cpfl_ethdev.c > +++ b/drivers/net/cpfl/cpfl_ethdev.c > @@ -896,6 +896,47 @@ cpfl_start_queues(struct rte_eth_dev *dev) > } > } >=20 > + /* For non-manual bind hairpin queues, enable Tx queue and Rx queue, > + * then enable Tx completion queue and Rx buffer queue. > + */ > + for (i =3D 0; i < dev->data->nb_tx_queues; i++) { [Liu, Mingxia] Better to use for (i =3D cpfl_tx_vport->nb_data_txq; i < dev= ->data->nb_tx_queues; i++), because when i < cpfl_tx_vport->nb_data_txq, (c= pfl_txq->hairpin_info.hairpin_q && !cpfl_vport- > >p2p_manual_bind) must be false, or (i - cpfl_vport->nb_data_txq) will < = 0. > + cpfl_txq =3D dev->data->tx_queues[i]; > + if (cpfl_txq->hairpin_info.hairpin_q && !cpfl_vport- > >p2p_manual_bind) { > + err =3D cpfl_switch_hairpin_rxtx_queue(cpfl_vport, > + i - cpfl_vport- > >nb_data_txq, > + false, true); > + if (err) > + PMD_DRV_LOG(ERR, "Failed to switch hairpin > TX queue %u on", > + i); > + else > + cpfl_txq->base.q_started =3D true; > + } > + } > + > + for (i =3D 0; i < dev->data->nb_rx_queues; i++) { [Liu, Mingxia] Better to use for (i =3D cpfl_rx_vport->nb_data_rxq; i < dev= ->data->nb_rx_queues; i++), because when i < cpfl_rx_vport->nb_data_rxq, (c= pfl_txq->hairpin_info.hairpin_q && !cpfl_vport- > >p2p_manual_bind) must be false, or (i - cpfl_vport->nb_data_rxq) will < = 0. > + cpfl_rxq =3D dev->data->rx_queues[i]; > + if (cpfl_rxq->hairpin_info.hairpin_q && !cpfl_vport- > >p2p_manual_bind) { > + err =3D cpfl_switch_hairpin_rxtx_queue(cpfl_vport, > + i - cpfl_vport- > >nb_data_rxq, > + true, true); > + if (err) > + PMD_DRV_LOG(ERR, "Failed to switch hairpin > RX queue %u on", > + i); > + else > + cpfl_rxq->base.q_started =3D true; > + } > + } > + > + if (!cpfl_vport->p2p_manual_bind && > + cpfl_vport->p2p_tx_complq !=3D NULL && > + cpfl_vport->p2p_rx_bufq !=3D NULL) { > + err =3D cpfl_switch_hairpin_bufq_complq(cpfl_vport, true); > + if (err !=3D 0) { > + PMD_DRV_LOG(ERR, "Failed to switch hairpin Tx > complq and Rx bufq"); > + return err; > + } > + } > + > return err; > } >=20 > diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c = index > 702054d1c5..38c48ad8c7 100644 > --- a/drivers/net/cpfl/cpfl_rxtx.c > +++ b/drivers/net/cpfl/cpfl_rxtx.c > @@ -991,6 +991,81 @@ cpfl_hairpin_txq_config(struct idpf_vport *vport, > struct cpfl_tx_queue *cpfl_txq > return idpf_vc_txq_config_by_info(vport, txq_info, 1); } >=20 > +int > +cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on) > +{ > + struct idpf_vport *vport =3D &cpfl_vport->base; > + uint32_t type; > + int err, queue_id; > + > + type =3D VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION; > + queue_id =3D cpfl_vport->p2p_tx_complq->queue_id; > + err =3D idpf_vc_ena_dis_one_queue(vport, queue_id, type, on); > + if (err) > + return err; > + > + type =3D VIRTCHNL2_QUEUE_TYPE_RX_BUFFER; > + queue_id =3D cpfl_vport->p2p_rx_bufq->queue_id; > + err =3D idpf_vc_ena_dis_one_queue(vport, queue_id, type, on); > + > + return err; > +} > + > +int > +cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t > logic_qid, > + bool rx, bool on) > +{ > + struct idpf_vport *vport =3D &cpfl_vport->base; > + uint32_t type; > + int err, queue_id; > + > + type =3D rx ? VIRTCHNL2_QUEUE_TYPE_RX : > VIRTCHNL2_QUEUE_TYPE_TX; > + > + if (type =3D=3D VIRTCHNL2_QUEUE_TYPE_RX) > + queue_id =3D cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info- > >rx_start_qid, logic_qid); > + else > + queue_id =3D cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info- > >tx_start_qid, logic_qid); > + err =3D idpf_vc_ena_dis_one_queue(vport, queue_id, type, on); > + if (err) > + return err; > + > + return err; > +} > + > +static int > +cpfl_alloc_split_p2p_rxq_mbufs(struct idpf_rx_queue *rxq) { > + volatile struct virtchnl2_p2p_rx_buf_desc *rxd; > + struct rte_mbuf *mbuf =3D NULL; > + uint64_t dma_addr; > + uint16_t i; > + > + for (i =3D 0; i < rxq->nb_rx_desc; i++) { > + mbuf =3D rte_mbuf_raw_alloc(rxq->mp); > + if (unlikely(!mbuf)) { > + PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX"); > + return -ENOMEM; > + } > + > + rte_mbuf_refcnt_set(mbuf, 1); > + mbuf->next =3D NULL; > + mbuf->data_off =3D RTE_PKTMBUF_HEADROOM; > + mbuf->nb_segs =3D 1; > + mbuf->port =3D rxq->port_id; > + dma_addr =3D > rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); > + > + rxd =3D &((volatile struct virtchnl2_p2p_rx_buf_desc *)(rxq- > >rx_ring))[i]; > + rxd->reserve0 =3D 0; > + rxd->pkt_addr =3D dma_addr; > + } > + > + rxq->nb_rx_hold =3D 0; > + /* The value written in the RX buffer queue tail register, must be a > multiple of 8.*/ > + rxq->rx_tail =3D rxq->nb_rx_desc - CPFL_HAIRPIN_Q_TAIL_AUX_VALUE; > + > + return 0; > +} > + > int > cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) { @@ = - > 1044,22 +1119,31 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t > rx_queue_id) > IDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); > } else { > /* Split queue */ > - err =3D idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1); > - if (err !=3D 0) { > - PMD_DRV_LOG(ERR, "Failed to allocate RX buffer > queue mbuf"); > - return err; > - } > - err =3D idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2); > - if (err !=3D 0) { > - PMD_DRV_LOG(ERR, "Failed to allocate RX buffer > queue mbuf"); > - return err; > + if (cpfl_rxq->hairpin_info.hairpin_q) { > + err =3D cpfl_alloc_split_p2p_rxq_mbufs(rxq->bufq1); > + if (err !=3D 0) { > + PMD_DRV_LOG(ERR, "Failed to allocate p2p RX > buffer queue mbuf"); > + return err; > + } > + } else { > + err =3D idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1); > + if (err !=3D 0) { > + PMD_DRV_LOG(ERR, "Failed to allocate RX > buffer queue mbuf"); > + return err; > + } > + err =3D idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2); > + if (err !=3D 0) { > + PMD_DRV_LOG(ERR, "Failed to allocate RX > buffer queue mbuf"); > + return err; > + } > } >=20 > rte_wmb(); >=20 > /* Init the RX tail register. */ > IDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1- > >rx_tail); > - IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2- > >rx_tail); > + if (rxq->bufq2) > + IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq- > >bufq2->rx_tail); > } >=20 > return err; > @@ -1166,7 +1250,12 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, > uint16_t rx_queue_id) > return -EINVAL; >=20 > cpfl_rxq =3D dev->data->rx_queues[rx_queue_id]; > - err =3D idpf_vc_queue_switch(vport, rx_queue_id, true, false); > + if (cpfl_rxq->hairpin_info.hairpin_q) > + err =3D cpfl_switch_hairpin_rxtx_queue(cpfl_vport, > + rx_queue_id - cpfl_vport- > >nb_data_txq, > + true, false); > + else > + err =3D idpf_vc_queue_switch(vport, rx_queue_id, true, false); > if (err !=3D 0) { > PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off", > rx_queue_id); > @@ -1180,10 +1269,17 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, > uint16_t rx_queue_id) > idpf_qc_single_rx_queue_reset(rxq); > } else { > rxq->bufq1->ops->release_mbufs(rxq->bufq1); > - rxq->bufq2->ops->release_mbufs(rxq->bufq2); > - idpf_qc_split_rx_queue_reset(rxq); > + if (rxq->bufq2) > + rxq->bufq2->ops->release_mbufs(rxq->bufq2); > + if (cpfl_rxq->hairpin_info.hairpin_q) { > + cpfl_rx_hairpin_descq_reset(rxq); > + cpfl_rx_hairpin_bufq_reset(rxq->bufq1); > + } else { > + idpf_qc_split_rx_queue_reset(rxq); > + } > } > - dev->data->rx_queue_state[rx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; > + if (!cpfl_rxq->hairpin_info.hairpin_q) > + dev->data->rx_queue_state[rx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; >=20 > return 0; > } > @@ -1202,7 +1298,12 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, > uint16_t tx_queue_id) >=20 > cpfl_txq =3D dev->data->tx_queues[tx_queue_id]; >=20 > - err =3D idpf_vc_queue_switch(vport, tx_queue_id, false, false); > + if (cpfl_txq->hairpin_info.hairpin_q) > + err =3D cpfl_switch_hairpin_rxtx_queue(cpfl_vport, > + tx_queue_id - cpfl_vport- > >nb_data_txq, > + false, false); > + else > + err =3D idpf_vc_queue_switch(vport, tx_queue_id, false, false); > if (err !=3D 0) { > PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", > tx_queue_id); > @@ -1215,10 +1316,17 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > if (vport->txq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > idpf_qc_single_tx_queue_reset(txq); > } else { > - idpf_qc_split_tx_descq_reset(txq); > - idpf_qc_split_tx_complq_reset(txq->complq); > + if (cpfl_txq->hairpin_info.hairpin_q) { > + cpfl_tx_hairpin_descq_reset(txq); > + cpfl_tx_hairpin_complq_reset(txq->complq); > + } else { > + idpf_qc_split_tx_descq_reset(txq); > + idpf_qc_split_tx_complq_reset(txq->complq); > + } > } > - dev->data->tx_queue_state[tx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; > + > + if (!cpfl_txq->hairpin_info.hairpin_q) > + dev->data->tx_queue_state[tx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; >=20 > return 0; > } > @@ -1238,10 +1346,17 @@ cpfl_dev_tx_queue_release(struct rte_eth_dev > *dev, uint16_t qid) void cpfl_stop_queues(struct rte_eth_dev *dev) { > + struct cpfl_vport *cpfl_vport =3D > + (struct cpfl_vport *)dev->data->dev_private; > struct cpfl_rx_queue *cpfl_rxq; > struct cpfl_tx_queue *cpfl_txq; > int i; >=20 > + if (cpfl_vport->p2p_rx_bufq !=3D NULL) { > + if (cpfl_switch_hairpin_bufq_complq(cpfl_vport, false) !=3D 0) > + PMD_DRV_LOG(ERR, "Failed to stop hairpin Tx complq > and Rx bufq"); > + } > + > for (i =3D 0; i < dev->data->nb_rx_queues; i++) { > cpfl_rxq =3D dev->data->rx_queues[i]; > if (cpfl_rxq =3D=3D NULL) > diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h = index > 872ebc1bfd..42dfd07155 100644 > --- a/drivers/net/cpfl/cpfl_rxtx.h > +++ b/drivers/net/cpfl/cpfl_rxtx.h > @@ -41,6 +41,17 @@ >=20 > #define CPFL_RX_BUF_STRIDE 64 >=20 > +/* The value written in the RX buffer queue tail register, > + * and in WritePTR field in the TX completion queue context, > + * must be a multiple of 8. > + */ > +#define CPFL_HAIRPIN_Q_TAIL_AUX_VALUE 8 > + > +struct virtchnl2_p2p_rx_buf_desc { > + __le64 reserve0; > + __le64 pkt_addr; /* Packet buffer address */ }; > + > struct cpfl_rxq_hairpin_info { > bool hairpin_q; /* if rx queue is a hairpin queue */ > uint16_t peer_txp; > @@ -102,4 +113,7 @@ int cpfl_hairpin_tx_complq_config(struct cpfl_vport > *cpfl_vport); int cpfl_hairpin_txq_config(struct idpf_vport *vport, stru= ct > cpfl_tx_queue *cpfl_txq); int cpfl_hairpin_rx_bufq_config(struct cpfl_vp= ort > *cpfl_vport); int cpfl_hairpin_rxq_config(struct idpf_vport *vport, stru= ct > cpfl_rx_queue *cpfl_rxq); > +int cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool > +on); int cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, u= int16_t > qid, > + bool rx, bool on); > #endif /* _CPFL_RXTX_H_ */ > -- > 2.26.2