From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73FCD42BDA; Tue, 30 May 2023 04:27:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0202C40F18; Tue, 30 May 2023 04:27:27 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 98F8B406BC for ; Tue, 30 May 2023 04:27:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685413645; x=1716949645; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=pK+lQR29gL8060Cp1sizmI8/kww08i/Yz1Nzx+R8bk0=; b=BUckaAnzmbKMyCt0r9WSLXjxZLN73rG9kD9Dy02O4TzjGxIUZMP6PrMY i8NdDtJPX2jD3RVKy5wWChuqYKNnLW1HBIfaKqA2h+5S3AJSRa7vMOYy4 65vIrQldYiNwXz9udqPM9HPpLf71MsfmAWq6mGmHUCPEyJJTppe1RdhdW tR7hOrI0mY459gk+ko/kKTJP/9iwrKEIt07NphIwfwEM8gO/r7w3OSg5z xd7HUUKzRWw8GvoChB5fL94jp/Nf9GonVZgDxnUVLgrJpJ+JOMRqiI688 YvY8+SoebSTE44Le2jdbE2fXrj9DbsabNKa/im2ZHziHq9XWu4Z72TUO0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="354814376" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="354814376" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2023 19:27:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="850566488" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="850566488" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by fmsmga001.fm.intel.com with ESMTP; 29 May 2023 19:27:24 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Mon, 29 May 2023 19:27:24 -0700 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 19:27:24 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.176) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.23; Mon, 29 May 2023 19:27:23 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jD74pRIIKiV35xF6Oz4YeuMohqpqmol38OsYdnxEb7r0pTgVucD0tSlePwN0ksVVzaJ1JNwXHrnwtXv/u6Q1E1cfidZEsK7/IZEMYE6MD1+ZhArlMRqwiGcjAX6Fnq9/B0YfhlJQ2VApp1OtzHKS/SFFR4UddlBTD5wFHogV/FATraPhaKOvvwFTuuwyXz8MqoMLj73/+J7bfI1FNHVNQcreYL3+w43k5OPfJt8SyhpXeDhKXKpm9ua5m516Gu/eTXI7dK2yX32lKVN//lBvMe8pz+ICWXiivOUrb+MbITvEsmaB4TBUGTsRtUYqRCdpODH66tlHhDSuMakbALS6mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=i2K4J7ELHa0AEMgA4TN91vSjiXKq3lI8aLg9pXENE0c=; b=DcY4J7Gd41bdztjZ92MUuFsi9aFTEopAqnuJKjsMwd4XzAjp9ycZ1B9lGRxzN6ouejPc39eZYSy1YAzPeHgNea0WroEWPqMSwK0tSm0KlniVswIrpRSVp8RGSII6U+aisEeN0iNlsqBmlAbP6jRtkreg3l3Nsjsk387RfsK0j2/mV6xLeQJsT2CxHwO6EBTR6+mmgdB2u+RA9TDYrYlIIYlKfh9B2jMCNnquBtHkqe3T/98H4ZJK3S8zj0/4kWiZN0q9ADShbQpm6dqJENqahZ9HiqBApl1pp8JF3HFf8vPOGy1NzgltpdCFaMuFtiDp05P1lAFJj5axDq6+9Hk4AQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from PH0PR11MB5877.namprd11.prod.outlook.com (2603:10b6:510:141::12) by DM6PR11MB4755.namprd11.prod.outlook.com (2603:10b6:5:2ae::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.23; Tue, 30 May 2023 02:27:20 +0000 Received: from PH0PR11MB5877.namprd11.prod.outlook.com ([fe80::da1b:ee87:709:3174]) by PH0PR11MB5877.namprd11.prod.outlook.com ([fe80::da1b:ee87:709:3174%4]) with mapi id 15.20.6433.018; Tue, 30 May 2023 02:27:20 +0000 From: "Liu, Mingxia" To: "Xing, Beilei" , "Wu, Jingjing" CC: "dev@dpdk.org" , "Wang, Xiao W" Subject: RE: [PATCH v4 05/13] net/cpfl: support hairpin queue setup and release Thread-Topic: [PATCH v4 05/13] net/cpfl: support hairpin queue setup and release Thread-Index: AQHZj6h1TcZrIi8rtkKFu48MQZC+Gq9yGe2A Date: Tue, 30 May 2023 02:27:19 +0000 Message-ID: References: <20230519073116.56749-1-beilei.xing@intel.com> <20230526073850.101079-1-beilei.xing@intel.com> <20230526073850.101079-6-beilei.xing@intel.com> In-Reply-To: <20230526073850.101079-6-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5877:EE_|DM6PR11MB4755:EE_ x-ms-office365-filtering-correlation-id: 01c9a0a1-b5ee-4879-b07e-08db60b564c0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 41wiKyfPwy+K6n1Tny3MgCEQS6UbcgeAGQQNFon/VwbtkTpCg1yj63WeL5cQ5pzEpDdhOVUY+3Ywd2rAgNNioqtBEkC+MTpIO4p8IncpbRgaqKpvYM5nyLrgg6eQfTC/C0nrKWaFDR5ZI7GbgMRq/F6KtdVXbRe6eoUOp2XtUNH73+/r2X/qTN+e+zQGJwp2iacinwGjvQtP/Avh/4Pt/b8vcChcqr2fIfwmch0kEQMZirD8u88dETTusHAqUlXYYPZRCQYSk6M/wiEj53MAMKCybNvoY1XoZvzPxUDT/1LvuHXGoZmhEsdGuGuVAWPgB8h42P3nzMVv93jO7ymx5ccTALmlJbL06aZpjqCR+vZDT/QrW4/Vq/OYfngTa3gjmxWZSqLKjWkeAbLoagPW2NEBjAJ+IsIZkCz631Vh8pt1CCGsEw4ZORwS6TsAJxhRsNuraA89N3Bb2VIJyr9Q4IQW4lwjK+c1gMitf7eGHQFCDb4OXOcOXHJuO22FcBlMbR7VzsaQkWziA/UCiRsYWEtDvfbA5gKDhhgbLThUfQMznoBWneq+GhvRbtRODKmx1PolgazZTrhWZQaxO+axpMj/eKMctGsAVPJjdKz62wzY2z3E5BFDWMtbL4fIPEFK x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PH0PR11MB5877.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230028)(366004)(396003)(376002)(136003)(346002)(39860400002)(451199021)(6506007)(9686003)(186003)(2906002)(53546011)(54906003)(110136005)(478600001)(26005)(83380400001)(86362001)(7696005)(122000001)(41300700001)(8676002)(82960400001)(38100700002)(8936002)(55016003)(66556008)(5660300002)(64756008)(66446008)(66476007)(66946007)(76116006)(316002)(33656002)(71200400001)(38070700005)(52536014)(107886003)(6636002)(4326008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-2022-jp?B?MTVYQjEyakVOMktwK0hOV1lTSi9IR3VJVE8xeGJNamhpbkRkWlVlRUoz?= =?iso-2022-jp?B?MWlYTUZhR3Qvc01UWEZZa1NsaTNlVklZQVRwa1NPZzVsT2Fpclh3VjNY?= =?iso-2022-jp?B?ZExUaWxrKzhGMzZwWHovMi9YZEpKMzRuaU1JRldaZTI5dVVCbFpNRzFP?= =?iso-2022-jp?B?QWJ1K2F2eUovWVpFdDFyNmdDTFpjSXZHZXNWU1RmVVJpdTQwUmVZMXhP?= =?iso-2022-jp?B?Um9VUktocU9hOEEzcFQrWC82T2tPN1NLbGxMZWU0cEpUVlN0S0xnWmZD?= =?iso-2022-jp?B?QUEyaUl4WE0yV2pLNnZUZVpDZERJS2VJZllYUU5Rc053Z2tvM3U2TkFh?= =?iso-2022-jp?B?UmFGV212aHhwczNFb25KMDI0YWJUTzRnNGJ1MmYwSEV0K2ZkZWZpell2?= =?iso-2022-jp?B?b05EQld2S3k1bVB5bzJneGFmVkUwYTFnKzl1YXlIaUtWazgwYzRXOGw2?= =?iso-2022-jp?B?M1JJa21rYkVsVmR6Um1GWEgwbmJxK3F2Ly9jbkhkNWpQa1ZmenJQMWJP?= =?iso-2022-jp?B?ZUllZHQ3R2F3N2R1MkdiWmdYWFpFSkl1ZGViOWQ4RnFPUHoyZWthcU1u?= =?iso-2022-jp?B?Z0k0QktyUnZWTGFTbkdwQVRMM3FPNDFXRFdFQTNmeU1KZkErSWFtNG5F?= =?iso-2022-jp?B?SUFGNXRZTmIxaE9tcWRoNnJ3YnlrSjRaeVVxNEZ6WE90YzIvalN5S3Z3?= =?iso-2022-jp?B?OCsrSE9zL29mUmtIeDVzQURoT1V2bEVvN1FFUU9OUkRocG1rS0NOS0dG?= =?iso-2022-jp?B?eXFKMFd1WVh5VUNqOXB4VzgzTkk4T2doMG1LTGpvdGd4cFJBV1kxcXF5?= =?iso-2022-jp?B?Z2NqRmx3QkJJcEh5eFBkRjRsdWJvQXFGb0VPeVV4RVhmbHVwbWRlN1lK?= =?iso-2022-jp?B?V2tSUndoMStPdDI1TUQ0MkgxU3BBemNVREtQWWJCSWgxbjkwR21xbmlB?= =?iso-2022-jp?B?NzR3V0tRNkE1YXF1bmkxbzM5NFV6WFAwcGxieFYzbkF6Q3JaSDQ4cjAz?= =?iso-2022-jp?B?TzQvRnQrVmFJY2NuOHNoSjlMVE9FWVhJQldHNjNMRkE1RUtRQWtyaVh0?= =?iso-2022-jp?B?dVZZbGlETmEyMXN4Z25paFhUbGwvKzI0OTE0Wml0OXpPRlhEZFd4SDBJ?= =?iso-2022-jp?B?T0gyc2MxOEFUcHFOTjhpbDNYSWhrb2l1aHQza1hnTVVRRUFjN2liVjRN?= =?iso-2022-jp?B?STE3Z25mcDNMRWx5aFdOdzVmVVBjcGRDVVdhZkJybkFCcHRYN2tvSlUy?= =?iso-2022-jp?B?cnpCd2gwMHZUM1Q2M1lJMFV0bWtuQkRvTmZUR0RTRTUyd05wVGRFZ2tp?= =?iso-2022-jp?B?T2IvK05NUzBpZmZlNEFzSUg3SnV3aGpUZ0pYajRiTW16eVZrUXdXNFd3?= =?iso-2022-jp?B?WWduQTl2dUt5MUp1RXFKZzk5eHZjRWlyeGVrYjdBeUNlZWlNbjNMUzNl?= =?iso-2022-jp?B?akIzYkl0L1N4MGpKek52Y0x0dENzdFRoN2NuRWxSWnJIaTJrTU9GWUpr?= =?iso-2022-jp?B?VkMvSHFGd1UwSGhBY0RZL0xDb0ZRZVhWMkFzZEdZeTBBb2JDc3JWWHhB?= =?iso-2022-jp?B?T3hSQnpxaEcrdTBEU0QvTHBid3NCRkpNREJsTk44aXRONk9XTkwrbmRG?= =?iso-2022-jp?B?MUVBUFBPbzh5TUkvQXAwenhZNVJWaDlBVXQycExhOUJwVS94UC9RaDMw?= =?iso-2022-jp?B?ZDhuWnFMeVBvVjlRTEhLRndnR1Z2NEtuazdaT2VkdjNhSzRjdEVSdzls?= =?iso-2022-jp?B?YlNTcnl6OFFjM0tISHdZN0RMRmpjN0Jlc2U2ZzI2dklQYzBVZG5nWi9U?= =?iso-2022-jp?B?K2hkbHY0STlWcklmaUdmUWtzUDNrcUZKby92cWpWMkVPbGZ1cUNGeVh4?= =?iso-2022-jp?B?TGcxSTdOWTRublN2bTROU0E4ZXJ6OWY3RU9BNWFkSWVXUGtlVmNPUTBa?= =?iso-2022-jp?B?OW1EbHd6SUpMTzV2Z0Q1MzJUQU9YRlordjJIK2wyL25rbFIwa0hRZTlL?= =?iso-2022-jp?B?cXpQd1lZcUlFQWNzMmJhMlBBU05INm4wZk8zbVF0MFpQSUNJdjNYcmZI?= =?iso-2022-jp?B?d0w2dVFQVnpGRm9EL3p6YlMvQ1hBdHdwdStVNmxpajc4cnFFYWdtd1F5?= =?iso-2022-jp?B?cVJLTkk0bS9IMEhlMmZCUlc1ejF3Wm5RWXZ2ak1kZlZaY2VRMnVBV0F0?= =?iso-2022-jp?B?MlFaMHVoT2JhRlJoanpvYm52VGs2bGhtQUIrTVFuL3FzNVFSelpYMzRt?= =?iso-2022-jp?B?VHduRCtSeUd5QTJWbi94RnhqUnc3c01WNjczQTF1RjgxdlFhZ3dmRmFy?= =?iso-2022-jp?B?azBXSQ==?= Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5877.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01c9a0a1-b5ee-4879-b07e-08db60b564c0 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 May 2023 02:27:19.8418 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yFm8DcrFwSia9ihdYvCjuI25JufED0rhUlFLVwLGmPkK0B8m+mIixcTWKtDwtRRh6h1Yv2Zs1OYlzQEzuyMU6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4755 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Xing, Beilei > Sent: Friday, May 26, 2023 3:39 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Liu, Mingxia ; Xing, Beilei > ; Wang, Xiao W > Subject: [PATCH v4 05/13] net/cpfl: support hairpin queue setup and relea= se >=20 > From: Beilei Xing >=20 > Support hairpin Rx/Tx queue setup and release. >=20 > Signed-off-by: Xiao Wang > Signed-off-by: Mingxia Liu > Signed-off-by: Beilei Xing > --- > drivers/net/cpfl/cpfl_ethdev.c | 6 + > drivers/net/cpfl/cpfl_ethdev.h | 11 + > drivers/net/cpfl/cpfl_rxtx.c | 353 +++++++++++++++++++++++- > drivers/net/cpfl/cpfl_rxtx.h | 36 +++ > drivers/net/cpfl/cpfl_rxtx_vec_common.h | 4 + > 5 files changed, 409 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethde= v.c index > 40b4515539..b17c538ec2 100644 > --- a/drivers/net/cpfl/cpfl_ethdev.c > +++ b/drivers/net/cpfl/cpfl_ethdev.c > @@ -879,6 +879,10 @@ cpfl_dev_close(struct rte_eth_dev *dev) > struct cpfl_adapter_ext *adapter =3D CPFL_ADAPTER_TO_EXT(vport- > >adapter); >=20 > cpfl_dev_stop(dev); > + if (cpfl_vport->p2p_mp) { > + rte_mempool_free(cpfl_vport->p2p_mp); > + cpfl_vport->p2p_mp =3D NULL; > + } >=20 > if (!adapter->base.is_rx_singleq && !adapter->base.is_tx_singleq) > cpfl_p2p_queue_grps_del(vport); > @@ -922,6 +926,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops =3D = { > .xstats_get_names =3D cpfl_dev_xstats_get_names, > .xstats_reset =3D cpfl_dev_xstats_reset, > .hairpin_cap_get =3D cpfl_hairpin_cap_get, > + .rx_hairpin_queue_setup =3D cpfl_rx_hairpin_queue_setup, > + .tx_hairpin_queue_setup =3D cpfl_tx_hairpin_queue_setup, > }; >=20 > +int > +cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf) { > + struct cpfl_vport *cpfl_vport =3D (struct cpfl_vport *)dev->data- > >dev_private; > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter_base =3D vport->adapter; > + uint16_t logic_qid =3D cpfl_vport->nb_p2p_rxq; > + struct cpfl_rxq_hairpin_info *hairpin_info; > + struct cpfl_rx_queue *cpfl_rxq; > + struct idpf_rx_queue *bufq1 =3D NULL; > + struct idpf_rx_queue *rxq; > + uint16_t peer_port, peer_q; > + uint16_t qid; > + int ret; > + > + if (vport->rxq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > + PMD_INIT_LOG(ERR, "Only spilt queue model supports hairpin > queue."); > + return -EINVAL; > + } > + > + if (conf->peer_count !=3D 1) { > + PMD_INIT_LOG(ERR, "Can't support Rx hairpin queue peer > count %d", conf->peer_count); > + return -EINVAL; > + } > + > + peer_port =3D conf->peers[0].port; > + peer_q =3D conf->peers[0].queue; > + > + if (nb_desc % CPFL_ALIGN_RING_DESC !=3D 0 || > + nb_desc > CPFL_MAX_RING_DESC || > + nb_desc < CPFL_MIN_RING_DESC) { > + PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is > invalid", nb_desc); > + return -EINVAL; > + } > + > + /* Free memory if needed */ > + if (dev->data->rx_queues[queue_idx]) { > + cpfl_rx_queue_release(dev->data->rx_queues[queue_idx]); > + dev->data->rx_queues[queue_idx] =3D NULL; > + } > + > + /* Setup Rx description queue */ > + cpfl_rxq =3D rte_zmalloc_socket("cpfl hairpin rxq", > + sizeof(struct cpfl_rx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!cpfl_rxq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for rx queue > data structure"); > + return -ENOMEM; > + } > + > + rxq =3D &cpfl_rxq->base; > + hairpin_info =3D &cpfl_rxq->hairpin_info; > + rxq->nb_rx_desc =3D nb_desc * 2; > + rxq->queue_id =3D cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info- > >rx_start_qid, logic_qid); > + rxq->port_id =3D dev->data->port_id; > + rxq->adapter =3D adapter_base; > + rxq->rx_buf_len =3D CPFL_P2P_MBUF_SIZE - RTE_PKTMBUF_HEADROOM; > + hairpin_info->hairpin_q =3D true; > + hairpin_info->peer_txp =3D peer_port; > + hairpin_info->peer_txq_id =3D peer_q; > + > + if (conf->manual_bind !=3D 0) > + cpfl_vport->p2p_manual_bind =3D true; > + else > + cpfl_vport->p2p_manual_bind =3D false; > + > + if (cpfl_vport->p2p_rx_bufq =3D=3D NULL) { > + bufq1 =3D rte_zmalloc_socket("hairpin rx bufq1", > + sizeof(struct idpf_rx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!bufq1) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for > hairpin Rx buffer queue 1."); > + ret =3D -ENOMEM; > + goto err_alloc_bufq1; > + } > + qid =3D 2 * logic_qid; > + ret =3D cpfl_rx_hairpin_bufq_setup(dev, bufq1, qid, nb_desc); > + if (ret) { > + PMD_INIT_LOG(ERR, "Failed to setup hairpin Rx buffer > queue 1"); > + ret =3D -EINVAL; > + goto err_setup_bufq1; > + } > + cpfl_vport->p2p_rx_bufq =3D bufq1; > + } > + > + rxq->bufq1 =3D cpfl_vport->p2p_rx_bufq; > + rxq->bufq2 =3D NULL; > + > + cpfl_vport->nb_p2p_rxq++; > + rxq->q_set =3D true; > + dev->data->rx_queues[queue_idx] =3D cpfl_rxq; > + > + return 0; > + > +err_setup_bufq1: > + rte_free(bufq1); > +err_alloc_bufq1: > + rte_free(rxq); [Liu, Mingxia] Here should free cpfl_rxq, right=1B$B!)=1B(B > + > + return ret; > +} > + > +int > +cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf) { > + struct cpfl_vport *cpfl_vport =3D > + (struct cpfl_vport *)dev->data->dev_private; > + > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter_base =3D vport->adapter; > + uint16_t logic_qid =3D cpfl_vport->nb_p2p_txq; > + struct cpfl_txq_hairpin_info *hairpin_info; > + struct idpf_hw *hw =3D &adapter_base->hw; > + struct cpfl_tx_queue *cpfl_txq; > + struct idpf_tx_queue *txq, *cq; > + const struct rte_memzone *mz; > + uint32_t ring_size; > + uint16_t peer_port, peer_q; > + > + if (vport->txq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > + PMD_INIT_LOG(ERR, "Only spilt queue model supports hairpin > queue."); > + return -EINVAL; > + } > + > + if (conf->peer_count !=3D 1) { > + PMD_INIT_LOG(ERR, "Can't support Tx hairpin queue peer > count %d", conf->peer_count); > + return -EINVAL; > + } > + > + peer_port =3D conf->peers[0].port; > + peer_q =3D conf->peers[0].queue; > + > + if (nb_desc % CPFL_ALIGN_RING_DESC !=3D 0 || > + nb_desc > CPFL_MAX_RING_DESC || > + nb_desc < CPFL_MIN_RING_DESC) { > + PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is > invalid", > + nb_desc); > + return -EINVAL; > + } > + > + /* Free memory if needed. */ > + if (dev->data->tx_queues[queue_idx]) { > + cpfl_tx_queue_release(dev->data->tx_queues[queue_idx]); > + dev->data->tx_queues[queue_idx] =3D NULL; > + } > + > + /* Allocate the TX queue data structure. */ > + cpfl_txq =3D rte_zmalloc_socket("cpfl hairpin txq", > + sizeof(struct cpfl_tx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!cpfl_txq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx queue > structure"); > + return -ENOMEM; > + } > + > + txq =3D &cpfl_txq->base; > + hairpin_info =3D &cpfl_txq->hairpin_info; > + /* Txq ring length should be 2 times of Tx completion queue size. */ > + txq->nb_tx_desc =3D nb_desc * 2; > + txq->queue_id =3D cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info- > >tx_start_qid, logic_qid); > + txq->port_id =3D dev->data->port_id; > + hairpin_info->hairpin_q =3D true; > + hairpin_info->peer_rxp =3D peer_port; > + hairpin_info->peer_rxq_id =3D peer_q; > + > + if (conf->manual_bind !=3D 0) > + cpfl_vport->p2p_manual_bind =3D true; > + else > + cpfl_vport->p2p_manual_bind =3D false; > + > + /* Always Tx hairpin queue allocates Tx HW ring */ > + ring_size =3D RTE_ALIGN(txq->nb_tx_desc * CPFL_P2P_DESC_LEN, > + CPFL_DMA_MEM_ALIGN); > + mz =3D rte_eth_dma_zone_reserve(dev, "hairpin_tx_ring", logic_qid, > + ring_size + CPFL_P2P_RING_BUF, > + CPFL_RING_BASE_ALIGN, > + dev->device->numa_node); > + if (!mz) { > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX"); > + rte_free(txq); [Liu, Mingxia] Here should free cpfl_txq, right=1B$B!)=1B(B > + return -ENOMEM; > + } > + > + txq->tx_ring_phys_addr =3D mz->iova; > + txq->desc_ring =3D mz->addr; > + txq->mz =3D mz; > + > + cpfl_tx_hairpin_descq_reset(txq); > + txq->qtx_tail =3D hw->hw_addr + > + cpfl_hw_qtail_get(cpfl_vport->p2p_q_chunks_info- > >tx_qtail_start, > + logic_qid, cpfl_vport->p2p_q_chunks_info- > >tx_qtail_spacing); > + txq->ops =3D &def_txq_ops; > + > + if (cpfl_vport->p2p_tx_complq =3D=3D NULL) { > + cq =3D rte_zmalloc_socket("cpfl hairpin cq", > + sizeof(struct idpf_tx_queue), > + RTE_CACHE_LINE_SIZE, > + dev->device->numa_node); > + if (!cq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx > queue structure"); [Liu, Mingxia] Before returning, should free some resource, such as free cp= fl_txq, right=1B$B!)=1B(B > + return -ENOMEM; > + } > + > + cq->nb_tx_desc =3D nb_desc; > + cq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info->tx_compl_start_qid, > + 0); > + cq->port_id =3D dev->data->port_id; > + > + /* Tx completion queue always allocates the HW ring */ > + ring_size =3D RTE_ALIGN(cq->nb_tx_desc * CPFL_P2P_DESC_LEN, > + CPFL_DMA_MEM_ALIGN); > + mz =3D rte_eth_dma_zone_reserve(dev, "hairpin_tx_compl_ring", > logic_qid, > + ring_size + CPFL_P2P_RING_BUF, > + CPFL_RING_BASE_ALIGN, > + dev->device->numa_node); > + if (!mz) { > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory > for TX completion queue"); > + rte_free(txq); [Liu, Mingxia]Here should free cpfl_txq, right=1B$B!)=1B(BIn addition, shou= ld cq resource be released?