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Sun, 21 Mar 2021 14:43:32 +0000 From: Pavan Nikhilesh Bhagavatula To: Shijith Thotton , Erik Gabriel Carrillo CC: Jerin Jacob Kollanukkaran , "dev@dpdk.org" Thread-Topic: [PATCH v3 3/3] event/octeontx2: add timer periodic mode support Thread-Index: AQHXGwRwEETtGsZAbEuBYqma/bCjEqqOiwww Date: Sun, 21 Mar 2021 14:43:31 +0000 Message-ID: References: <51c875237a4f639dd566eca8cfc181aecc06b513.1615967694.git.sthotton@marvell.com> In-Reply-To: <51c875237a4f639dd566eca8cfc181aecc06b513.1615967694.git.sthotton@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [2405:201:d009:304d:9db4:99d5:8ce4:b375] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: da9bf390-090e-4497-0ed5-08d8ec77b313 x-ms-traffictypediagnostic: PH0PR18MB3893: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1332; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: Y8tj4aXplS5MHo2lYopSphpgtWvWwW0YjpwRY6ntKlrcNL8fExjhrwfh+b0xdghvqXZ4MFJkSYDw/DxHD3K5lLMBnLiI/C4op4sHbFd1ulSplCF1fpLPKHri9JLWErT4DF4YxM7VLYBJOkaC43y5EApj7n7GvMC0HDRDLRTnQxvQRUqHtOFUrEwrItU47phcTHlNxPLJ72CPpd0pJ5SWxcTYrDo/wDsEcst+IbV9oohmtv5m5CZKaiFYHixAOcXL56sBr9Gm7l3TW54N0DUSfYsEr66zyVgAlo3Q/Z0iniWei/17mYHo9GcDx1oxTy/3sFZ2oF1QCXzbcz/pwTt3FgccClxg9RkF9Vce+UWdX3Ji1corgPn1QBBNaeyJ9xICyCOvUaLgXrXJHKRKNMuff9j6PT961t5N9g3U89Ti1wqb5JMazNJC6NGH4FHs37K2HgW1YS8lkO/ji3YxCpry1uNvWhNrY/roEA5TRgCZDlKYywrR0H4dQ09vLTz2+gjI/YuKqh1Rb8jFEB8lSy+QGw3j2Izk9msI+EyG7ah93V4F0BwhgpcdM9HiMrUUoC5ZuwrNfhDQ8iQCQxILSd1H1DSOO6/erpVGAFEnLQW9tpm3KdExYJL4RVG+dG1LyCD0VKn36ob+70GO0oKGxqeJl9EvUVG3Q2rBVh/CrTFO0zw= x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR18MB4086.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: da9bf390-090e-4497-0ed5-08d8ec77b313 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Mar 2021 14:43:32.0299 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GVnV+KhFeNgj/staNqfZYoGfRfYuPv+lsVFX8/d/R9ZrdfoHrKubeKwWENUQOxvAGHURQ5Fau18LcZCGyGPBxHHip/ea6PHMG0J6CUS8x18= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR18MB3893 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-21_02:2021-03-19, 2021-03-21 signatures=0 Subject: Re: [dpdk-dev] [PATCH v3 3/3] event/octeontx2: add timer periodic mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >-----Original Message----- >From: Shijith Thotton >Sent: Wednesday, March 17, 2021 1:34 PM >To: Erik Gabriel Carrillo >Cc: Shijith Thotton ; Pavan Nikhilesh >Bhagavatula ; Jerin Jacob Kollanukkaran >; dev@dpdk.org >Subject: [PATCH v3 3/3] event/octeontx2: add timer periodic mode >support > >Add support for periodic mode in event timer adapter. > >Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh >--- > drivers/event/octeontx2/otx2_tim_evdev.c | 29 >++++++++++++++++++++---- > drivers/event/octeontx2/otx2_tim_evdev.h | 1 + > 2 files changed, 25 insertions(+), 5 deletions(-) > >diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c >b/drivers/event/octeontx2/otx2_tim_evdev.c >index 4c24cc8a6..39a29f17f 100644 >--- a/drivers/event/octeontx2/otx2_tim_evdev.c >+++ b/drivers/event/octeontx2/otx2_tim_evdev.c >@@ -65,7 +65,8 @@ otx2_tim_ring_info_get(const struct >rte_event_timer_adapter *adptr, > struct otx2_tim_ring *tim_ring =3D adptr->data->adapter_priv; > > adptr_info->max_tmo_ns =3D tim_ring->max_tout; >- adptr_info->min_resolution_ns =3D tim_ring->tck_nsec; >+ adptr_info->min_resolution_ns =3D tim_ring->ena_periodic ? >+ tim_ring->max_tout : tim_ring->tck_nsec; > rte_memcpy(&adptr_info->conf, &adptr->data->conf, > sizeof(struct rte_event_timer_adapter_conf)); > } >@@ -163,7 +164,7 @@ tim_chnk_pool_create(struct otx2_tim_ring >*tim_ring, > } > tim_ring->aura =3D npa_lf_aura_handle_to_aura( > tim_ring->chunk_pool->pool_id); >- tim_ring->ena_dfb =3D 0; >+ tim_ring->ena_dfb =3D tim_ring->ena_periodic ? 1 : 0; > } else { > tim_ring->chunk_pool =3D >rte_mempool_create(pool_name, > tim_ring->nb_chunks, tim_ring- >>chunk_sz, >@@ -254,6 +255,7 @@ otx2_tim_ring_create(struct >rte_event_timer_adapter *adptr) > struct tim_ring_req *free_req; > struct tim_lf_alloc_req *req; > struct tim_lf_alloc_rsp *rsp; >+ uint8_t is_periodic; > int i, rc; > > if (dev =3D=3D NULL) >@@ -284,6 +286,20 @@ otx2_tim_ring_create(struct >rte_event_timer_adapter *adptr) > } > } > >+ is_periodic =3D 0; >+ if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) { >+ if (rcfg->max_tmo_ns && >+ rcfg->max_tmo_ns !=3D rcfg->timer_tick_ns) { >+ rc =3D -ERANGE; >+ goto rng_mem_err; >+ } >+ >+ /* Use 2 buckets to avoid contention */ >+ rcfg->max_tmo_ns =3D rcfg->timer_tick_ns; >+ rcfg->timer_tick_ns /=3D 2; >+ is_periodic =3D 1; >+ } >+ > tim_ring =3D rte_zmalloc("otx2_tim_prv", sizeof(struct >otx2_tim_ring), 0); > if (tim_ring =3D=3D NULL) { > rc =3D -ENOMEM; >@@ -296,11 +312,13 @@ otx2_tim_ring_create(struct >rte_event_timer_adapter *adptr) > tim_ring->clk_src =3D (int)rcfg->clk_src; > tim_ring->ring_id =3D adptr->data->id; > tim_ring->tck_nsec =3D RTE_ALIGN_MUL_CEIL(rcfg- >>timer_tick_ns, 10); >- tim_ring->max_tout =3D rcfg->max_tmo_ns; >+ tim_ring->max_tout =3D is_periodic ? >+ rcfg->timer_tick_ns * 2 : rcfg->max_tmo_ns; > tim_ring->nb_bkts =3D (tim_ring->max_tout / tim_ring->tck_nsec); > tim_ring->chunk_sz =3D dev->chunk_sz; > tim_ring->nb_timers =3D rcfg->nb_timers; > tim_ring->disable_npa =3D dev->disable_npa; >+ tim_ring->ena_periodic =3D is_periodic; > tim_ring->enable_stats =3D dev->enable_stats; > > for (i =3D 0; i < dev->ring_ctl_cnt ; i++) { >@@ -348,7 +366,7 @@ otx2_tim_ring_create(struct >rte_event_timer_adapter *adptr) > cfg_req->ring =3D tim_ring->ring_id; > cfg_req->bigendian =3D false; > cfg_req->clocksource =3D tim_ring->clk_src; >- cfg_req->enableperiodic =3D false; >+ cfg_req->enableperiodic =3D tim_ring->ena_periodic; > cfg_req->enabledontfreebuffer =3D tim_ring->ena_dfb; > cfg_req->bucketsize =3D tim_ring->nb_bkts; > cfg_req->chunksize =3D tim_ring->chunk_sz; >@@ -568,7 +586,8 @@ otx2_tim_caps_get(const struct rte_eventdev >*evdev, uint64_t flags, > > /* Store evdev pointer for later use. */ > dev->event_dev =3D (struct rte_eventdev *)(uintptr_t)evdev; >- *caps =3D RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; >+ *caps =3D RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT | >+ RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; > *ops =3D &otx2_tim_ops; > > return 0; >diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h >b/drivers/event/octeontx2/otx2_tim_evdev.h >index 44e3c7b51..82d116c09 100644 >--- a/drivers/event/octeontx2/otx2_tim_evdev.h >+++ b/drivers/event/octeontx2/otx2_tim_evdev.h >@@ -155,6 +155,7 @@ struct otx2_tim_ring { > uint8_t disable_npa; > uint8_t optimized; > uint8_t ena_dfb; >+ uint8_t ena_periodic; > uint16_t ring_id; > uint32_t aura; > uint64_t nb_timers; >-- >2.25.1