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Thu, 29 Sep 2022 08:10:49 +0000 From: Shijith Thotton To: Olivier Matz CC: "dev@dpdk.org" , Pavan Nikhilesh Bhagavatula , "Honnappa.Nagarahalli@arm.com" , "bruce.richardson@intel.com" , Jerin Jacob Kollanukkaran , "mb@smartsharesystems.com" , "stephen@networkplumber.org" , "thomas@monjalon.net" , "david.marchand@redhat.com" , Ruifeng Wang , Jan Viktorin , Nithin Kumar Dabilpuram , Kiran Kumar Kokkilagadda , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj , Radha Chintakuntla , Veerasenareddy Burru , Ashwin Sekhar T K , Jakub Palider , Tomasz Duszynski Subject: RE: [EXT] Re: [PATCH v3 4/5] drivers: mark Marvell cnxk PMDs work with IOVA as VA Thread-Topic: [EXT] Re: [PATCH v3 4/5] drivers: mark Marvell cnxk PMDs work with IOVA as VA Thread-Index: AQHYzcIKjyIbiG2iSUK5tuExHMOwYa301vmAgAEjLxCAABjagIAABxVw Date: Thu, 29 Sep 2022 08:10:49 +0000 Message-ID: References: <20220907134340.3629224-1-sthotton@marvell.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR18MB4425:EE_|PH7PR18MB5228:EE_ x-ms-office365-filtering-correlation-id: f4ca14bc-dccc-441a-a4d1-08daa1f21e93 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR18MB4425.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4ca14bc-dccc-441a-a4d1-08daa1f21e93 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2022 08:10:49.3027 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Uh/XkwJTtbULnuseW720QN1dyBz7d/HMRJdQeLHMbBPeIwa3Uez+WEk8A5W8pgzJwcGZ6eotgnW1sQA0ZH3Wsg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR18MB5228 X-Proofpoint-GUID: uUw9p0lZBsRGt-gBD113817PvRvAF9B6 X-Proofpoint-ORIG-GUID: uUw9p0lZBsRGt-gBD113817PvRvAF9B6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-29_04,2022-09-29_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org >> >> Enabled the flag pmd_iova_as_va in cnxk driver build files as they wo= rk >> >> with IOVA as VA. Updated cn9k and cn10k soc build configurations to >> >> enable the IOVA as VA build by default. >> >> >> >> Signed-off-by: Shijith Thotton >> >> --- >> >> config/arm/meson.build | 8 +++- >> >> drivers/common/cnxk/meson.build | 1 + >> >> drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 4 +- >> >> drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 2 +- >> >> drivers/crypto/cnxk/meson.build | 2 + >> >> drivers/dma/cnxk/meson.build | 1 + >> >> drivers/event/cnxk/meson.build | 1 + >> >> drivers/mempool/cnxk/meson.build | 1 + >> >> drivers/net/cnxk/cn10k_tx.h | 55 +++++++---------------= -- >> >> drivers/net/cnxk/cn9k_tx.h | 55 +++++++---------------= -- >> >> drivers/net/cnxk/cnxk_ethdev.h | 1 - >> >> drivers/net/cnxk/meson.build | 1 + >> >> drivers/raw/cnxk_bphy/meson.build | 1 + >> >> drivers/raw/cnxk_gpio/meson.build | 1 + >> >> 14 files changed, 50 insertions(+), 84 deletions(-) >> >> >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build >> >> index 9f1636e0d5..4e95e8b388 100644 >> >> --- a/config/arm/meson.build >> >> +++ b/config/arm/meson.build >> >> @@ -294,7 +294,8 @@ soc_cn10k =3D { >> >> 'flags': [ >> >> ['RTE_MAX_LCORE', 24], >> >> ['RTE_MAX_NUMA_NODES', 1], >> >> - ['RTE_MEMPOOL_ALIGN', 128] >> >> + ['RTE_MEMPOOL_ALIGN', 128], >> >> + ['RTE_IOVA_AS_VA', 1] >> >> ], >> >> 'part_number': '0xd49', >> >> 'extra_march_features': ['crypto'], >> >> @@ -370,7 +371,10 @@ soc_cn9k =3D { >> >> 'description': 'Marvell OCTEON 9', >> >> 'implementer': '0x43', >> >> 'part_number': '0xb2', >> >> - 'numa': false >> >> + 'numa': false, >> >> + 'flags': [ >> >> + ['RTE_IOVA_AS_VA', 1] >> >> + ] >> >> } >> > >> >I think this could go in a separate patch: "disable IOVA as PA for octe= ontx2/3" >> > >> >The reason is that this patch clearly breaks the API (m->buf_iova field >> >becomes invalid) and the ABI (mbuf fields are moved) for these >> >architectures. This ABI breakage has to be advertised in the release >> >note. In fact, it should have been advertised before, but I suppose it >> >does not impact general purpose arm distributions, so I guess it is ok. >> > >> >One other thing to highlight: enabling RTE_IOVA_AS_VA means that it >> >disable all drivers that do not have the pmd_iova_as_va flag. Are there >> >use-cases where drivers other than cnxk are used? For instance, is ther= e >> >a PCI bus which is likely to be used by a driver/* ? >> > >> >> All always enable drivers are enabled in this mode, which include >> bus/pci, bus/vdev and mempool/ring. > >I was thinking about use cases where a pci PMD (NIC, crypto, ...) is >used in addition to the SOC drivers. These PMD won't compile when IOVA >as PA is disabled, and the use case will be broken. > >This is probably a corner case (people at Marvell will know better than >me), I just wanted to highlight it. Should we document it? Thanks for noting. I will add this to cnxk platform document.