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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR11MB5817.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 168f8fce-de7b-4a4f-bdfa-08da52c2513b X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jun 2022 13:39:36.6036 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: qLLATqCkdYs8xfkQXkKNWDFJB4cl12yi8OR0xflF1AjFmYmf3+oYLKaN0Eb+290oAOWiHKaVSzASoSXJS3W+Hg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3638 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi, Thank you for the explanation. In that case I'd suggest instead of warping the branches=20 completely with macro, wrapping on the last "else" instead. Something like if (vector_mode =3D=3D IPSEC_MB_NOT_SUPPORTED) { /* Check CPU for supported vector instruction set */ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) vector_mode =3D IPSEC_MB_AVX512; else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) vector_mode =3D IPSEC_MB_AVX2; else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX)) vector_mode =3D IPSEC_MB_AVX; else #ifdef RTE_ARCH_X86_64=20 vector_mode =3D IPSEC_MB_SSE; #elif RTE_ARCH_ARM64 ? Vector_mode =3D IPSEC_MB_ARM64; /* newly introduced ARM vector mode */ #else /* error return */ #endif } This should also help setting RTE_CRYPTODEV_FF_CPU_ARM_CE in device feature= flag bitmap later. Regards, Fan > -----Original Message----- > From: Ashwin Sekhar Thalakalath Kottilveetil > Sent: Friday, June 17, 2022 11:34 AM > To: Zhang, Roy Fan ; dev@dpdk.org > Cc: Jerin Jacob Kollanukkaran ; Sunil Kumar Kori > ; Satha Koteswara Rao Kottidi > ; Pavan Nikhilesh Bhagavatula > ; Kiran Kumar Kokkilagadda > ; Satheesh Paul Antonysamy > ; Anoob Joseph ; Akhil Goyal > ; Harman Kalra ; Nithin Kumar > Dabilpuram > Subject: RE: [PATCH] crypto/ipsec_mb: enable compilation for non x86 arch >=20 > Hi Fan, >=20 > There is an ARM64 port for IPSEC-MB https://gitlab.arm.com/arm-reference- > solutions/ipsec-mb . >=20 > When we compile DPDK with this IPSEC-MB port for ARM64, the vector_mode > value doesn't matter. >=20 > And the cpuflag #defines RTE_CPUFLAG_AVX512F, RTE_CPUFLAG_AVX2 etc. > are not available in ARM64. So these need to be made x86 specific. >=20 > Thank you > Ashwin >=20 > Ashwin Sekhar T K >=20 > > -----Original Message----- > > From: Zhang, Roy Fan > > Sent: Friday, June 17, 2022 3:53 PM > > To: Ashwin Sekhar Thalakalath Kottilveetil ; > > dev@dpdk.org > > Cc: Jerin Jacob Kollanukkaran ; Sunil Kumar Kori > > ; Satha Koteswara Rao Kottidi > > ; Pavan Nikhilesh Bhagavatula > > ; Kiran Kumar Kokkilagadda > > ; Satheesh Paul Antonysamy > > ; Anoob Joseph ; Akhil > > Goyal ; Harman Kalra ; Nithin > > Kumar Dabilpuram > > Subject: [EXT] RE: [PATCH] crypto/ipsec_mb: enable compilation for non = x86 > > arch > > > > External Email > > > > ---------------------------------------------------------------------- > > Hi, > > > > IPsec-mb PMD should not be built at all if the library is not installed= . > > Also, the code you are warping with macro only prevents initializing th= e > > vector mode param to SSE which is later used to add feature flag bits. = To me > > this change does not make much sense. > > Can you share with me the purpose of this change? > > > > Regards, > > Fan > > > > > -----Original Message----- > > > From: Ashwin Sekhar T K > > > Sent: Friday, June 10, 2022 5:21 PM > > > To: dev@dpdk.org > > > Cc: jerinj@marvell.com; skori@marvell.com; skoteshwar@marvell.com; > > > pbhagavatula@marvell.com; kirankumark@marvell.com; > > > psatheesh@marvell.com; asekhar@marvell.com; anoobj@marvell.com; > > > gakhil@marvell.com; hkalra@marvell.com; ndabilpuram@marvell.com > > > Subject: [PATCH] crypto/ipsec_mb: enable compilation for non x86 arch > > > > > > Enable compilation for non x86 architectures by conditionally > > > compiling x86 specific code. > > > > > > Signed-off-by: Ashwin Sekhar T K > > > --- > > > drivers/crypto/ipsec_mb/ipsec_mb_private.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/drivers/crypto/ipsec_mb/ipsec_mb_private.c > > > b/drivers/crypto/ipsec_mb/ipsec_mb_private.c > > > index aab42c360c..9ea1110aaf 100644 > > > --- a/drivers/crypto/ipsec_mb/ipsec_mb_private.c > > > +++ b/drivers/crypto/ipsec_mb/ipsec_mb_private.c > > > @@ -53,6 +53,7 @@ ipsec_mb_create(struct rte_vdev_device *vdev, > > > const char *name, *args; > > > int retval; > > > > > > +#ifdef RTE_ARCH_X86_64 > > > if (vector_mode =3D=3D IPSEC_MB_NOT_SUPPORTED) { > > > /* Check CPU for supported vector instruction set */ > > > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) > > > @@ -64,6 +65,7 @@ ipsec_mb_create(struct rte_vdev_device *vdev, > > > else > > > vector_mode =3D IPSEC_MB_SSE; > > > } > > > +#endif > > > > > > init_params.private_data_size =3D sizeof(struct > > ipsec_mb_dev_private) + > > > pmd_data->internals_priv_size; > > > -- > > > 2.25.1