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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 4zpJeB8q4quWna5eDmD2a3+eCFYp0cIpsQAlQwVfCONM9OjF0ORj4eFuwa1ynekRqb2joQ1QqO6XaGEoAl4Vqtn95Jf0UFFCN9FG7Jpai/0/XACK/7jBtvzmONU9aL3mgnyYlYGAenFajPpQDbx+oHrJd4ATDwXZCRn0t59oT8i01y8bjKudvwv2fjaujQT1lWTL7jL9D0fOnk7p/LQub+9u+bsnj8QLnNctY2iae+OXEha+pagR/glVP6+jAUTACPUhuBvrKHPgTECgljjzA0BWG8GdHF8zoEHUiQyCPfEkkv+aaDWGqVYu4wq1MkGF09e4RIzNdVo1eaEgJ/vPSGko2ZbzViIiG3ZW78/BdDdnj1DGwxmoDD2dz/wmyarv7z9RRFng+KsuBRPmhlLrHI8bfdKUwwOjKZt6PSi9hqqPdChJQZqSQ/BV+uxbzFW/tBOLjJB7sgmqbuXW9ttePB4txVIYzLNW9ntjDzq7nAUgCulmz5iGUzHQ9WV0edg9dT9j3ue2x7L6HrCiEoZeXbLn6gE3dkqsoSJS2kJvOi/BUP3YszLIveBjx0Mu+B3z5BCQ7UHrUPkSllOaAGiymXGHzAfSu/SclIs7Sbc9Veea2cbvdAO26l8dK77szcEE8MJUswDPir4G4EOi5fqicw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4229c4d1-f8cf-4c4e-8091-08d86b0074da X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Oct 2020 20:34:57.2916 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GNoJwo2faKXhv3sTeeeBnvDp08J5S5udZvHG/LyAeR+08L0Q/mX5sA9fl03hDTaLOJEK5qHkNKsizDx28xnp7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB4985 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 11/22] event/dlb2: add port setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Friday, September 11, 2020 3:26 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH 11/22] event/dlb2: add port setup >=20 > Configure the load balanded (ldb) or directed (dir) port. > The consumer queue (CQ) and producer port (PP) are also > set up here. >=20 > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb2/dlb2.c | 527 +++++++++++++++++ > drivers/event/dlb2/dlb2_iface.c | 9 + > drivers/event/dlb2/dlb2_iface.h | 8 + > drivers/event/dlb2/pf/base/dlb2_resource.c | 921 > +++++++++++++++++++++++++++++ > drivers/event/dlb2/pf/dlb2_main.c | 28 + > drivers/event/dlb2/pf/dlb2_pf.c | 179 ++++++ > 6 files changed, 1672 insertions(+) >=20 > diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c > index 366e194..a4c8833 100644 > --- a/drivers/event/dlb2/dlb2.c > +++ b/drivers/event/dlb2/dlb2.c > @@ -1043,6 +1043,532 @@ dlb2_eventdev_queue_setup(struct rte_eventdev > *dev, > return ret; > } >=20 > +static int > +dlb2_init_consume_qe(struct dlb2_port *qm_port, char *mz_name) > +{ > + struct dlb2_cq_pop_qe *qe; > + > + qe =3D rte_malloc(mz_name, > + DLB2_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb2_cq_pop_qe), > + RTE_CACHE_LINE_SIZE); > + > + if (qe =3D=3D NULL) { > + DLB2_LOG_ERR("dlb2: no memory for consume_qe\n"); > + return -ENOMEM; > + } > + qm_port->consume_qe =3D qe; > + > + memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb2_cq_pop_qe)); You can use rte_zmalloc() instead (applies to other init_*_qe functions bel= ow too), and no need to zero-init the fields again after the memset. > + > + qe->qe_valid =3D 0; > + qe->qe_frag =3D 0; > + qe->qe_comp =3D 0; > + qe->cq_token =3D 1; > + /* Tokens value is 0-based; i.e. '0' returns 1 token, '1' returns 2, > + * and so on. > + */ > + qe->tokens =3D 0; /* set at run time */ > + qe->meas_lat =3D 0; > + qe->no_dec =3D 0; > + /* Completion IDs are disabled */ > + qe->cmp_id =3D 0; > + > + return 0; > +} > + > +static int > +dlb2_init_int_arm_qe(struct dlb2_port *qm_port, char *mz_name) > +{ > + struct dlb2_enqueue_qe *qe; > + > + qe =3D rte_malloc(mz_name, > + DLB2_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb2_enqueue_qe), > + RTE_CACHE_LINE_SIZE); > + > + if (qe =3D=3D NULL) { > + DLB2_LOG_ERR("dlb2: no memory for complete_qe\n"); > + return -ENOMEM; > + } > + qm_port->int_arm_qe =3D qe; > + > + memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb2_enqueue_qe)); > + > + /* V2 - INT ARM is CQ_TOKEN + FRAG */ > + qe->qe_valid =3D 0; > + qe->qe_frag =3D 1; > + qe->qe_comp =3D 0; > + qe->cq_token =3D 1; > + qe->meas_lat =3D 0; > + qe->no_dec =3D 0; > + /* Completion IDs are disabled */ > + qe->cmp_id =3D 0; > + > + return 0; > +} > + > +static int > +dlb2_init_qe_mem(struct dlb2_port *qm_port, char *mz_name) > +{ > + int ret, sz; > + > + sz =3D DLB2_NUM_QES_PER_CACHE_LINE * sizeof(struct > dlb2_enqueue_qe); > + > + qm_port->qe4 =3D rte_malloc(mz_name, sz, RTE_CACHE_LINE_SIZE); > + > + if (qm_port->qe4 =3D=3D NULL) { > + DLB2_LOG_ERR("dlb2: no qe4 memory\n"); > + ret =3D -ENOMEM; > + goto error_exit; > + } > + > + memset(qm_port->qe4, 0, sz); > + > + ret =3D dlb2_init_int_arm_qe(qm_port, mz_name); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: dlb2_init_int_arm_qe ret=3D%d\n", > + ret); This can fit on one line > + goto error_exit; > + } > + > + ret =3D dlb2_init_consume_qe(qm_port, mz_name); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: dlb2_init_consume_qe ret=3D%d\n", > + ret); This can fit on one line > + goto error_exit; > + } > + > + return 0; > + > +error_exit: > + > + dlb2_free_qe_mem(qm_port); > + > + return ret; > +} > + > +static int > +dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2, > + struct dlb2_eventdev_port *ev_port, > + uint32_t dequeue_depth, > + uint32_t enqueue_depth) > +{ > + struct dlb2_hw_dev *handle =3D &dlb2->qm_instance; > + struct dlb2_create_ldb_port_args cfg =3D {0}; > + int ret; > + struct dlb2_port *qm_port =3D NULL; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t qm_port_id; > + uint16_t ldb_credit_high_watermark; > + uint16_t dir_credit_high_watermark; > + > + if (handle =3D=3D NULL) > + return -EINVAL; > + > + if (dequeue_depth < DLB2_MIN_CQ_DEPTH || > + dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) { > + DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d- > %d\n", > + DLB2_MIN_CQ_DEPTH, > DLB2_MAX_INPUT_QUEUE_DEPTH); > + return -EINVAL; > + } > + > + if (enqueue_depth < DLB2_MIN_ENQUEUE_DEPTH) { > + DLB2_LOG_ERR("dlb2: invalid enqueue_depth, must be at least > %d\n", > + DLB2_MIN_ENQUEUE_DEPTH); > + return -EINVAL; > + } The dequeue and enqueue depth checks are suspiciously inconsistent -- only = the dequeue depth is compared against an upper bound. I suspect the enqueue upper bound= check is missing because it's already checked in both dlb2_eventdev_port_setup() and rte_event_port_setup()...if that's the case, can the dequeue depth max chec= k be dropped as well? > + > + rte_spinlock_lock(&handle->resource_lock); > + > + /* TODO - additional parameter validation */ Leftover TODO > + /* We round up to the next power of 2 if necessary */ > + cfg.cq_depth =3D rte_align32pow2(dequeue_depth); > + cfg.cq_depth_threshold =3D 1; > + > + cfg.cq_history_list_size =3D > DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; > + > + if (handle->cos_id =3D=3D DLB2_COS_DEFAULT) > + cfg.cos_id =3D 0; > + else > + cfg.cos_id =3D handle->cos_id; > + > + cfg.cos_strict =3D 0; > + > + /* User controls the LDB high watermark via enqueue depth. The DIR > high > + * watermark is equal, unless the directed credit pool is too small. > + */ > + ldb_credit_high_watermark =3D enqueue_depth; > + > + /* If there are no directed ports, the kernel driver will ignore this > + * port's directed credit settings. Don't use enqueue_depth if it would > + * require more directed credits than are available. > + */ > + dir_credit_high_watermark =3D > + RTE_MIN(enqueue_depth, > + handle->cfg.num_dir_credits / dlb2->num_ports); > + > + /* Per QM values */ > + > + /* DEBUG > + * DLB2_LOG_ERR("create ldb port - grp=3D%d, devId=3D%d\n", > + * handle->cfg.domain_id, handle->device_id); > + */ Leftover debug code > + > + ret =3D dlb2_iface_ldb_port_create(handle, &cfg, dlb2->poll_mode); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: dlb2_ldb_port_create error, ret=3D%d > (driver status: %s)\n", > + ret, dlb2_error_strings[cfg.response.status]); > + goto error_exit; > + } > + > + qm_port_id =3D cfg.response.id; > + > + DLB2_LOG_DBG("dlb2: ev_port %d uses qm LB port %d <<<<<\n", > + ev_port->id, qm_port_id); > + > + qm_port =3D &ev_port->qm_port; > + qm_port->ev_port =3D ev_port; /* back ptr */ > + qm_port->dlb2 =3D dlb2; /* back ptr */ > + /* > + * Allocate and init local qe struct(s). > + * Note: MOVDIR64 requires the enqueue QE (qe4) to be aligned. > + */ > + > + snprintf(mz_name, sizeof(mz_name), "%s_ldb_port%d", > + handle->device_name, > + ev_port->id); > + I see handle->device_name getting read here, in dlb2_hw_create_dir_port(), and also in dlb2_eventdev_dump(), but I don't see it written anywhere? > + ret =3D dlb2_init_qe_mem(qm_port, mz_name); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=3D%d\n", ret); > + goto error_exit; > + } > + > + qm_port->id =3D qm_port_id; > + > + qm_port->cached_ldb_credits =3D 0; > + qm_port->cached_dir_credits =3D 0; > + /* CQs with depth < 8 use an 8-entry queue, but withhold credits so > + * the effective depth is smaller. > + */ > + qm_port->cq_depth =3D cfg.cq_depth <=3D 8 ? 8 : cfg.cq_depth; > + qm_port->cq_idx =3D 0; > + qm_port->cq_idx_unmasked =3D 0; > + > + if (dlb2->poll_mode =3D=3D DLB2_CQ_POLL_MODE_SPARSE) > + qm_port->cq_depth_mask =3D (qm_port->cq_depth * 4) - 1; > + else > + qm_port->cq_depth_mask =3D qm_port->cq_depth - 1; > + > + qm_port->gen_bit_shift =3D __builtin_popcount(qm_port- > >cq_depth_mask); > + /* starting value of gen bit - it toggles at wrap time */ > + qm_port->gen_bit =3D 1; > + > + qm_port->int_armed =3D false; > + > + /* Save off for later use in info and lookup APIs. */ > + qm_port->qid_mappings =3D &dlb2->qm_ldb_to_ev_queue_id[0]; > + > + qm_port->dequeue_depth =3D dequeue_depth; > + qm_port->token_pop_thresh =3D dequeue_depth; > + > + qm_port->owed_tokens =3D 0; > + qm_port->issued_releases =3D 0; > + > + /* Save config message too. */ > + rte_memcpy(&qm_port->cfg.ldb, &cfg, sizeof(cfg)); I know qm_port->cfg.ldb and cfg are the same type, but just for safety in c= ase that ever changes in the future...probably better to use sizeof() on the destina= tion rather than the source. > + > + /* update state */ > + qm_port->state =3D PORT_STARTED; /* enabled at create time */ > + qm_port->config_state =3D DLB2_CONFIGURED; > + > + qm_port->dir_credits =3D dir_credit_high_watermark; > + qm_port->ldb_credits =3D ldb_credit_high_watermark; > + qm_port->credit_pool[DLB2_DIR_QUEUE] =3D &dlb2->dir_credit_pool; > + qm_port->credit_pool[DLB2_LDB_QUEUE] =3D &dlb2->ldb_credit_pool; > + > + DLB2_LOG_DBG("dlb2: created ldb port %d, depth =3D %d, ldb credits=3D%d= , > dir credits=3D%d\n", > + qm_port_id, > + dequeue_depth, > + qm_port->ldb_credits, > + qm_port->dir_credits); > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + return 0; > + > +error_exit: > + > + if (qm_port) > + dlb2_free_qe_mem(qm_port); > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + DLB2_LOG_ERR("dlb2: create ldb port failed!\n"); > + > + return ret; > +} > + > +static void > +dlb2_port_link_teardown(struct dlb2_eventdev *dlb2, > + struct dlb2_eventdev_port *ev_port) > +{ > + struct dlb2_eventdev_queue *ev_queue; > + int i; > + > + for (i =3D 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) { > + if (!ev_port->link[i].valid) > + continue; > + > + ev_queue =3D &dlb2->ev_queues[ev_port->link[i].queue_id]; > + > + ev_port->link[i].valid =3D false; > + ev_port->num_links--; > + ev_queue->num_links--; > + } > +} > + > +static int > +dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2, > + struct dlb2_eventdev_port *ev_port, > + uint32_t dequeue_depth, > + uint32_t enqueue_depth) > +{ > + struct dlb2_hw_dev *handle =3D &dlb2->qm_instance; > + struct dlb2_create_dir_port_args cfg =3D {0}; > + int ret; > + struct dlb2_port *qm_port =3D NULL; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t qm_port_id; > + uint16_t ldb_credit_high_watermark; > + uint16_t dir_credit_high_watermark; > + > + if (dlb2 =3D=3D NULL || handle =3D=3D NULL) > + return -EINVAL; > + > + if (dequeue_depth < DLB2_MIN_CQ_DEPTH || > + dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) { > + DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d- > %d\n", > + DLB2_MIN_CQ_DEPTH, > DLB2_MAX_INPUT_QUEUE_DEPTH); > + return -EINVAL; > + } Enqueue depth check needed? > + > + rte_spinlock_lock(&handle->resource_lock); > + > + /* Directed queues are configured at link time. */ > + cfg.queue_id =3D -1; > + > + /* We round up to the next power of 2 if necessary */ > + cfg.cq_depth =3D rte_align32pow2(dequeue_depth); > + cfg.cq_depth_threshold =3D 1; > + > + /* User controls the LDB high watermark via enqueue depth. The DIR > high > + * watermark is equal, unless the directed credit pool is too small. > + */ > + ldb_credit_high_watermark =3D enqueue_depth; > + > + /* Don't use enqueue_depth if it would require more directed credits > + * than are available. > + */ > + dir_credit_high_watermark =3D > + RTE_MIN(enqueue_depth, > + handle->cfg.num_dir_credits / dlb2->num_ports); > + > + /* Per QM values */ > + > + ret =3D dlb2_iface_dir_port_create(handle, &cfg, dlb2->poll_mode); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: dlb2_dir_port_create error, ret=3D%d (driver > status: %s)\n", > + ret, dlb2_error_strings[cfg.response.status]); > + goto error_exit; > + } > + > + qm_port_id =3D cfg.response.id; > + > + DLB2_LOG_DBG("dlb2: ev_port %d uses qm DIR port %d <<<<<\n", > + ev_port->id, qm_port_id); > + > + qm_port =3D &ev_port->qm_port; > + qm_port->ev_port =3D ev_port; /* back ptr */ > + qm_port->dlb2 =3D dlb2; /* back ptr */ > + > + /* > + * Init local qe struct(s). > + * Note: MOVDIR64 requires the enqueue QE to be aligned > + */ > + > + snprintf(mz_name, sizeof(mz_name), "%s_dir_port%d", > + handle->device_name, (See device_name comment above) > + ev_port->id); > + > + ret =3D dlb2_init_qe_mem(qm_port, mz_name); > + > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=3D%d\n", ret); > + goto error_exit; > + } > + > + qm_port->id =3D qm_port_id; > + > + qm_port->cached_ldb_credits =3D 0; > + qm_port->cached_dir_credits =3D 0; > + /* CQs with depth < 8 use an 8-entry queue, but withhold credits so > + * the effective depth is smaller. > + */ > + qm_port->cq_depth =3D cfg.cq_depth <=3D 8 ? 8 : cfg.cq_depth; > + qm_port->cq_idx =3D 0; > + qm_port->cq_idx_unmasked =3D 0; > + > + if (dlb2->poll_mode =3D=3D DLB2_CQ_POLL_MODE_SPARSE) > + qm_port->cq_depth_mask =3D (cfg.cq_depth * 4) - 1; > + else > + qm_port->cq_depth_mask =3D cfg.cq_depth - 1; > + > + qm_port->gen_bit_shift =3D __builtin_popcount(qm_port- > >cq_depth_mask); > + /* starting value of gen bit - it toggles at wrap time */ > + qm_port->gen_bit =3D 1; > + > + qm_port->int_armed =3D false; > + > + /* Save off for later use in info and lookup APIs. */ > + qm_port->qid_mappings =3D &dlb2->qm_dir_to_ev_queue_id[0]; > + > + qm_port->dequeue_depth =3D dequeue_depth; > + > + /* Directed ports are auto-pop, by default. */ > + qm_port->token_pop_mode =3D AUTO_POP; > + qm_port->owed_tokens =3D 0; > + qm_port->issued_releases =3D 0; > + > + /* Save config message too. */ > + rte_memcpy(&qm_port->cfg.dir, &cfg, sizeof(cfg)); (See sizeof() comment above) > + > + /* update state */ > + qm_port->state =3D PORT_STARTED; /* enabled at create time */ > + qm_port->config_state =3D DLB2_CONFIGURED; > + > + qm_port->dir_credits =3D dir_credit_high_watermark; > + qm_port->ldb_credits =3D ldb_credit_high_watermark; > + qm_port->credit_pool[DLB2_DIR_QUEUE] =3D &dlb2->dir_credit_pool; > + qm_port->credit_pool[DLB2_LDB_QUEUE] =3D &dlb2->ldb_credit_pool; > + > + DLB2_LOG_DBG("dlb2: created dir port %d, depth =3D %d cr=3D%d,%d\n", > + qm_port_id, > + dequeue_depth, > + dir_credit_high_watermark, > + ldb_credit_high_watermark); > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + return 0; > + > +error_exit: > + > + if (qm_port) > + dlb2_free_qe_mem(qm_port); > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + DLB2_LOG_ERR("dlb2: create dir port failed!\n"); > + > + return ret; > +} > + > +static int > +dlb2_eventdev_port_setup(struct rte_eventdev *dev, > + uint8_t ev_port_id, > + const struct rte_event_port_conf *port_conf) > +{ > + struct dlb2_eventdev *dlb2; > + struct dlb2_eventdev_port *ev_port; > + int ret; > + > + if (dev =3D=3D NULL || port_conf =3D=3D NULL) { > + DLB2_LOG_ERR("Null parameter\n"); > + return -EINVAL; > + } > + > + dlb2 =3D dlb2_pmd_priv(dev); > + > + if (ev_port_id >=3D DLB2_MAX_NUM_PORTS) > + return -EINVAL; > + > + if (port_conf->dequeue_depth > > + evdev_dlb2_default_info.max_event_port_dequeue_depth || > + port_conf->enqueue_depth > > + evdev_dlb2_default_info.max_event_port_enqueue_depth) > + return -EINVAL; > + > + ev_port =3D &dlb2->ev_ports[ev_port_id]; > + /* configured? */ > + if (ev_port->setup_done) { > + DLB2_LOG_ERR("evport %d is already configured\n", > ev_port_id); > + return -EINVAL; > + } > + > + /* The reserved token interrupt arming scheme requires that one or > more > + * CQ tokens be reserved by the PMD. This limits the amount of CQ space > + * usable by the DLB, so in order to give an *effective* CQ depth equal > + * to the user-requested value, we double CQ depth and reserve half of > + * its tokens. If the user requests the max CQ depth (256) then we > + * cannot double it, so we reserve one token and give an effective > + * depth of 255 entries. > + */ I don't think this comment applies to the 2.0 device. > + > + ev_port->qm_port.is_directed =3D port_conf->event_port_cfg & > + RTE_EVENT_PORT_CFG_SINGLE_LINK; > + > + if (!ev_port->qm_port.is_directed) { > + ret =3D dlb2_hw_create_ldb_port(dlb2, > + ev_port, > + port_conf->dequeue_depth, > + port_conf->enqueue_depth); > + if (ret < 0) { > + DLB2_LOG_ERR("Failed to create the lB port ve > portId=3D%d\n", > + ev_port_id); > + > + return ret; > + } > + } else { > + ret =3D dlb2_hw_create_dir_port(dlb2, > + ev_port, > + port_conf->dequeue_depth, > + port_conf->enqueue_depth); > + if (ret < 0) { > + DLB2_LOG_ERR("Failed to create the DIR port\n"); > + return ret; > + } > + } > + > + /* Save off port config for reconfig */ > + dlb2->ev_ports[ev_port_id].conf =3D *port_conf; Nit: 'ev_port' is assigned to &dlb2->ev_ports[ev_port_id] above, use it her= e and below? > + > + dlb2->ev_ports[ev_port_id].id =3D ev_port_id; > + dlb2->ev_ports[ev_port_id].enq_configured =3D true; > + dlb2->ev_ports[ev_port_id].setup_done =3D true; > + dlb2->ev_ports[ev_port_id].inflight_max =3D > + port_conf->new_event_threshold; > + dlb2->ev_ports[ev_port_id].implicit_release =3D > + !(port_conf->event_port_cfg & > + RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL); > + dlb2->ev_ports[ev_port_id].outstanding_releases =3D 0; > + dlb2->ev_ports[ev_port_id].inflight_credits =3D 0; > + dlb2->ev_ports[ev_port_id].credit_update_quanta =3D > + RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA; > + dlb2->ev_ports[ev_port_id].dlb2 =3D dlb2; /* reverse link */ > + > + /* Tear down pre-existing port->queue links */ > + if (dlb2->run_state =3D=3D DLB2_RUN_STATE_STOPPED) > + dlb2_port_link_teardown(dlb2, &dlb2->ev_ports[ev_port_id]); > + > + dev->data->ports[ev_port_id] =3D &dlb2->ev_ports[ev_port_id]; > + > + return 0; > +} [...] > diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2= _pf.c > index dea70e6..a6824b1 100644 > --- a/drivers/event/dlb2/pf/dlb2_pf.c > +++ b/drivers/event/dlb2/pf/dlb2_pf.c > @@ -234,6 +234,183 @@ dlb2_pf_set_sn_allocation(struct dlb2_hw_dev > *handle, > return ret; > } >=20 > +static void * > +dlb2_alloc_coherent_aligned(uintptr_t *phys, size_t size, int align) > +{ > + const struct rte_memzone *mz; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t core_id =3D rte_lcore_id(); > + unsigned int socket_id; > + > + snprintf(mz_name, sizeof(mz_name) - 1, "%lx", > + (unsigned long)rte_get_timer_cycles()); For debug purposes, it would be better if this name can trace the mz back t= o this driver. How about something like event_dlb2_pf_name + ldb/dir_port + p= ort ID? > + if (core_id =3D=3D (unsigned int)LCORE_ID_ANY) > + core_id =3D rte_get_master_lcore(); > + socket_id =3D rte_lcore_to_socket_id(core_id); Should this use the socket ID devarg (and perhaps fall back to the core's s= ocket if unspecified)? > + mz =3D rte_memzone_reserve_aligned(mz_name, size, socket_id, > + RTE_MEMZONE_IOVA_CONTIG, align); > + if (!mz) { > + DLB2_LOG_DBG("Unable to allocate DMA memory of size %zu > bytes - %s\n", > + size, rte_strerror(rte_errno)); > + *phys =3D 0; > + return NULL; > + } > + *phys =3D mz->iova; > + return mz->addr; > +} > + > +static int > +dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle, > + struct dlb2_create_ldb_port_args *cfg, > + enum dlb2_cq_poll_modes poll_mode) > +{ > + struct dlb2_dev *dlb2_dev =3D (struct dlb2_dev *)handle->pf_dev; > + struct dlb2_cmd_response response =3D {0}; > + struct dlb2_port_memory port_memory; > + int ret, cq_alloc_depth; > + uint8_t *port_base; > + int alloc_sz, qe_sz; > + phys_addr_t cq_base; > + phys_addr_t pp_base; > + int is_dir =3D false; > + > + DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__); > + > + if (poll_mode =3D=3D DLB2_CQ_POLL_MODE_STD) > + qe_sz =3D sizeof(struct dlb2_dequeue_qe); > + else > + qe_sz =3D RTE_CACHE_LINE_SIZE; > + > + /* Calculate the port memory required, and round up to the nearest > + * cache line. > + */ > + cq_alloc_depth =3D RTE_MAX(cfg->cq_depth, > DLB2_MIN_HARDWARE_CQ_DEPTH); > + alloc_sz =3D cq_alloc_depth * qe_sz; > + alloc_sz =3D RTE_CACHE_LINE_ROUNDUP(alloc_sz); > + > + port_base =3D dlb2_alloc_coherent_aligned(&cq_base, > + alloc_sz, > + PAGE_SIZE); This can fit on one line > + if (port_base =3D=3D NULL) > + return -ENOMEM; > + > + /* Lock the page in memory */ > + ret =3D rte_mem_lock_page(port_base); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device > i/o\n"); > + goto create_port_err; > + } > + > + > + memset(port_base, 0, alloc_sz); > + > + ret =3D dlb2_pf_create_ldb_port(&dlb2_dev->hw, > + handle->domain_id, > + cfg, > + cq_base, > + &response); > + if (ret) > + goto create_port_err; > + > + pp_base =3D (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir); > + dlb2_port[response.id][DLB2_LDB_PORT].pp_addr =3D > + (void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id)); If pp_base is defined as a uintptr_t, I think you can avoid some of the exp= licit casts. > + > + dlb2_port[response.id][DLB2_LDB_PORT].cq_base =3D > + (void *)(uintptr_t)(port_base); Since port_base is a uint8_t*, the uintptr_t cast shouldn't be necessary > + memset(&port_memory, 0, sizeof(port_memory)); > + dlb2_list_init_head(&port_memory.list); > + > + /* Fill out the per-port memory tracking structure */ > + dlb2_dev->ldb_port_pages[response.id].valid =3D true; > + dlb2_list_splice(&port_memory.list, > + &dlb2_dev->ldb_port_pages[response.id].list); Does the list serve any purpose? Looks like port_memory is zero-initialized= , then it becomes the sole entry on a per-port list. > + > + cfg->response =3D response; > + > + DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=3D%d\n", > + __func__, ret); > + > +create_port_err: Need to free the memzone in this case. > + > + return ret; > +} > + > +static int > +dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle, > + struct dlb2_create_dir_port_args *cfg, > + enum dlb2_cq_poll_modes poll_mode) > +{ > + struct dlb2_dev *dlb2_dev =3D (struct dlb2_dev *)handle->pf_dev; > + struct dlb2_cmd_response response =3D {0}; > + struct dlb2_port_memory port_memory; > + int ret; > + uint8_t *port_base; > + int alloc_sz, qe_sz; > + phys_addr_t cq_base; > + phys_addr_t pp_base; > + int is_dir =3D true; > + > + DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__); > + > + if (poll_mode =3D=3D DLB2_CQ_POLL_MODE_STD) > + qe_sz =3D sizeof(struct dlb2_dequeue_qe); > + else > + qe_sz =3D RTE_CACHE_LINE_SIZE; > + > + /* Calculate the port memory required, and round up to the nearest > + * cache line. > + */ > + alloc_sz =3D cfg->cq_depth * qe_sz; > + alloc_sz =3D RTE_CACHE_LINE_ROUNDUP(alloc_sz); > + > + port_base =3D dlb2_alloc_coherent_aligned(&cq_base, > + alloc_sz, > + PAGE_SIZE); This can fit on one line > + if (port_base =3D=3D NULL) > + return -ENOMEM; > + > + /* Lock the page in memory */ > + ret =3D rte_mem_lock_page(port_base); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device > i/o\n"); > + goto create_port_err; > + } > + > + memset(port_base, 0, alloc_sz); > + > + ret =3D dlb2_pf_create_dir_port(&dlb2_dev->hw, > + handle->domain_id, > + cfg, > + cq_base, > + &response); > + if (ret) > + goto create_port_err; > + > + pp_base =3D (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir); (See uintptr_t comment above) > + dlb2_port[response.id][DLB2_DIR_PORT].pp_addr =3D > + (void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id)); > + > + dlb2_port[response.id][DLB2_DIR_PORT].cq_base =3D > + (void *)(uintptr_t)(port_base); (See port_base comment above) > + memset(&port_memory, 0, sizeof(port_memory)); > + dlb2_list_init_head(&port_memory.list); > + > + /* Fill out the per-port memory tracking structure */ > + dlb2_dev->dir_port_pages[response.id].valid =3D true; > + dlb2_list_splice(&port_memory.list, > + &dlb2_dev->dir_port_pages[response.id].list); > + (See list comment above) > + cfg->response =3D response; > + > + DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=3D%d\n", > + __func__, ret); > + > +create_port_err: Need to free the memzone in this case > + > + return ret; > +} > + > static void > dlb2_pf_iface_fn_ptrs_init(void) > { > @@ -247,6 +424,8 @@ dlb2_pf_iface_fn_ptrs_init(void) > dlb2_iface_get_cq_poll_mode =3D dlb2_pf_get_cq_poll_mode; > dlb2_iface_sched_domain_create =3D dlb2_pf_sched_domain_create; > dlb2_iface_ldb_queue_create =3D dlb2_pf_ldb_queue_create; > + dlb2_iface_ldb_port_create =3D dlb2_pf_ldb_port_create; > + dlb2_iface_dir_port_create =3D dlb2_pf_dir_port_create; > dlb2_iface_get_sn_allocation =3D dlb2_pf_get_sn_allocation; > dlb2_iface_set_sn_allocation =3D dlb2_pf_set_sn_allocation; > dlb2_iface_get_sn_occupancy =3D dlb2_pf_get_sn_occupancy; > -- > 2.6.4 I don't see the port memzones getting freed anywhere, e.g. if the event dev= ice is reset. Looks like a possible memory leak. Thanks, Gage