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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: tB/0VCBm2ECdmTUOMNtJfE/iW8rRfoiKJan52NrezP0W5BxSMRjrj9dNe+cJGmOoWqQpm55wMdk114qGCZhOzPKzyb1/M7RvIZk8KZK1RKdGxgAVg0Kl12oETX23CL2nWwnL+v2D93K/rv3Knva7IhHsG8o4msrp1gsmZCCJ8AvkzdmdvsUdUrk9ItIg1fa9mkh2lds2LtrnPDeymqBHu9hElTVVg4sndMZGGphia6kawW3MD6wyb3Sw0AnRhNs4w+Q6IDi0O7B10kRBaQYqJ6ZaGRHRux8dRQKy2kzzpO8krUtSAxNeaRmlOE7vROWC+q8bhqYrvQB9gkN4Th8+9R+NYYAjCs+ugFTU9KGKo1U0i27ANRgsgeqrmtbBTOHsI4Sitk+3H2091o1D69GFUKwr5iYjjbasGC81/9PMpOHB7LdRArYq/8suS5tmkgPJ4tgyY0TPCvjX1HsxmSfB8RZzJK4jIJEH19NSE5XugWKmNPgSs+RDvOWzA+xz6lu/SIGL9xvzDSvplhb6efCKnMIo6F+roJrBR5vC1L1Ib/p90GrMsU2kx5FnNz/Dm+Y+noOmdMdMIzfPmfebvOJxM7s8ilt8OGwRutEPhPlzWSRwkIzbCEp/dNOtWQ6N50wwTFHTM/0nAzU77GlEI4939Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7de9b17c-8bc9-4101-a556-08d86bcd4d83 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 21:01:18.4326 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: I+ybc2B/HGZr4+Hp+Q8SSP0xz8Boi3ds/0TIyU9eoHuzh6GdZd7oy0l+xINKa6n9tkVkAL8IY1xvBb7vXJGy1Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3198 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v4 08/22] event/dlb: add infos get and configure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Friday, September 11, 2020 2:18 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH v4 08/22] event/dlb: add infos get and configure >=20 > Add support for configuring the DLB hardware. Please expand the commit message. >=20 > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb/dlb.c | 402 +++ > drivers/event/dlb/dlb_iface.c | 11 + > drivers/event/dlb/dlb_iface.h | 11 + > drivers/event/dlb/pf/base/dlb_resource.c | 4098 > +++++++++++++++++++++++++++++- > drivers/event/dlb/pf/dlb_pf.c | 88 + > 5 files changed, 4517 insertions(+), 93 deletions(-) >=20 > diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c > index f89edf2..2dba396 100644 > --- a/drivers/event/dlb/dlb.c > +++ b/drivers/event/dlb/dlb.c > @@ -140,6 +140,23 @@ dlb_hw_query_resources(struct dlb_eventdev *dlb) > return 0; > } >=20 > +void > +dlb_free_qe_mem(struct dlb_port *qm_port) > +{ > + if (qm_port =3D=3D NULL) > + return; > + > + if (qm_port->qe4) { > + rte_free(qm_port->qe4); > + qm_port->qe4 =3D NULL; > + } > + > + if (qm_port->consume_qe) { > + rte_free(qm_port->consume_qe); > + qm_port->consume_qe =3D NULL; > + } > +} Checking for NULL is not strictly required, rte_free() will simply return i= n that case. > + > /* Wrapper for string to int conversion. Substituted for atoi(...), whic= h is > * unsafe. > */ > @@ -231,6 +248,389 @@ set_num_dir_credits(const char *key __rte_unused, > DLB_MAX_NUM_DIR_CREDITS); > return -EINVAL; > } > + return 0; > +} > + > +/* VDEV-only notes: > + * This function first unmaps all memory mappings and closes the > + * domain's file descriptor, which causes the driver to reset the > + * scheduling domain. Once that completes (when close() returns), we > + * can safely free the dynamically allocated memory used by the > + * scheduling domain. > + * > + * PF-only notes: > + * We will maintain a use count and use that to determine when > + * a reset is required. In PF mode, we never mmap, or munmap > + * device memory, and we own the entire physical PCI device. > + */ > + > +static void > +dlb_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig) > +{ > + struct dlb_eventdev *dlb =3D dlb_pmd_priv(dev); > + enum dlb_configuration_state config_state; > + int i, j; > + > + /* Close and reset the domain */ > + dlb_iface_domain_close(dlb); > + > + /* Free all dynamically allocated port memory */ > + for (i =3D 0; i < dlb->num_ports; i++) > + dlb_free_qe_mem(&dlb->ev_ports[i].qm_port); > + > + /* If reconfiguring, mark the device's queues and ports as "previously > + * configured." If the user does not reconfigure them, the PMD will > + * reapply their previous configuration when the device is started. > + */ > + config_state =3D (reconfig) ? DLB_PREV_CONFIGURED : > DLB_NOT_CONFIGURED; > + > + for (i =3D 0; i < dlb->num_ports; i++) { > + dlb->ev_ports[i].qm_port.config_state =3D config_state; > + /* Reset setup_done so ports can be reconfigured */ > + dlb->ev_ports[i].setup_done =3D false; > + for (j =3D 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++) > + dlb->ev_ports[i].link[j].mapped =3D false; > + } > + > + for (i =3D 0; i < dlb->num_queues; i++) > + dlb->ev_queues[i].qm_queue.config_state =3D config_state; > + > + for (i =3D 0; i < DLB_MAX_NUM_QUEUES; i++) > + dlb->ev_queues[i].setup_done =3D false; > + > + dlb->num_ports =3D 0; > + dlb->num_ldb_ports =3D 0; > + dlb->num_dir_ports =3D 0; > + dlb->num_queues =3D 0; > + dlb->num_ldb_queues =3D 0; > + dlb->num_dir_queues =3D 0; > + dlb->configured =3D false; > +} > + > +static int > +dlb_ldb_credit_pool_create(struct dlb_hw_dev *handle) > +{ > + struct dlb_create_ldb_pool_args cfg; > + struct dlb_cmd_response response; > + int ret; > + > + if (handle =3D=3D NULL) > + return -EINVAL; > + > + if (!handle->cfg.resources.num_ldb_credits) { > + handle->cfg.ldb_credit_pool_id =3D 0; > + handle->cfg.num_ldb_credits =3D 0; > + return 0; > + } > + > + cfg.response =3D (uintptr_t)&response; > + cfg.num_ldb_credits =3D handle->cfg.resources.num_ldb_credits; > + > + ret =3D dlb_iface_ldb_credit_pool_create(handle, > + &cfg); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: ldb_credit_pool_create ret=3D%d (driver > status: %s)\n", > + ret, dlb_error_strings[response.status]); > + } > + > + handle->cfg.ldb_credit_pool_id =3D response.id; > + handle->cfg.num_ldb_credits =3D cfg.num_ldb_credits; > + > + return ret; > +} > + > +static int > +dlb_dir_credit_pool_create(struct dlb_hw_dev *handle) > +{ > + struct dlb_create_dir_pool_args cfg; > + struct dlb_cmd_response response; > + int ret; > + > + if (handle =3D=3D NULL) > + return -EINVAL; > + > + if (!handle->cfg.resources.num_dir_credits) { > + handle->cfg.dir_credit_pool_id =3D 0; > + handle->cfg.num_dir_credits =3D 0; > + return 0; > + } > + > + cfg.response =3D (uintptr_t)&response; > + cfg.num_dir_credits =3D handle->cfg.resources.num_dir_credits; > + > + ret =3D dlb_iface_dir_credit_pool_create(handle, &cfg); > + if (ret < 0) > + DLB_LOG_ERR("dlb: dir_credit_pool_create ret=3D%d (driver > status: %s)\n", > + ret, dlb_error_strings[response.status]); > + > + handle->cfg.dir_credit_pool_id =3D response.id; > + handle->cfg.num_dir_credits =3D cfg.num_dir_credits; > + > + return ret; > +} > + > +static int > +dlb_hw_create_sched_domain(struct dlb_hw_dev *handle, > + struct dlb_eventdev *dlb, > + const struct dlb_hw_rsrcs *resources_asked) > +{ > + int ret =3D 0; > + struct dlb_create_sched_domain_args *config_params; > + struct dlb_cmd_response response; > + > + if (resources_asked =3D=3D NULL) { > + DLB_LOG_ERR("dlb: dlb_create NULL parameter\n"); > + ret =3D EINVAL; > + goto error_exit; > + } > + > + /* Map generic qm resources to dlb resources */ > + config_params =3D &handle->cfg.resources; > + > + config_params->response =3D (uintptr_t)&response; > + > + /* DIR ports and queues */ > + > + config_params->num_dir_ports =3D > + resources_asked->num_dir_ports; > + > + config_params->num_dir_credits =3D > + resources_asked->num_dir_credits; > + > + /* LDB ports and queues */ > + > + config_params->num_ldb_queues =3D > + resources_asked->num_ldb_queues; > + > + config_params->num_ldb_ports =3D > + resources_asked->num_ldb_ports; > + > + config_params->num_ldb_credits =3D > + resources_asked->num_ldb_credits; > + > + config_params->num_atomic_inflights =3D > + dlb->num_atm_inflights_per_queue * > + config_params->num_ldb_queues; > + > + config_params->num_hist_list_entries =3D config_params- > >num_ldb_ports * > + DLB_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; > + > + /* dlb limited to 1 credit pool per queue type */ > + config_params->num_ldb_credit_pools =3D 1; > + config_params->num_dir_credit_pools =3D 1; > + > + DLB_LOG_DBG("sched domain create - ldb_qs=3D%d, ldb_ports=3D%d, > dir_ports=3D%d, atomic_inflights=3D%d, hist_list_entries=3D%d, ldb_credit= s=3D%d, > dir_credits=3D%d, ldb_cred_pools=3D%d, dir-credit_pools=3D%d\n", > + config_params->num_ldb_queues, > + config_params->num_ldb_ports, > + config_params->num_dir_ports, > + config_params->num_atomic_inflights, > + config_params->num_hist_list_entries, > + config_params->num_ldb_credits, > + config_params->num_dir_credits, > + config_params->num_ldb_credit_pools, > + config_params->num_dir_credit_pools); > + > + /* Configure the QM */ > + > + ret =3D dlb_iface_sched_domain_create(handle, config_params); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: domain create failed, device_id =3D %d, (driver > ret =3D %d, extra status: %s)\n", > + handle->device_id, > + ret, > + dlb_error_strings[response.status]); > + goto error_exit; > + } > + > + handle->domain_id =3D response.id; > + handle->domain_id_valid =3D 1; > + > + config_params->response =3D 0; > + > + ret =3D dlb_ldb_credit_pool_create(handle); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: create ldb credit pool failed\n"); > + goto error_exit2; > + } > + > + ret =3D dlb_dir_credit_pool_create(handle); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: create dir credit pool failed\n"); > + goto error_exit2; > + } > + > + handle->cfg.configured =3D true; > + > + return 0; > + > +error_exit2: > + dlb_iface_domain_close(dlb); > + > +error_exit: > + return ret; > +} > + > +/* End HW specific */ > +static void > +dlb_eventdev_info_get(struct rte_eventdev *dev, > + struct rte_event_dev_info *dev_info) > +{ > + struct dlb_eventdev *dlb =3D dlb_pmd_priv(dev); > + int ret; > + > + ret =3D dlb_hw_query_resources(dlb); > + if (ret) { > + const struct rte_eventdev_data *data =3D dev->data; > + > + DLB_LOG_ERR("get resources err=3D%d, devid=3D%d\n", > + ret, data->dev_id); > + /* fn is void, so fall through and return values set up in > + * probe > + */ > + } > + > + /* Add num resources currently owned by this domain. > + * These would become available if the scheduling domain were reset > due > + * to the application recalling eventdev_configure to *reconfigure* the > + * domain. > + */ > + evdev_dlb_default_info.max_event_ports +=3D dlb->num_ldb_ports; > + evdev_dlb_default_info.max_event_queues +=3D dlb->num_ldb_queues; > + evdev_dlb_default_info.max_num_events +=3D dlb->num_ldb_credits; > + > + Nit: extra whitespace > + /* In DLB A-stepping hardware, applications are limited to 128 > + * configured ports (load-balanced or directed). The reported number of > + * available ports must reflect this. > + */ > + if (dlb->revision < DLB_REV_B0) { > + int used_ports; > + > + used_ports =3D DLB_MAX_NUM_LDB_PORTS + > DLB_MAX_NUM_DIR_PORTS - > + dlb->hw_rsrc_query_results.num_ldb_ports - > + dlb->hw_rsrc_query_results.num_dir_ports; > + > + evdev_dlb_default_info.max_event_ports =3D > + RTE_MIN(evdev_dlb_default_info.max_event_ports, > + 128 - used_ports); > + } > + > + evdev_dlb_default_info.max_event_queues =3D > + RTE_MIN(evdev_dlb_default_info.max_event_queues, > + RTE_EVENT_MAX_QUEUES_PER_DEV); > + > + evdev_dlb_default_info.max_num_events =3D > + RTE_MIN(evdev_dlb_default_info.max_num_events, > + dlb->max_num_events_override); > + > + *dev_info =3D evdev_dlb_default_info; > +} > + > +/* Note: 1 QM instance per QM device, QM instance/device =3D=3D event de= vice */ > +static int > +dlb_eventdev_configure(const struct rte_eventdev *dev) > +{ > + struct dlb_eventdev *dlb =3D dlb_pmd_priv(dev); > + struct dlb_hw_dev *handle =3D &dlb->qm_instance; > + struct dlb_hw_rsrcs *rsrcs =3D &handle->info.hw_rsrc_max; > + const struct rte_eventdev_data *data =3D dev->data; > + const struct rte_event_dev_config *config =3D &data->dev_conf; > + int ret; > + > + /* If this eventdev is already configured, we must release the current > + * scheduling domain before attempting to configure a new one. > + */ > + if (dlb->configured) { > + dlb_hw_reset_sched_domain(dev, true); > + > + ret =3D dlb_hw_query_resources(dlb); > + if (ret) { > + DLB_LOG_ERR("get resources err=3D%d, devid=3D%d\n", > + ret, data->dev_id); > + return ret; > + } > + } > + > + if (config->nb_event_queues > rsrcs->num_queues) { > + DLB_LOG_ERR("nb_event_queues parameter (%d) exceeds the > QM device's capabilities (%d).\n", > + config->nb_event_queues, > + rsrcs->num_queues); > + return -EINVAL; > + } > + if (config->nb_event_ports > (rsrcs->num_ldb_ports > + + rsrcs->num_dir_ports)) { > + DLB_LOG_ERR("nb_event_ports parameter (%d) exceeds the > QM device's capabilities (%d).\n", > + config->nb_event_ports, > + (rsrcs->num_ldb_ports + rsrcs->num_dir_ports)); > + return -EINVAL; > + } > + if (config->nb_events_limit > rsrcs->nb_events_limit) { > + DLB_LOG_ERR("nb_events_limit parameter (%d) exceeds the > QM device's capabilities (%d).\n", > + config->nb_events_limit, > + rsrcs->nb_events_limit); > + return -EINVAL; > + } > + > + if (config->event_dev_cfg & > RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) { > + dlb->global_dequeue_wait =3D false; Nit: don't use braces on single-statement conditionals Thanks, Gage