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Tue, 20 Oct 2020 14:04:32 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH v2 20/22] event/dlb2: add queue and port release Thread-Index: AQHWpLIX+u9RSxieeEql4VOUKIfFsamgg5PA Date: Tue, 20 Oct 2020 14:04:32 +0000 Message-ID: References: <1599855987-25976-2-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-1-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-21-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1602958879-8558-21-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [68.203.30.51] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5086a9cb-7a95-4a41-b546-08d87501119c x-ms-traffictypediagnostic: SA2PR11MB5097: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5797; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5086a9cb-7a95-4a41-b546-08d87501119c X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Oct 2020 14:04:32.2925 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7D6ovPGNhpdk/QOxfgXwcXe6TxccIJZi1ezfelH7fD92IXI9bwZgSlZ1loGQ4YbFmI1YJo3P+SsSh1xhkbO1Ag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB5097 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 20/22] event/dlb2: add queue and port release X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Saturday, October 17, 2020 1:21 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH v2 20/22] event/dlb2: add queue and port release >=20 > DLB does not support reconfiguring individual queues > or ports on the fly. The entire device must be reconfigured. > Previously allocated port QE ond memzone memory > is freed in this patch. >=20 > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb2/dlb2.c | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c > index 06a59a5..968923e 100644 > --- a/drivers/event/dlb2/dlb2.c > +++ b/drivers/event/dlb2/dlb2.c > @@ -89,8 +89,8 @@ dlb2_free_qe_mem(struct dlb2_port *qm_port) > rte_free(qm_port->consume_qe); > qm_port->consume_qe =3D NULL; >=20 > - rte_free(dlb2_port[qm_port->id][PORT_TYPE(qm_port)].cq_base); > - rte_free(dlb2_port[qm_port->id][PORT_TYPE(qm_port)].pp_addr); > + rte_memzone_free(dlb2_port[qm_port- > >id][PORT_TYPE(qm_port)].mz); > + dlb2_port[qm_port->id][PORT_TYPE(qm_port)].mz =3D NULL; > } This code should be a part of patch 8, when free_qe_mem is introduced. With= that change: Reviewed-by: Gage Eads Thanks, Gage