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Fri, 30 Oct 2020 19:51:37 +0000 Received: from SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a]) by SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a%4]) with mapi id 15.20.3499.029; Fri, 30 Oct 2020 19:51:37 +0000 From: "Eads, Gage" <gage.eads@intel.com> To: "McDaniel, Timothy" <timothy.mcdaniel@intel.com> CC: "dev@dpdk.org" <dev@dpdk.org>, "Carrillo, Erik G" <erik.g.carrillo@intel.com>, "Van Haaren, Harry" <harry.van.haaren@intel.com>, "jerinj@marvell.com" <jerinj@marvell.com>, "thomas@monjalon.net" <thomas@monjalon.net> Thread-Topic: [PATCH v10 18/23] event/dlb: add dequeue and its burst variants Thread-Index: AQHWruov4qO9JXFD30+BwKfmw97tr6mwjTWA Date: Fri, 30 Oct 2020 19:51:37 +0000 Message-ID: <SN6PR11MB25746B3CD338FCFA278E4951F6150@SN6PR11MB2574.namprd11.prod.outlook.com> References: <20200612212434.6852-2-timothy.mcdaniel@intel.com> <1604082458-15368-1-git-send-email-timothy.mcdaniel@intel.com> <1604082458-15368-19-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1604082458-15368-19-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c4c8bc7f-7dc9-439c-7610-08d87d0d3646 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Oct 2020 19:51:37.0300 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: X784eUdsrhAfhh8gPqn5WZdmDr3m0Ix8RGglEd4DaQNjbdJTGWqxRzdSSdFpybPXuonV+6a+/uVUZ0J4iJhm/g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3343 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v10 18/23] event/dlb: add dequeue and its burst variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> > -----Original Message----- > From: McDaniel, Timothy <timothy.mcdaniel@intel.com> > Sent: Friday, October 30, 2020 1:28 PM > Cc: dev@dpdk.org; Carrillo, Erik G <erik.g.carrillo@intel.com>; Eads, Gag= e > <gage.eads@intel.com>; Van Haaren, Harry <harry.van.haaren@intel.com>; > jerinj@marvell.com; thomas@monjalon.net > Subject: [PATCH v10 18/23] event/dlb: add dequeue and its burst variants >=20 > Add support for dequeue, dequeue_burst, ... >=20 > DLB does not currently support interrupts, but instead uses > umonitor/umwait if supported by the processor. This allows > the software to monitor and wait on writes to a cache-line. >=20 > DLB supports normal and sparse cq mode. In normal mode the > hardware will pack 4 QEs into each cache line. In sparse cq > mode, the hardware will only populate one QE per cache line. > Software must be aware of the cq mode, and take the appropriate > actions, based on the mode. >=20 > Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com> I believe I added my tag to the v5 of this patch, but for good measure: Reviewed-by: Gage Eads <gage.eads@intel.com> Thanks, Gage