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Wed, 7 Oct 2020 21:18:40 +0000 Received: from SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a]) by SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a%4]) with mapi id 15.20.3455.021; Wed, 7 Oct 2020 21:18:40 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH 16/22] event/dlb2: add dequeue and its burst variants Thread-Index: AQHWiHpe1awmZ7WuwEKbpKqOBAcYWKmMyWmw Date: Wed, 7 Oct 2020 21:18:40 +0000 Message-ID: References: <1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com> <1599855987-25976-17-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1599855987-25976-17-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: ewdfZ82YPc1yKwYb6kHP3XqVPK5WTEEGIFUXasxOOtmkFKUrrSI9nqbbX5EDTHSpGr7MITQIVd2QSUcHRh/X/DBP1foXoF2sDUM+WkKtYwdsHcLM2c1Zt5OBFyrJn1TBWgabhn1Ol21c78iP00tcn0HArjHrd/P9vuxxF1Yt52YwQQpr1rhBrs8LnfoGBbs7jYcydLzKxsNYsODrHifeJgtpKjm52Rvn1DcvTNJULyZSFsCCbNPWeJsZEDd31GpCSgQjcQEm1Hx3LJkfazYOB7hDiWM7gI/KWruGILXTrLiL/cZZDZ/txNWYp8jWgefvd3m72HnwyGzuLM8CM3LsggPCEQlPTkT/AN8Iqw8Sn0RQHVUgAqofDcgDlevvnkoN92qS3WwNUgfsvYr8iabTeh9VIR8rm9uPFujjWCImRPXvAu1jEhMB78j3FOZ1h0SjMxDUJbDslwy+yyl/XCgPpbjHiKqi6MwRoqRB95wVj7lb6K8kFUal7Jhrgo3VCTKtLNFprc5WrW+c0lXeO9YpbH27pdPsg1a1CkVaEmRhcwUBqZOMejmgQb2SNLxaLnG3Jc6yCltEow78Xgss/4Qv9deaADFUK5onCprLQoVyvjF9Mpq213HJn2yyxzb2jcqX8YXJ5+0yamn44+ccURdqxQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 998bf474-30ec-4e8f-eafa-08d86b06905f X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Oct 2020 21:18:40.7836 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WodwhriodKW3RGyVfO1SrQNB+yrHyEfPl2suO7aJe3r8p4clX8D4K7Yow7Zuxni09Fi0QwxLkQx+fLizFDheag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2575 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 16/22] event/dlb2: add dequeue and its burst variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Friday, September 11, 2020 3:26 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH 16/22] event/dlb2: add dequeue and its burst variants >=20 > Add support for dequeue, dequeue_burst, ... Please elaborate -- this commit message doesn't mention (e.g.) the use of umonitor/umwait or the "sparse" dequeue function variants. I think the average reviewer needs some more context in order to understand this change= . [...] > + > +static inline int > +dlb2_process_dequeue_qes(struct dlb2_eventdev_port *ev_port, > + struct dlb2_port *qm_port, > + struct rte_event *events, > + struct dlb2_dequeue_qe *qes, > + int cnt) > +{ > + uint8_t *qid_mappings =3D qm_port->qid_mappings; > + int i, num, evq_id; > + > + RTE_SET_USED(ev_port); /* avoids unused variable error if stats off */ Looks like ev_port is used unconditionally later on: "evq_id =3D ev_port->l= ink[0].queue_id;" > + > + for (i =3D 0, num =3D 0; i < cnt; i++) { > + struct dlb2_dequeue_qe *qe =3D &qes[i]; > + int sched_type_map[DLB2_NUM_HW_SCHED_TYPES] =3D { > + [DLB2_SCHED_ATOMIC] =3D RTE_SCHED_TYPE_ATOMIC, > + [DLB2_SCHED_UNORDERED] =3D > RTE_SCHED_TYPE_PARALLEL, > + [DLB2_SCHED_ORDERED] =3D RTE_SCHED_TYPE_ORDERED, > + [DLB2_SCHED_DIRECTED] =3D RTE_SCHED_TYPE_ATOMIC, > + }; > + > + /* Fill in event information. > + * Note that flow_id must be embedded in the data by > + * the app, such as the mbuf RSS hash field if the data > + * buffer is a mbuf. > + */ > + if (unlikely(qe->error)) { > + DLB2_LOG_ERR("QE error bit ON\n"); > + DLB2_INC_STAT(ev_port->stats.traffic.rx_drop, 1); > + dlb2_consume_qe_immediate(qm_port, 1); > + continue; /* Ignore */ > + } > + > + events[num].u64 =3D qe->data; > + events[num].flow_id =3D qe->flow_id; > + events[num].priority =3D DLB2_TO_EV_PRIO((uint8_t)qe->priority); > + events[num].event_type =3D qe->u.event_type.major; > + events[num].sub_event_type =3D qe->u.event_type.sub; > + events[num].sched_type =3D sched_type_map[qe->sched_type]; > + events[num].impl_opaque =3D qe->qid_depth; > + > + /* qid not preserved for directed queues */ > + if (qm_port->is_directed) > + evq_id =3D ev_port->link[0].queue_id; > + else > + evq_id =3D qid_mappings[qe->qid]; > + > + events[num].queue_id =3D evq_id; > + DLB2_INC_STAT( > + ev_port->stats.queue[evq_id].qid_depth[qe- > >qid_depth], > + 1); > + DLB2_INC_STAT(ev_port->stats.rx_sched_cnt[qe->sched_type], > 1); > + DLB2_INC_STAT(ev_port->stats.traffic.rx_ok, 1); Move this outside the loop and increment by 'num' rather than '1'? > + num++; > + } > + > + return num; > +} > + > +static inline int > +dlb2_process_dequeue_four_qes(struct dlb2_eventdev_port *ev_port, > + struct dlb2_port *qm_port, > + struct rte_event *events, > + struct dlb2_dequeue_qe *qes) > +{ > + int sched_type_map[] =3D { > + [DLB2_SCHED_ATOMIC] =3D RTE_SCHED_TYPE_ATOMIC, > + [DLB2_SCHED_UNORDERED] =3D RTE_SCHED_TYPE_PARALLEL, > + [DLB2_SCHED_ORDERED] =3D RTE_SCHED_TYPE_ORDERED, > + [DLB2_SCHED_DIRECTED] =3D RTE_SCHED_TYPE_ATOMIC, > + }; > + const int num_events =3D DLB2_NUM_QES_PER_CACHE_LINE; > + uint8_t *qid_mappings =3D qm_port->qid_mappings; > + __m128i sse_evt[2]; > + > + RTE_SET_USED(ev_port); /* avoids unused variable error, if stats off *= / ev_port gets passed to dlb2_process_dequeue_qes, I don't think this line is= necessary. > + > + /* In the unlikely case that any of the QE error bits are set, process > + * them one at a time. > + */ > + if (unlikely(qes[0].error || qes[1].error || > + qes[2].error || qes[3].error)) > + return dlb2_process_dequeue_qes(ev_port, qm_port, events, > + qes, num_events); Thanks, Gage