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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: P4U9D4ukSR4x/r2/BJ/njNRSUcPr2LtmO9OPS2TMvveo+Df6ongJp6dHpgEmmkNSYJE7jHZHgRDpR4H/2IK2VT+hiUIJgqCdlUef5zeVhrlqjk56WLXSfzeTF5cYUkWb1xmVW3jU6RpEOJs4BrGdeqqC2bURISPgya6DacOtuVB0bO/s5to1y/564T/MXkWuhEL1tc7/O+HMoHx5IdYDR2o7PoTql22zoiSGrbXt6xs4rH9wCdweuTryUtTOrhF0Ii15cHoerS2WcROVp0HH6guDc3zjb3zaB4Nh/xDcA0P7cVh6HT7AAmnHtDEsqD5w043S+q0a/ddGGt/otPXeMDiWeTrszUK2g+MyifE1YZ1nc+ZdQOZVPjJv8WcGJ5yZCzSagNXiHgNAwUYMw85Yz5IBLgpaLXaX4Ig5H05LWfVkoXe7l0+qVox+ZWKUZmKQ8ZmZ1nniRuidczfM9/LjDK6jA/PdQDRhm6Mlzwx97Z1i0l3FHw+5toDQ+91Y38S8xVfje4oPHOJOeIT2xm2yVYeW6WLnQNjzv0PnfffBqSsxHP0OxmrJUibl0eDGjYPiCSj7S2f8tL8TYsIDnqiztPEfjdWTGi6Ya7SJWAjsLi2gop38xc3PrxJzN3ZmxQE1rw8soinBlTsb4R/b/JOW8Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f5a27f61-8965-4b03-fed9-08d86bd1241b X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 21:28:46.9627 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XDPY/HJrBSxmYC46p7J7hUPQqa378P3TT19KSgFb3qq2+UtWWmiuXKQy3ciMXcDOzy7AJxXB8ruYvLP1K4fQww== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2782 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v4 11/22] event/dlb: add port setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Friday, September 11, 2020 2:18 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH v4 11/22] event/dlb: add port setup >=20 > Configure the load balanded (ldb) or directed (dir) port. > The consumer queue (CQ) and producer port (PP) are also > set up here. >=20 > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb/dlb.c | 539 +++++++++++ > drivers/event/dlb/dlb_iface.c | 11 + > drivers/event/dlb/dlb_iface.h | 14 + > drivers/event/dlb/pf/base/dlb_resource.c | 1430 > ++++++++++++++++++++++++++++++ > drivers/event/dlb/pf/dlb_pf.c | 204 +++++ > 5 files changed, 2198 insertions(+) >=20 > diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c > index 0b474a5..e90a088 100644 > --- a/drivers/event/dlb/dlb.c > +++ b/drivers/event/dlb/dlb.c > @@ -157,6 +157,75 @@ dlb_free_qe_mem(struct dlb_port *qm_port) > } > } >=20 > +static int > +dlb_init_consume_qe(struct dlb_port *qm_port, char *mz_name) > +{ > + struct dlb_cq_pop_qe *qe; > + > + qe =3D rte_malloc(mz_name, > + DLB_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb_cq_pop_qe), > + RTE_CACHE_LINE_SIZE); > + > + if (qe =3D=3D NULL) { > + DLB_LOG_ERR("dlb: no memory for consume_qe\n"); > + return -ENOMEM; > + } > + > + qm_port->consume_qe =3D qe; > + > + memset(qe, 0, DLB_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb_cq_pop_qe)); This is a good candidate for rte_zmalloc(). > + > + qe->qe_valid =3D 0; > + qe->qe_frag =3D 0; > + qe->qe_comp =3D 0; > + qe->cq_token =3D 1; > + /* Tokens value is 0-based; i.e. '0' returns 1 token, '1' returns 2, > + * and so on. > + */ > + qe->tokens =3D 0; /* set at run time */ > + qe->meas_lat =3D 0; > + qe->no_dec =3D 0; > + /* Completion IDs are disabled */ > + qe->cmp_id =3D 0; > + > + return 0; > +} > + > +int > +dlb_init_qe_mem(struct dlb_port *qm_port, char *mz_name) > +{ > + int ret, sz; > + > + sz =3D DLB_NUM_QES_PER_CACHE_LINE * sizeof(struct dlb_enqueue_qe); > + > + qm_port->qe4 =3D rte_malloc(mz_name, sz, RTE_CACHE_LINE_SIZE); > + > + if (qm_port->qe4 =3D=3D NULL) { > + DLB_LOG_ERR("dlb: no qe4 memory\n"); > + ret =3D -ENOMEM; > + goto error_exit; > + } > + > + memset(qm_port->qe4, 0, sz); > + > + ret =3D dlb_init_consume_qe(qm_port, mz_name); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: dlb_init_consume_qe ret=3D%d\n", > + ret); This can fit on one line > + goto error_exit; > + } > + > + return 0; > + > +error_exit: > + > + dlb_free_qe_mem(qm_port); > + > + return ret; > +} > + > /* Wrapper for string to int conversion. Substituted for atoi(...), whic= h is > * unsafe. > */ > @@ -662,6 +731,348 @@ dlb_eventdev_queue_default_conf_get(struct > rte_eventdev *dev, > queue_conf->priority =3D 0; > } >=20 > +static int > +dlb_hw_create_ldb_port(struct dlb_eventdev *dlb, > + struct dlb_eventdev_port *ev_port, > + uint32_t dequeue_depth, > + uint32_t cq_depth, > + uint32_t enqueue_depth, > + uint16_t rsvd_tokens, > + bool use_rsvd_token_scheme) > +{ > + struct dlb_hw_dev *handle =3D &dlb->qm_instance; > + struct dlb_create_ldb_port_args cfg =3D {0}; > + struct dlb_cmd_response response =3D {0}; > + int ret; > + struct dlb_port *qm_port =3D NULL; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t qm_port_id; > + > + if (handle =3D=3D NULL) > + return -EINVAL; > + > + if (cq_depth < DLB_MIN_LDB_CQ_DEPTH || > + cq_depth > DLB_MAX_INPUT_QUEUE_DEPTH) { > + DLB_LOG_ERR("dlb: invalid cq_depth, must be %d-%d\n", > + DLB_MIN_LDB_CQ_DEPTH, > DLB_MAX_INPUT_QUEUE_DEPTH); > + return -EINVAL; > + } > + > + if (enqueue_depth < DLB_MIN_ENQUEUE_DEPTH) { > + DLB_LOG_ERR("dlb: invalid enqueue_depth, must be at least > %d\n", > + DLB_MIN_ENQUEUE_DEPTH); > + return -EINVAL; > + } Like my comment in the dlb2 "add port setup" patch, looks like the cq depth upper bound check can be dropped, since it's already done in dlb_eventdev_port_setup(). > + > + rte_spinlock_lock(&handle->resource_lock); > + > + cfg.response =3D (uintptr_t)&response; > + > + /* We round up to the next power of 2 if necessary */ > + cfg.cq_depth =3D rte_align32pow2(cq_depth); > + cfg.cq_depth_threshold =3D rsvd_tokens; > + > + cfg.cq_history_list_size =3D > DLB_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; > + > + /* User controls the LDB high watermark via enqueue depth. The DIR > high > + * watermark is equal, unless the directed credit pool is too small. > + */ > + cfg.ldb_credit_high_watermark =3D enqueue_depth; > + > + /* If there are no directed ports, the kernel driver will ignore this > + * port's directed credit settings. Don't use enqueue_depth if it would > + * require more directed credits than are available. > + */ > + cfg.dir_credit_high_watermark =3D > + RTE_MIN(enqueue_depth, > + handle->cfg.num_dir_credits / dlb->num_ports); > + > + cfg.ldb_credit_quantum =3D cfg.ldb_credit_high_watermark / 2; > + cfg.ldb_credit_low_watermark =3D RTE_MIN(16, cfg.ldb_credit_quantum); > + > + cfg.dir_credit_quantum =3D cfg.dir_credit_high_watermark / 2; > + cfg.dir_credit_low_watermark =3D RTE_MIN(16, cfg.dir_credit_quantum); > + > + /* Per QM values */ > + > + cfg.ldb_credit_pool_id =3D handle->cfg.ldb_credit_pool_id; > + cfg.dir_credit_pool_id =3D handle->cfg.dir_credit_pool_id; > + > + ret =3D dlb_iface_ldb_port_create(handle, &cfg, dlb->poll_mode); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: dlb_ldb_port_create error, ret=3D%d (driver > status: %s)\n", > + ret, dlb_error_strings[response.status]); > + goto error_exit; > + } > + > + qm_port_id =3D response.id; > + > + DLB_LOG_DBG("dlb: ev_port %d uses qm LB port %d <<<<<\n", > + ev_port->id, qm_port_id); > + > + qm_port =3D &ev_port->qm_port; > + qm_port->ev_port =3D ev_port; /* back ptr */ > + qm_port->dlb =3D dlb; /* back ptr */ > + > + /* > + * Allocate and init local qe struct(s). > + * Note: MOVDIR64 requires the enqueue QE (qe4) to be aligned. > + */ > + > + snprintf(mz_name, sizeof(mz_name), "%s_ldb_port%d", > + handle->device_name, > + ev_port->id); I don't believe device_name is initialized. > + > + ret =3D dlb_init_qe_mem(qm_port, mz_name); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: init_qe_mem failed, ret=3D%d\n", ret); > + goto error_exit; > + } > + > + qm_port->pp_mmio_base =3D DLB_LDB_PP_BASE + PAGE_SIZE * > qm_port_id; > + qm_port->id =3D qm_port_id; > + > + /* The credit window is one high water mark of QEs */ > + qm_port->ldb_pushcount_at_credit_expiry =3D 0; > + qm_port->cached_ldb_credits =3D cfg.ldb_credit_high_watermark; > + /* The credit window is one high water mark of QEs */ > + qm_port->dir_pushcount_at_credit_expiry =3D 0; > + qm_port->cached_dir_credits =3D cfg.dir_credit_high_watermark; > + qm_port->cq_depth =3D cfg.cq_depth; > + /* CQs with depth < 8 use an 8-entry queue, but withhold credits so > + * the effective depth is smaller. > + */ > + qm_port->cq_depth =3D cfg.cq_depth <=3D 8 ? 8 : cfg.cq_depth; > + qm_port->cq_idx =3D 0; > + qm_port->cq_idx_unmasked =3D 0; > + if (dlb->poll_mode =3D=3D DLB_CQ_POLL_MODE_SPARSE) > + qm_port->cq_depth_mask =3D (qm_port->cq_depth * 4) - 1; > + else > + qm_port->cq_depth_mask =3D qm_port->cq_depth - 1; > + > + qm_port->gen_bit_shift =3D __builtin_popcount(qm_port- > >cq_depth_mask); > + /* starting value of gen bit - it toggles at wrap time */ > + qm_port->gen_bit =3D 1; > + > + qm_port->use_rsvd_token_scheme =3D use_rsvd_token_scheme; > + qm_port->cq_rsvd_token_deficit =3D rsvd_tokens; > + qm_port->int_armed =3D false; > + > + /* Save off for later use in info and lookup APIs. */ > + qm_port->qid_mappings =3D &dlb->qm_ldb_to_ev_queue_id[0]; > + > + /* When using the reserved token scheme, token_pop_thresh is > + * initially 2 * dequeue_depth. Once the tokens are reserved, > + * the enqueue code re-assigns it to dequeue_depth. > + */ > + qm_port->dequeue_depth =3D dequeue_depth; > + qm_port->token_pop_thresh =3D cq_depth; > + > + /* When the deferred scheduling vdev arg is selected, use deferred pop > + * for all single-entry CQs. > + */ > + if (cfg.cq_depth =3D=3D 1 || (cfg.cq_depth =3D=3D 2 && > use_rsvd_token_scheme)) { > + if (dlb->defer_sched) > + qm_port->token_pop_mode =3D DEFERRED_POP; > + } > + > + qm_port->owed_tokens =3D 0; > + qm_port->issued_releases =3D 0; > + > + /* Save config message too. */ > + rte_memcpy(&qm_port->cfg.ldb, &cfg, sizeof(cfg)); Safer to do sizeof() on the destination than the source, I think. > + > + /* update state */ > + qm_port->state =3D PORT_STARTED; /* enabled at create time */ > + qm_port->config_state =3D DLB_CONFIGURED; > + > + qm_port->dir_credits =3D cfg.dir_credit_high_watermark; > + qm_port->ldb_credits =3D cfg.ldb_credit_high_watermark; > + > + DLB_LOG_DBG("dlb: created ldb port %d, depth =3D %d, ldb credits=3D%d, = dir > credits=3D%d\n", > + qm_port_id, > + cq_depth, > + qm_port->ldb_credits, > + qm_port->dir_credits); > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + return 0; > + > +error_exit: > + if (qm_port) { > + dlb_free_qe_mem(qm_port); > + qm_port->pp_mmio_base =3D 0; > + } > + > + rte_spinlock_unlock(&handle->resource_lock); > + > + DLB_LOG_ERR("dlb: create ldb port failed!\n"); > + > + return ret; > +} > + > +static int > +dlb_hw_create_dir_port(struct dlb_eventdev *dlb, > + struct dlb_eventdev_port *ev_port, > + uint32_t dequeue_depth, > + uint32_t cq_depth, > + uint32_t enqueue_depth, > + uint16_t rsvd_tokens, > + bool use_rsvd_token_scheme) > +{ > + struct dlb_hw_dev *handle =3D &dlb->qm_instance; > + struct dlb_create_dir_port_args cfg =3D {0}; > + struct dlb_cmd_response response =3D {0}; > + int ret; > + struct dlb_port *qm_port =3D NULL; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t qm_port_id; > + > + if (dlb =3D=3D NULL || handle =3D=3D NULL) > + return -EINVAL; > + > + if (cq_depth < DLB_MIN_DIR_CQ_DEPTH || > + cq_depth > DLB_MAX_INPUT_QUEUE_DEPTH) { > + DLB_LOG_ERR("dlb: invalid cq_depth, must be %d-%d\n", > + DLB_MIN_DIR_CQ_DEPTH, > DLB_MAX_INPUT_QUEUE_DEPTH); > + return -EINVAL; > + } Enqueue depth check needed? > + > + rte_spinlock_lock(&handle->resource_lock); > + > + /* Directed queues are configured at link time. */ > + cfg.queue_id =3D -1; > + > + cfg.response =3D (uintptr_t)&response; > + > + /* We round up to the next power of 2 if necessary */ > + cfg.cq_depth =3D rte_align32pow2(cq_depth); > + cfg.cq_depth_threshold =3D rsvd_tokens; > + > + /* User controls the LDB high watermark via enqueue depth. The DIR > high > + * watermark is equal, unless the directed credit pool is too small. > + */ > + cfg.ldb_credit_high_watermark =3D enqueue_depth; > + > + /* Don't use enqueue_depth if it would require more directed credits > + * than are available. > + */ > + cfg.dir_credit_high_watermark =3D > + RTE_MIN(enqueue_depth, > + handle->cfg.num_dir_credits / dlb->num_ports); > + > + cfg.ldb_credit_quantum =3D cfg.ldb_credit_high_watermark / 2; > + cfg.ldb_credit_low_watermark =3D RTE_MIN(16, cfg.ldb_credit_quantum); > + > + cfg.dir_credit_quantum =3D cfg.dir_credit_high_watermark / 2; > + cfg.dir_credit_low_watermark =3D RTE_MIN(16, cfg.dir_credit_quantum); > + > + /* Per QM values */ > + > + cfg.ldb_credit_pool_id =3D handle->cfg.ldb_credit_pool_id; > + cfg.dir_credit_pool_id =3D handle->cfg.dir_credit_pool_id; > + > + ret =3D dlb_iface_dir_port_create(handle, &cfg, dlb->poll_mode); > + if (ret < 0) { > + DLB_LOG_ERR("dlb: dlb_dir_port_create error, ret=3D%d (driver > status: %s)\n", > + ret, dlb_error_strings[response.status]); > + goto error_exit; > + } > + > + qm_port_id =3D response.id; > + > + DLB_LOG_DBG("dlb: ev_port %d uses qm DIR port %d <<<<<\n", > + ev_port->id, qm_port_id); > + > + qm_port =3D &ev_port->qm_port; > + qm_port->ev_port =3D ev_port; /* back ptr */ > + qm_port->dlb =3D dlb; /* back ptr */ > + > + /* > + * Init local qe struct(s). > + * Note: MOVDIR64 requires the enqueue QE to be aligned > + */ > + > + snprintf(mz_name, sizeof(mz_name), "%s_dir_port%d", > + handle->device_name, > + ev_port->id); (See device_name comment above) > + > + ret =3D dlb_init_qe_mem(qm_port, mz_name); > + > + if (ret < 0) { > + DLB_LOG_ERR("dlb: init_qe_mem failed, ret=3D%d\n", ret); > + goto error_exit; > + } > + > + qm_port->pp_mmio_base =3D DLB_DIR_PP_BASE + PAGE_SIZE * > qm_port_id; > + qm_port->id =3D qm_port_id; > + > + /* The credit window is one high water mark of QEs */ > + qm_port->ldb_pushcount_at_credit_expiry =3D 0; > + qm_port->cached_ldb_credits =3D cfg.ldb_credit_high_watermark; > + /* The credit window is one high water mark of QEs */ > + qm_port->dir_pushcount_at_credit_expiry =3D 0; > + qm_port->cached_dir_credits =3D cfg.dir_credit_high_watermark; > + qm_port->cq_depth =3D cfg.cq_depth; > + qm_port->cq_idx =3D 0; > + qm_port->cq_idx_unmasked =3D 0; > + if (dlb->poll_mode =3D=3D DLB_CQ_POLL_MODE_SPARSE) > + qm_port->cq_depth_mask =3D (cfg.cq_depth * 4) - 1; > + else > + qm_port->cq_depth_mask =3D cfg.cq_depth - 1; > + > + qm_port->gen_bit_shift =3D __builtin_popcount(qm_port- > >cq_depth_mask); > + /* starting value of gen bit - it toggles at wrap time */ > + qm_port->gen_bit =3D 1; > + > + qm_port->use_rsvd_token_scheme =3D use_rsvd_token_scheme; > + qm_port->cq_rsvd_token_deficit =3D rsvd_tokens; > + qm_port->int_armed =3D false; > + > + /* Save off for later use in info and lookup APIs. */ > + qm_port->qid_mappings =3D &dlb->qm_dir_to_ev_queue_id[0]; > + > + qm_port->dequeue_depth =3D dequeue_depth; > + > + /* Directed ports are auto-pop, by default. */ > + qm_port->token_pop_mode =3D AUTO_POP; > + qm_port->owed_tokens =3D 0; > + qm_port->issued_releases =3D 0; > + > + /* Save config message too. */ > + rte_memcpy(&qm_port->cfg.dir, &cfg, sizeof(cfg)); (See sizeof() comment above) [...] > diff --git a/drivers/event/dlb/pf/dlb_pf.c b/drivers/event/dlb/pf/dlb_pf.= c > index fffb88b..cd766d3 100644 > --- a/drivers/event/dlb/pf/dlb_pf.c > +++ b/drivers/event/dlb/pf/dlb_pf.c > @@ -221,6 +221,207 @@ dlb_pf_ldb_queue_create(struct dlb_hw_dev *handle, > } >=20 > static int > +dlb_pf_dir_queue_create(struct dlb_hw_dev *handle, > + struct dlb_create_dir_queue_args *cfg) > +{ > + struct dlb_dev *dlb_dev =3D (struct dlb_dev *)handle->pf_dev; > + struct dlb_cmd_response response =3D {0}; > + int ret; > + > + DLB_INFO(dev->dlb_device, "Entering %s()\n", __func__); > + > + ret =3D dlb_hw_create_dir_queue(&dlb_dev->hw, > + handle->domain_id, > + cfg, > + &response); > + > + *(struct dlb_cmd_response *)cfg->response =3D response; > + > + DLB_INFO(dev->dlb_device, "Exiting %s() with ret=3D%d\n", __func__, > ret); > + > + return ret; > +} > + > +static void * > +dlb_alloc_coherent_aligned(rte_iova_t *phys, size_t size, int align) > +{ > + const struct rte_memzone *mz; > + char mz_name[RTE_MEMZONE_NAMESIZE]; > + uint32_t core_id =3D rte_lcore_id(); > + unsigned int socket_id; > + > + snprintf(mz_name, sizeof(mz_name) - 1, "%lx", > + (unsigned long)rte_get_timer_cycles()); For debug purposes, it would be better if this name can trace the mz back t= o this driver. How about something like event_dlb2_pf_name + ldb/dir_port + p= ort ID? I also don't see the port memzones getting freed anywhere, e.g. if the even= t device is reset. Looks like a possible memory leak. Thanks, Gage