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Mon, 5 Oct 2020 13:20:11 +0000 From: "De Lara Guarch, Pablo" To: "O'loingsigh, Mairtin" , "Singh, Jasvinder" , "Richardson, Bruce" CC: "dev@dpdk.org" , "Ryan, Brendan" , "Coyle, David" Thread-Topic: [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ based CRC Thread-Index: AQHWlnZX3D7fks+FTkqLD3p2ZSzORqmJBMIQ Date: Mon, 5 Oct 2020 13:20:11 +0000 Message-ID: References: <1601393761-11588-1-git-send-email-mairtin.oloingsigh@intel.com> <1601393761-11588-3-git-send-email-mairtin.oloingsigh@intel.com> In-Reply-To: <1601393761-11588-3-git-send-email-mairtin.oloingsigh@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.255.188.24] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 112b51aa-cd13-4a3c-d662-08d869316359 x-ms-traffictypediagnostic: SN6PR11MB2640: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4303; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB3101.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 112b51aa-cd13-4a3c-d662-08d869316359 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Oct 2020 13:20:11.2452 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TvW+X79Zmq1tS4qPjdYZDIwJ5L8mLASWx7g+2y3uqKga0mpXPL2A9CViZKZmVmLQBKDFIIinEdUHhIy1BTAVtxAksa3lp8HpKIWnDorQNww= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2640 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ based CRC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Mairtin, > -----Original Message----- > From: O'loingsigh, Mairtin > Sent: Tuesday, September 29, 2020 4:36 PM > To: Singh, Jasvinder ; Richardson, Bruce > ; De Lara Guarch, Pablo > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, David > ; O'loingsigh, Mairtin > Subject: [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ based CRC >=20 > This patch enables the optimized calculation of CRC32-Ethernet and CRC16- > CCITT using the AVX512 and VPCLMULQDQ instruction sets. This CRC > implementation is built if the compiler supports the required instruction= sets. It is > selected at run-time if the host CPU, again, supports the required instru= ction > sets. >=20 > Signed-off-by: Mairtin o Loingsigh > Signed-off-by: David Coyle ... > +static __rte_always_inline uint32_t > +crc32_eth_calc_vpclmulqdq(const uint8_t *data, uint32_t data_len, uint32= _t > crc, > + const struct crc_vpclmulqdq_ctx *params) { > + __m128i res, d; > + __m256i b; > + __m512i temp, k; > + __m512i qw0 =3D _mm512_set1_epi64(0), qw1, qw2, qw3; > + __m512i fold0, fold1, fold2, fold3; > + __mmask16 mask; > + uint32_t n =3D 0; > + int reduction =3D 0; > + > + /* Get CRC init value */ > + b =3D _mm256_insert_epi32(_mm256_setzero_si256(), crc, 0); > + temp =3D _mm512_inserti32x8(_mm512_setzero_si512(), b, 0); You can replace this with the following, which produces less instructions (b needs to be changed to __m128i): b =3D _mm_cvtsi32_si128(crc); temp =3D _mm512_castsi128_si512(b); > + > + if (data_len > 255) { > + fold0 =3D _mm512_loadu_si512((const __m512i *)data); ... > + } else { > + if (data_len > 31) { > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, 0); Should work better with: res =3D _mm_cvtsi32_si128(crc); > + d =3D _mm_loadu_si128((const __m128i *)data); > + res =3D _mm_xor_si128(res, d); > + n +=3D 16; > + > + reduction =3D 240 - ((n+256)-data_len); > + > + while (reduction > 0) > + reduction_loop(&res, &reduction, data, &n, > + params); > + > + if (n !=3D data_len) > + res =3D last_two_xmm(data, data_len, n, res, > + params); > + } else if (data_len > 16) { > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, 0); Same as above. > + d =3D _mm_loadu_si128((const __m128i *)data); > + res =3D _mm_xor_si128(res, d); > + n +=3D 16; > + > + if (n !=3D data_len) > + res =3D last_two_xmm(data, data_len, n, res, > + params); > + } else if (data_len =3D=3D 16) { > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, 0); Same. > + d =3D _mm_loadu_si128((const __m128i *)data); > + res =3D _mm_xor_si128(res, d); > + } else { > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, 0); Same. > + mask =3D byte_len_to_mask_table[data_len]; > + d =3D _mm_maskz_loadu_epi8(mask, data);