From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7BAE5A034F; Wed, 31 Mar 2021 08:55:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66268140DE4; Wed, 31 Mar 2021 08:55:21 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id C163E140DEA for ; Wed, 31 Mar 2021 08:55:19 +0200 (CEST) IronPort-SDR: NzDX2qX9RHaV3xzNe037jEnL5NiP4KPk+qI1c/C3f0+IhGs99TWdRFr9BmpinFH6/sFvEFrm+p RZMLOLNmqYMg== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="188672184" X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="188672184" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 23:55:18 -0700 IronPort-SDR: +daWDbLa7RCxEH3E5lNgSadeP3tdpgNrEkwW8qil4Iohhxgk12trdWqniiS7sws99M2w6ptfQ6 2siEDGgcsvog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="595796133" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga005.jf.intel.com with ESMTP; 30 Mar 2021 23:55:18 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 30 Mar 2021 23:55:17 -0700 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 30 Mar 2021 23:55:17 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2 via Frontend Transport; Tue, 30 Mar 2021 23:55:17 -0700 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (104.47.58.103) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2106.2; Tue, 30 Mar 2021 23:55:17 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RtQWIEPsxkMEBm0SUDu77pxDrHWMaiBm/xk7nnP2BmMj0Stqpcgga7qQ78L8RgLmSkuUUwvNQK2lzGZZC3x939zU3lifYB3JV90zKdZ/hVaghGoSBFKa4ezYPyvM3bd0ZDUtR3M+halhrpfZKPvsGr7eKIb6tiiIBEsxzotFuuV08YCHTvZXVEULgG77Y0/ws/OvXTBn38gCBxCU1ZjCNw0UEdNKBi4PV9ybMqPX7O4HKQbeb5C9n7adMSSUhLMJ0Z5hn8Qb6itEcmwxvp84/5WLHIupp1j5WV/ysQwNxICPYwv7dbD5fsxaQWP0GvMMgVz7AaSBTmpRUTmRaRux+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MEJRNWxZxTqBlTiZvs9vGuwN5GtzfQoYuj0OYg/m7iA=; b=XKiM+B0m+OPU8NyCOgWd9WAGfKkQB0YOmt1JqcwEkyDQPZqtz8nZXUNHWxWwDhwROCW/UBD+r1Tx2jxlBPVEKnGIgZ4FdaaCe018BKaX3P12D/s5vGGHf6OXZi/j1Y0jkaNoGx2UmjGzHOFvRj9mem776bpawYPq8nZTy199rnt1wYHSd2dJwH1t83XJ0yKKEThQ8vpr1sAXTqHu61wlgpxywSsbDOJ7YIHQHx9Qo9jzOFjj9KaLRERJXreFQ83JNNnG52NCtA0LU5F1oHXcd6+RAWGbRi2cifnZttz+0tXLz1zPGKal+XHMFOy2N2n5bovvlVFXpoccIqMeOIeURw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MEJRNWxZxTqBlTiZvs9vGuwN5GtzfQoYuj0OYg/m7iA=; b=ChNhug3B3r7JnKAvtIDLstox//rX3ClciVDRsVT1whnlFPz4i/BjyVDTfa/A8oR/dcRyQwjxueI7hVtHPmfyMWne0Oec3OeAZ5XboM80qTn/xlwUGt7OHIS+ZOmFlb1nY4HcUqS5Al2v/e0cvYDfKqK91c7y8MTfCA1aOb6KplM= Received: from SN6PR11MB3117.namprd11.prod.outlook.com (2603:10b6:805:d7::32) by SA0PR11MB4640.namprd11.prod.outlook.com (2603:10b6:806:9b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3999.27; Wed, 31 Mar 2021 06:55:15 +0000 Received: from SN6PR11MB3117.namprd11.prod.outlook.com ([fe80::4579:2bc0:3dc8:8b37]) by SN6PR11MB3117.namprd11.prod.outlook.com ([fe80::4579:2bc0:3dc8:8b37%5]) with mapi id 15.20.3977.033; Wed, 31 Mar 2021 06:55:15 +0000 From: "Jayatheerthan, Jay" To: "pbhagavatula@marvell.com" , "jerinj@marvell.com" , "Carrillo, Erik G" , "Gujjar, Abhinandan S" , "McDaniel, Timothy" , "hemant.agrawal@nxp.com" , "Van Haaren, Harry" , mattias.ronnblom , "Ma, Liang J" , Ray Kinsella , Neil Horman CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev v21.11] [PATCH v9 8/8] eventdev: simplify Rx adapter event vector config Thread-Index: AQHXJT32HsTkUQJIRk+U+x++wARlZqqdqnAA Date: Wed, 31 Mar 2021 06:55:14 +0000 Message-ID: References: <20210326140850.7332-1-pbhagavatula@marvell.com> <20210330082212.707-1-pbhagavatula@marvell.com> <20210330082212.707-9-pbhagavatula@marvell.com> In-Reply-To: <20210330082212.707-9-pbhagavatula@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [223.226.90.31] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9340b843-2541-4b2d-6d5a-08d8f411eff4 x-ms-traffictypediagnostic: SA0PR11MB4640: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4303; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: VFmE+A9nd2IwOLhFV7eB1OJy8fBa/L2s0kOikUUSPoe6ryeS3gh53GobvHscQXnYuYj/QyUPco02Z2Q87hIQuHZiGdP6krQpAoOvrQbNErteosVmrEi61uXIO9FUZq+FfBs0ZoS9kE8eDf19vJLavvEKe1SdvYW9D1fumKaCHPBdyP6TvW0AcVG/oZ0ncZA9GrCg4FKIUlBEF5KVM9Y9mfndTWyvCABM6Z2M5Y21u5VS4dDu4AT9vOwzjiKi1b+bigNO3Au9prHo+x6APR3w5CzWqTSvpdmrvWCdifFoB/YmC8Rq5Vkjj+2JDlHthBVWdaWQgGV9E6IAJX90Tr4MU7PQhXWGNZfTTlcPl+1oAFonHahiI8SzmqtIHb7eS1n7rD4bDocfMcRqsKSz2pDGW+Vg4klcYzthDiijPbrbzvAniHRrDjwpByeCmZKmgfCUayIJf23YY+/5sAgt2dp1XC7EwyJYBANWIbmojZ3t3Fj+8lpQvb6iAGHoN8M/Fh59YIXpxU4vzNkLutwD/r3i3r5otMyKOmJr/5ayhnkpnrfADLx8Kmxzu1Qyv1IiaJvvQkvDcG3YqgAJQyonkPF2KRX+S8risQyRVD9jiqmXFYHyk/BwxG5qGAF/iGgSNl4sRdi+qUVc9gW1CfTtf9/9vOrJ7sNf0qLM6CAgHAxrbaCaLepdpdps3XVmdS1ZHumQ x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR11MB3117.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(396003)(346002)(376002)(136003)(366004)(39860400002)(6506007)(53546011)(55016002)(33656002)(38100700001)(55236004)(5660300002)(9686003)(71200400001)(83380400001)(921005)(8936002)(478600001)(186003)(4326008)(8676002)(86362001)(316002)(110136005)(7696005)(76116006)(30864003)(2906002)(52536014)(66476007)(66946007)(64756008)(26005)(66556008)(66446008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: =?us-ascii?Q?NgMQW6rqGTnIdSQNncR6t6zi9tAyONJY3i0jNB9uzbQQBLk4XUpIJZ2PEIIm?= =?us-ascii?Q?p125C+HXEmK0pDZggivsn8BiYTu6CIDqRRGVa+Si8UUjitT1JLL+XKNMxuM4?= =?us-ascii?Q?xi0bTaF0M1ZOPmBJvtpyADWd4+T1wbcjvkRpJEqAzoseZXMJeCjtvuFiOs4S?= =?us-ascii?Q?iCd8MwQjocLxUVl7Fwpe8asuOx4WFvYMtWz6MlfxrCdPwPfjRlAzonfimBE5?= =?us-ascii?Q?zudNWgVKGYlDlHu9m5uZjeGlnINZgp/oPfqUdZQFQYcMV5Y0/oBC0zI4d1my?= =?us-ascii?Q?1BiNZ+YT9WB1L5lIQuuhDXvMLqOtuDWAoaqaBbTaKM3dVQAoD2OzqEadsTY4?= =?us-ascii?Q?A9iDJq1miKR7nOIrWFpUXDVOeYrYnSH2ZLR/le5+zzSF1w/Y7aENYOmOSCau?= =?us-ascii?Q?SGUpMvnB/Pa608DwSvBwMHvH2cqoi1Xkbnf9DePMGK8w+juVfN+JXmkLn+YZ?= =?us-ascii?Q?oafdhGxHl7YigAiz9ZQD3vnLQ6zQir3JF9zsPnCUaYSWMi68UdniZF4ipuSI?= =?us-ascii?Q?zaNqkdrz7lfGaFPgnNtYcyKK4/C9kz2DWSu08/p9yWcHZh7CuC5X8VLYP8+6?= =?us-ascii?Q?KRNQ1PiNo0Pf1vDapaPrYrAne89V9KW1kPppRBSIR5uChgqurvyspcMNFcCX?= =?us-ascii?Q?hRb7jt71eG6cDnPjDGgeFJMbNzIgKH0V0ZVYi9iaqg17K4+ZbzTdk2JoYnTR?= =?us-ascii?Q?/1I5P73g5Hqc6uOXuercuwdPKtU9zOj/FDmdOp1AOqaT9NwpwWZfIpCxTfW2?= =?us-ascii?Q?9GfLYn6qxNE5GVZu63eYfrVrkZCLMLler9Ze4GcMPHr5YPIOuxSiiAdV6ITG?= =?us-ascii?Q?vVjRa0pRPCazkhjfM360d1ENihynPmoLzHj6uRaXrKWcNxj+TgVHr55ax/6l?= =?us-ascii?Q?R0Z2xfTRQ0vpAgUXfzy8tIEj0SNb1K85ZWhME5mBUTBVt2h+7z1jSxhLtetd?= =?us-ascii?Q?I4j48ckQv4/+10YpqfkLiKpOMxzfjBEopngFstFdNyBrHNtUH2tuLOTtFe9d?= =?us-ascii?Q?ERdyf04yhF9F5brlnvpvpjJsA3vEyQ2krnsYU8zvUdr3mC+8fXAZDVboX6Pv?= =?us-ascii?Q?e1h6QazIdp4hzJsNM9o5hCLjFFO9oT5v/o81yQ+UcYgUDHSWRssx3orPoEPe?= =?us-ascii?Q?KiECwktl78u6hecNQBCPJLY2Y7x5TX4AX9B8PvS2hLmmHvlrrBVcocaU5N31?= =?us-ascii?Q?gLH5H1Gz14bCtiaryGFae37NtLuQCo92rYrKSoVaDy+VpZ/T49/ZWTAKjkqO?= =?us-ascii?Q?BkUDqj5xZUHqkZILl13UkLaBidWxiTPnVQ6/r0LZK8uLyHBCXORMh+zbnzNB?= =?us-ascii?Q?pMKYTPLRSTDIMM6DpTksLppI?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB3117.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9340b843-2541-4b2d-6d5a-08d8f411eff4 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Mar 2021 06:55:14.8920 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wDa5388UXCvFWMf9QejVmhZJROWoHZdeazWTvj37IGZM42NYt+jrWqS7pBtil2c6tf0lzr1qMvVFiOIse2tj5XTXZ4HmTf5E4yXA1dDROXA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4640 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [dpdk-dev v21.11] [PATCH v9 8/8] eventdev: simplify Rx adapter event vector config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: pbhagavatula@marvell.com > Sent: Tuesday, March 30, 2021 1:52 PM > To: jerinj@marvell.com; Jayatheerthan, Jay ;= Carrillo, Erik G ; Gujjar, > Abhinandan S ; McDaniel, Timothy ; hemant.agrawal@nxp.com; Van > Haaren, Harry ; mattias.ronnblom ; Ma, Liang J > ; Ray Kinsella ; Neil Horman > Cc: dev@dpdk.org; Pavan Nikhilesh > Subject: [dpdk-dev v21.11] [PATCH v9 8/8] eventdev: simplify Rx adapter e= vent vector config >=20 > From: Pavan Nikhilesh >=20 > Include vector configuration into the structure > ``rte_event_eth_rx_adapter_queue_conf`` used when configuring rest > of the Rx adapter ethernet device Rx queue parameters. > This simplifies event vector configuration as it avoids splitting > configuration per Rx queue. >=20 > Signed-off-by: Pavan Nikhilesh > --- > app/test-eventdev/test_pipeline_common.c | 16 +- > lib/librte_eventdev/eventdev_pmd.h | 29 --- > .../rte_event_eth_rx_adapter.c | 179 ++++++------------ > .../rte_event_eth_rx_adapter.h | 27 --- > lib/librte_eventdev/version.map | 1 - > 5 files changed, 63 insertions(+), 189 deletions(-) >=20 > diff --git a/app/test-eventdev/test_pipeline_common.c b/app/test-eventdev= /test_pipeline_common.c > index d5ef90500..76aee254b 100644 > --- a/app/test-eventdev/test_pipeline_common.c > +++ b/app/test-eventdev/test_pipeline_common.c > @@ -331,7 +331,6 @@ pipeline_event_rx_adapter_setup(struct evt_options *o= pt, uint8_t stride, > uint16_t prod; > struct rte_mempool *vector_pool =3D NULL; > struct rte_event_eth_rx_adapter_queue_conf queue_conf; > - struct rte_event_eth_rx_adapter_event_vector_config vec_conf; >=20 > memset(&queue_conf, 0, > sizeof(struct rte_event_eth_rx_adapter_queue_conf)); > @@ -397,8 +396,12 @@ pipeline_event_rx_adapter_setup(struct evt_options *= opt, uint8_t stride, > } >=20 > if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR) { > + queue_conf.vector_sz =3D opt->vector_size; > + queue_conf.vector_timeout_ns =3D > + opt->vector_tmo_nsec; > queue_conf.rx_queue_flags |=3D > RTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR; > + queue_conf.vector_mp =3D vector_pool; > } else { > evt_err("Rx adapter doesn't support event vector"); > return -EINVAL; > @@ -418,17 +421,6 @@ pipeline_event_rx_adapter_setup(struct evt_options *= opt, uint8_t stride, > return ret; > } >=20 > - if (opt->ena_vector) { > - vec_conf.vector_sz =3D opt->vector_size; > - vec_conf.vector_timeout_ns =3D opt->vector_tmo_nsec; > - vec_conf.vector_mp =3D vector_pool; > - if (rte_event_eth_rx_adapter_queue_event_vector_config( > - prod, prod, -1, &vec_conf) < 0) { > - evt_err("Failed to configure event vectorization for Rx adapter"); > - return -EINVAL; > - } > - } > - > if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) { > uint32_t service_id =3D -1U; >=20 > diff --git a/lib/librte_eventdev/eventdev_pmd.h b/lib/librte_eventdev/eve= ntdev_pmd.h > index 0f724ac85..63b3bc4b5 100644 > --- a/lib/librte_eventdev/eventdev_pmd.h > +++ b/lib/librte_eventdev/eventdev_pmd.h > @@ -667,32 +667,6 @@ typedef int (*eventdev_eth_rx_adapter_vector_limits_= get_t)( > const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev, > struct rte_event_eth_rx_adapter_vector_limits *limits); >=20 > -struct rte_event_eth_rx_adapter_event_vector_config; > -/** > - * Enable event vector on an given Rx queue of a ethernet devices belong= ing to > - * the Rx adapter. > - * > - * @param dev > - * Event device pointer > - * > - * @param eth_dev > - * Ethernet device pointer > - * > - * @param rx_queue_id > - * The Rx queue identifier > - * > - * @param config > - * Pointer to the event vector configuration structure. > - * > - * @return > - * - 0: Success. > - * - <0: Error code returned by the driver function. > - */ > -typedef int (*eventdev_eth_rx_adapter_event_vector_config_t)( > - const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev, > - int32_t rx_queue_id, > - const struct rte_event_eth_rx_adapter_event_vector_config *config); > - > typedef uint32_t rte_event_pmd_selftest_seqn_t; > extern int rte_event_pmd_selftest_seqn_dynfield_offset; >=20 > @@ -1118,9 +1092,6 @@ struct rte_eventdev_ops { > eventdev_eth_rx_adapter_vector_limits_get_t > eth_rx_adapter_vector_limits_get; > /**< Get event vector limits for the Rx adapter */ > - eventdev_eth_rx_adapter_event_vector_config_t > - eth_rx_adapter_event_vector_config; > - /**< Configure Rx adapter with event vector */ >=20 > eventdev_timer_adapter_caps_get_t timer_adapter_caps_get; > /**< Get timer adapter capabilities */ > diff --git a/lib/librte_eventdev/rte_event_eth_rx_adapter.c b/lib/librte_= eventdev/rte_event_eth_rx_adapter.c > index e273b3acf..5cdb3c3cb 100644 > --- a/lib/librte_eventdev/rte_event_eth_rx_adapter.c > +++ b/lib/librte_eventdev/rte_event_eth_rx_adapter.c > @@ -1896,6 +1896,24 @@ rxa_add_queue(struct rte_event_eth_rx_adapter *rx_= adapter, > } else > qi_ev->flow_id =3D 0; >=20 > + if (conf->rx_queue_flags & > + RTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR) { > + queue_info->ena_vector =3D 1; > + qi_ev->event_type =3D RTE_EVENT_TYPE_ETH_RX_ADAPTER_VECTOR; > + rxa_set_vector_data(queue_info, conf->vector_sz, > + conf->vector_timeout_ns, conf->vector_mp, > + rx_queue_id, dev_info->dev->data->port_id); > + rx_adapter->ena_vector =3D 1; > + rx_adapter->vector_tmo_ticks =3D > + rx_adapter->vector_tmo_ticks ? > + RTE_MIN(queue_info->vector_data > + .vector_timeout_ticks >> > + 1, > + rx_adapter->vector_tmo_ticks) : > + queue_info->vector_data.vector_timeout_ticks >> > + 1; > + } > + > rxa_update_queue(rx_adapter, dev_info, rx_queue_id, 1); > if (rxa_polled_queue(dev_info, rx_queue_id)) { > rx_adapter->num_rx_polled +=3D !pollq; > @@ -1921,42 +1939,6 @@ rxa_add_queue(struct rte_event_eth_rx_adapter *rx_= adapter, > } > } >=20 > -static void > -rxa_sw_event_vector_configure( > - struct rte_event_eth_rx_adapter *rx_adapter, uint16_t eth_dev_id, > - int rx_queue_id, > - const struct rte_event_eth_rx_adapter_event_vector_config *config) > -{ > - struct eth_device_info *dev_info =3D &rx_adapter->eth_devices[eth_dev_i= d]; > - struct eth_rx_queue_info *queue_info; > - struct rte_event *qi_ev; > - > - if (rx_queue_id =3D=3D -1) { > - uint16_t nb_rx_queues; > - uint16_t i; > - > - nb_rx_queues =3D dev_info->dev->data->nb_rx_queues; > - for (i =3D 0; i < nb_rx_queues; i++) > - rxa_sw_event_vector_configure(rx_adapter, eth_dev_id, i, > - config); > - return; > - } > - > - queue_info =3D &dev_info->rx_queue[rx_queue_id]; > - qi_ev =3D (struct rte_event *)&queue_info->event; > - queue_info->ena_vector =3D 1; > - qi_ev->event_type =3D RTE_EVENT_TYPE_ETH_RX_ADAPTER_VECTOR; > - rxa_set_vector_data(queue_info, config->vector_sz, > - config->vector_timeout_ns, config->vector_mp, > - rx_queue_id, dev_info->dev->data->port_id); > - rx_adapter->ena_vector =3D 1; > - rx_adapter->vector_tmo_ticks =3D > - rx_adapter->vector_tmo_ticks ? > - RTE_MIN(config->vector_timeout_ns >> 1, > - rx_adapter->vector_tmo_ticks) : > - config->vector_timeout_ns >> 1; > -} > - > static int rxa_sw_add(struct rte_event_eth_rx_adapter *rx_adapter, > uint16_t eth_dev_id, > int rx_queue_id, > @@ -2271,6 +2253,7 @@ rte_event_eth_rx_adapter_queue_add(uint8_t id, > struct rte_event_eth_rx_adapter *rx_adapter; > struct rte_eventdev *dev; > struct eth_device_info *dev_info; > + struct rte_event_eth_rx_adapter_vector_limits limits; >=20 > RTE_EVENT_ETH_RX_ADAPTER_ID_VALID_OR_ERR_RET(id, -EINVAL); > RTE_ETH_VALID_PORTID_OR_ERR_RET(eth_dev_id, -EINVAL); > @@ -2298,13 +2281,46 @@ rte_event_eth_rx_adapter_queue_add(uint8_t id, > return -EINVAL; > } >=20 > - if ((cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR) =3D=3D 0 && > - (queue_conf->rx_queue_flags & > - RTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR)) { > - RTE_EDEV_LOG_ERR("Event vectorization is not supported," > - " eth port: %" PRIu16 " adapter id: %" PRIu8, > - eth_dev_id, id); > - return -EINVAL; > + if (queue_conf->rx_queue_flags & > + RTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR) { > + > + if ((cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR) =3D=3D 0) { > + RTE_EDEV_LOG_ERR("Event vectorization is not supported," > + " eth port: %" PRIu16 > + " adapter id: %" PRIu8, > + eth_dev_id, id); > + return -EINVAL; > + } > + > + ret =3D rte_event_eth_rx_adapter_vector_limits_get( > + rx_adapter->eventdev_id, eth_dev_id, &limits); > + if (ret < 0) { > + RTE_EDEV_LOG_ERR("Failed to get event device vector limits," > + " eth port: %" PRIu16 > + " adapter id: %" PRIu8, > + eth_dev_id, id); > + return -EINVAL; > + } > + if (queue_conf->vector_sz < limits.min_sz || > + queue_conf->vector_sz > limits.max_sz || > + queue_conf->vector_timeout_ns < limits.min_timeout_ns || > + queue_conf->vector_timeout_ns > limits.max_timeout_ns || > + queue_conf->vector_mp =3D=3D NULL) { > + RTE_EDEV_LOG_ERR("Invalid event vector configuration," > + " eth port: %" PRIu16 > + " adapter id: %" PRIu8, > + eth_dev_id, id); > + return -EINVAL; > + } > + if (queue_conf->vector_mp->elt_size < > + (sizeof(struct rte_event_vector) + > + (sizeof(uintptr_t) * queue_conf->vector_sz))) { > + RTE_EDEV_LOG_ERR("Invalid event vector configuration," > + " eth port: %" PRIu16 > + " adapter id: %" PRIu8, > + eth_dev_id, id); > + return -EINVAL; > + } > } >=20 > if ((cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ) =3D=3D 0 && > @@ -2500,83 +2516,6 @@ rte_event_eth_rx_adapter_queue_del(uint8_t id, uin= t16_t eth_dev_id, > return ret; > } >=20 > -int > -rte_event_eth_rx_adapter_queue_event_vector_config( > - uint8_t id, uint16_t eth_dev_id, int32_t rx_queue_id, > - struct rte_event_eth_rx_adapter_event_vector_config *config) > -{ > - struct rte_event_eth_rx_adapter_vector_limits limits; > - struct rte_event_eth_rx_adapter *rx_adapter; > - struct rte_eventdev *dev; > - uint32_t cap; > - int ret; > - > - RTE_EVENT_ETH_RX_ADAPTER_ID_VALID_OR_ERR_RET(id, -EINVAL); > - RTE_ETH_VALID_PORTID_OR_ERR_RET(eth_dev_id, -EINVAL); > - > - rx_adapter =3D rxa_id_to_adapter(id); > - if ((rx_adapter =3D=3D NULL) || (config =3D=3D NULL)) > - return -EINVAL; > - > - dev =3D &rte_eventdevs[rx_adapter->eventdev_id]; > - ret =3D rte_event_eth_rx_adapter_caps_get(rx_adapter->eventdev_id, > - eth_dev_id, &cap); > - if (ret) { > - RTE_EDEV_LOG_ERR("Failed to get adapter caps edev %" PRIu8 > - "eth port %" PRIu16, > - id, eth_dev_id); > - return ret; > - } > - > - if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR)) { > - RTE_EDEV_LOG_ERR("Event vectorization is not supported," > - " eth port: %" PRIu16 " adapter id: %" PRIu8, > - eth_dev_id, id); > - return -EINVAL; > - } > - > - ret =3D rte_event_eth_rx_adapter_vector_limits_get( > - rx_adapter->eventdev_id, eth_dev_id, &limits); > - if (ret) { > - RTE_EDEV_LOG_ERR("Failed to get vector limits edev %" PRIu8 > - "eth port %" PRIu16, > - rx_adapter->eventdev_id, eth_dev_id); > - return ret; > - } > - > - if (config->vector_sz < limits.min_sz || > - config->vector_sz > limits.max_sz || > - config->vector_timeout_ns < limits.min_timeout_ns || > - config->vector_timeout_ns > limits.max_timeout_ns || > - config->vector_mp =3D=3D NULL) { > - RTE_EDEV_LOG_ERR("Invalid event vector configuration," > - " eth port: %" PRIu16 " adapter id: %" PRIu8, > - eth_dev_id, id); > - return -EINVAL; > - } > - if (config->vector_mp->elt_size < > - (sizeof(struct rte_event_vector) + > - (sizeof(uintptr_t) * config->vector_sz))) { > - RTE_EDEV_LOG_ERR("Invalid event vector configuration," > - " eth port: %" PRIu16 " adapter id: %" PRIu8, > - eth_dev_id, id); > - return -EINVAL; > - } > - > - if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT) { > - RTE_FUNC_PTR_OR_ERR_RET( > - *dev->dev_ops->eth_rx_adapter_event_vector_config, > - -ENOTSUP); > - ret =3D dev->dev_ops->eth_rx_adapter_event_vector_config( > - dev, &rte_eth_devices[eth_dev_id], rx_queue_id, config); > - } else { > - rxa_sw_event_vector_configure(rx_adapter, eth_dev_id, > - rx_queue_id, config); > - } > - > - return ret; > -} > - > int > rte_event_eth_rx_adapter_vector_limits_get( > uint8_t dev_id, uint16_t eth_port_id, > diff --git a/lib/librte_eventdev/rte_event_eth_rx_adapter.h b/lib/librte_= eventdev/rte_event_eth_rx_adapter.h > index 7407cde00..3f8b36229 100644 > --- a/lib/librte_eventdev/rte_event_eth_rx_adapter.h > +++ b/lib/librte_eventdev/rte_event_eth_rx_adapter.h > @@ -171,9 +171,6 @@ struct rte_event_eth_rx_adapter_queue_conf { > * The event adapter sets ev.event_type to RTE_EVENT_TYPE_ETHDEV in the > * enqueued event. > */ > -}; > - > -struct rte_event_eth_rx_adapter_event_vector_config { > uint16_t vector_sz; > /**< > * Indicates the maximum number for mbufs to combine and form a vector. > @@ -548,30 +545,6 @@ int rte_event_eth_rx_adapter_vector_limits_get( > uint8_t dev_id, uint16_t eth_port_id, > struct rte_event_eth_rx_adapter_vector_limits *limits); >=20 > -/** > - * Configure event vectorization for a given ethernet device queue, that= has > - * been added to a event eth Rx adapter. > - * > - * @param id > - * The identifier of the ethernet Rx event adapter. > - * > - * @param eth_dev_id > - * The identifier of the ethernet device. > - * > - * @param rx_queue_id > - * Ethernet device receive queue index. > - * If rx_queue_id is -1, then all Rx queues configured for the ethernet= device > - * are configured with event vectorization. > - * > - * @return > - * - 0: Success, Receive queue configured correctly. > - * - <0: Error code on failure. > - */ > -__rte_experimental > -int rte_event_eth_rx_adapter_queue_event_vector_config( > - uint8_t id, uint16_t eth_dev_id, int32_t rx_queue_id, > - struct rte_event_eth_rx_adapter_event_vector_config *config); > - > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eventdev/version.map b/lib/librte_eventdev/versio= n.map > index 902df0ae3..34c1c830e 100644 > --- a/lib/librte_eventdev/version.map > +++ b/lib/librte_eventdev/version.map > @@ -142,7 +142,6 @@ EXPERIMENTAL { > #added in 21.05 > rte_event_vector_pool_create; > rte_event_eth_rx_adapter_vector_limits_get; > - rte_event_eth_rx_adapter_queue_event_vector_config; > }; >=20 > INTERNAL { > -- > 2.17.1 Looks good. Thanks for all your effort and help! Acked-by: Jay Jayatheerthan