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charset="iso-8859-1" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN7PR11MB6725.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c789df7f-fc82-4a29-bba1-08dcdee19f11 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Sep 2024 10:46:19.7374 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QOO3rOlweeI4cXePao3HtOOv2fwAzlcjnDOBXJaCyPYLfILzTqu8Aqo8DgI1K+lGb5s/xJZRgjDafgcSPg64bg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB7836 X-OriginatorOrg: intel.com Content-Transfer-Encoding: quoted-printable X-Mailman-Approved-At: Sat, 28 Sep 2024 00:13:29 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org >On 9/26/2024 3:03 PM, Meade, Niall wrote: >>> From: Ferruh Yigit >>> Sent: Thursday, September 26, 2024 12:16 AM >>> To: Meade, Niall ; Thomas Monjalon ; Andrew Rybchenko ; Roman Zhukov >>> Cc: dev@dpdk.org >>> Subject: Re: [PATCH v1] ethdev: fix int overflow in descriptor count lo= gic >> >>>> The resolution involves upcasting nb_desc to a uint32_t before the >>>> RTE_ALIGN_CEIL macro is applied. This change ensures that the subseque= nt >>>> call to RTE_ALIGN_FLOOR(nb_desc + (nb_align - 1), nb_align) does not >>>> result in an overflow, as it would when nb_desc is a uint16_t. By using >>>> a uint32_t for these operations, the correct behavior is maintained >>>> without the risk of overflow. >>>> >>> >>> Hi Niall, >> >> Hi Ferruh, >> >>> Thanks for the patch. >>> >>> For the 'RTE_ALIGN_CEIL(val, align)' macro, 'align' should be power of >>> two, as 'desc_lim->nb_align' is uint16_t, max value it can get is 2^15. >>> 'val' should be smaller than or equal to 'align', so '*nb_desc' can be >>> maximum 2^15. >>> >>> So RTE_ALIGN_CEIL(2^15-1, 2^15) =3D 2^15, I think this should work fine >>> (although I didn't test). >>> >>> And even with your uint32_t cast, I think following will fail: >>> RTE_ALIGN_CEIL(2^16-1, 2^15) >>> (again, not tested). >>> >> >> I tested my code with these values and the behaviour is as expected from >> what I can see. >> At a high level I ran into this issue when passing uint16_tMAX into >> rte_eth_dev_adjust_nb_rx_tx_desc() with the intent of selecting the maxi= mum >> ring descriptor size but the minimum was selected. >> >>> Or maybe I am missing a case, can you please give some actual numbers to >>> show the problem and the fix? >> >> Yes sure! If we take an example of val=3D (2^16)-1 and align=3D 32. >> RTE_ALIGN_CEIL(val, align)=A0calls RTE_ALIGN_FLOOR(val + align - 1, alig= n). With >> val as a uint16_t this subsequent macro call results in a wrap around fo= r val >> (originally was the max uint16_t and now we are attempting to add align = to >> it). The returned value of RTE_ALIGN_CEIL() in this case is 0. This resu= lts in >> nb_desc being set to 0, and later set to the minimum ring descriptor siz= e for >> that NIC with *nb_desc =3D RTE_MAX(*nb_desc, desc_lim->nb_min). >> >> While this example is an unreasonably large request for a descriptor rin= g size, >> the expected behaviour would be that the descriptor ring=A0size defaults= back to >> the maximum possible for that particular NIC, not to the minimum which it >> currently does. >> By introducing a uint32_t, the wrap around in RTE_ALIGN_FLOOR() is avoid= ed, >> keeping the large value of nb_desc_32 which is later set to an appropria= te size >> in RTE_MIN(*nb_desc_32, desc_lim->nb_max) >> > >I see the problem now, thanks. > >When value > (2^16 - align), next aligned value is 2^16, which is >UINT16_MAX + 1, hence wraps to 0, this is kind of expected. > >For the relevant code, assuming 'desc_lim->nb_max' & 'desc_lim->nb_min' >are already aligned to 'desc_lim->nb_align', following should fix the >issue, that seems simpler to me, what do you think: Yes, while it is a simpler solution there is still potential for an overflo= w if nb_max is equal to 0. If nb_max is 0 while nb_desc is UINT16_MAX, UINT16_MAX will = be passed to the align macro resulting in an overflow again. > >``` >if (desc_lim->nb_max !=3D 0) >=A0=A0=A0=A0=A0=A0=A0 *nb_desc =3D RTE_MIN(*nb_desc, desc_lim->nb_max); > >nb_desc_32 =3D RTE_MAX(nb_desc_32, desc_lim->nb_min); > >if (desc_lim->nb_align !=3D 0) >=A0=A0=A0=A0=A0=A0=A0 *nb_desc =3D RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_a= lign); >``` > >Basically just changing the order of the operations... > >It is not easy to see the problem, can you please give sample values in >the commit log (for '*nb_desc', 'nb_align', 'nb_max' & 'nb_min'), that >makes much easier to see why above works. Yes, good idea! I'll add an example to the commit log for clarity. -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact = the sender and delete all copies.