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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Ferruh, We have sent a patch set which includes base PMD driver for NapaTech smartN= iC for DPDK v24.07. This time, driver has limited basic functionality(Link up only) and we have= made refactoring to split it into smaller patches. Extended functionality is planned for upstream to the next release DPDK 24.= 11. Patches have passed the CI but there are several code style warnings which = we assumed as false-positive. Could you please take a look at these patches and suggest us how we can pro= cced with it? Best regards, Serhii ________________________________ From: Mykola Kostenok Sent: 04 June 2024 13:29 To: Serhii Iliushyk ; dev@dpdk.org Cc: Christian Koue Muf ; andrew.rybchenko@oktetlabs.ru ; ferruh.yigit@amd.com Subject: RE: [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNi= C Recheck-request: iol-unit-amd64-testing, iol-compile-amd64-testing, iol-uni= t-arm64-testing, iol-compile-arm64-testing > -----Original Message----- > From: Serhii Iliushyk > Sent: Monday, June 3, 2024 7:18 PM > To: dev@dpdk.org > Cc: Mykola Kostenok ; Christian Koue Muf > ; andrew.rybchenko@oktetlabs.ru; > ferruh.yigit@amd.com > Subject: [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNiC > > The NTNIC PMD does not rely on a kernel space Napatech driver, > thus all defines related to the register layout is part of the PMD > code, which will be added in later commits. > > Signed-off-by: Serhii Iliushyk > --- > .../supported/nthw_fpga_9563_055_039_0000.c | 3488 > +++++++++++++++++ > .../nthw/supported/nthw_fpga_instances.c | 6 + > .../nthw/supported/nthw_fpga_instances.h | 7 + > .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 93 + > .../nthw/supported/nthw_fpga_mod_str_map.c | 78 + > .../nthw/supported/nthw_fpga_mod_str_map.h | 11 + > .../nthw/supported/nthw_fpga_param_defs.h | 232 ++ > .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 94 + > .../nthw/supported/nthw_fpga_reg_defs_cat.h | 237 ++ > .../nthw/supported/nthw_fpga_reg_defs_cb.h | 73 + > .../nthw/supported/nthw_fpga_reg_defs_cor.h | 81 + > .../nthw/supported/nthw_fpga_reg_defs_cpy.h | 112 + > .../nthw/supported/nthw_fpga_reg_defs_csu.h | 30 + > .../nthw/supported/nthw_fpga_reg_defs_dbs.h | 144 + > .../nthw/supported/nthw_fpga_reg_defs_ddp.h | 34 + > .../nthw/supported/nthw_fpga_reg_defs_epp.h | 64 + > .../nthw/supported/nthw_fpga_reg_defs_eqm.h | 45 + > .../nthw/supported/nthw_fpga_reg_defs_fhm.h | 48 + > .../nthw/supported/nthw_fpga_reg_defs_flm.h | 237 ++ > .../nthw/supported/nthw_fpga_reg_defs_gfg.h | 126 + > .../nthw/supported/nthw_fpga_reg_defs_gmf.h | 68 + > .../supported/nthw_fpga_reg_defs_gpio_phy.h | 48 + > .../nthw_fpga_reg_defs_gpio_phy_ports.h | 72 + > .../supported/nthw_fpga_reg_defs_gpio_sfpp.h | 34 + > .../nthw/supported/nthw_fpga_reg_defs_hfu.h | 48 + > .../nthw/supported/nthw_fpga_reg_defs_hif.h | 79 + > .../nthw/supported/nthw_fpga_reg_defs_hsh.h | 49 + > .../nthw/supported/nthw_fpga_reg_defs_i2cm.h | 38 + > .../nthw/supported/nthw_fpga_reg_defs_ifr.h | 41 + > .../nthw/supported/nthw_fpga_reg_defs_igam.h | 28 + > .../nthw/supported/nthw_fpga_reg_defs_iic.h | 96 + > .../nthw/supported/nthw_fpga_reg_defs_ins.h | 29 + > .../nthw/supported/nthw_fpga_reg_defs_ioa.h | 44 + > .../nthw/supported/nthw_fpga_reg_defs_ipf.h | 84 + > .../nthw/supported/nthw_fpga_reg_defs_km.h | 125 + > .../nthw/supported/nthw_fpga_reg_defs_mac.h | 177 + > .../supported/nthw_fpga_reg_defs_mac_pcs.h | 298 ++ > .../nthw_fpga_reg_defs_mac_pcs_xxv.h | 1092 ++++++ > .../supported/nthw_fpga_reg_defs_mac_rx.h | 90 + > .../supported/nthw_fpga_reg_defs_mac_tfg.h | 42 + > .../supported/nthw_fpga_reg_defs_mac_tx.h | 70 + > .../nthw/supported/nthw_fpga_reg_defs_msk.h | 42 + > .../supported/nthw_fpga_reg_defs_pci_rd_tg.h | 37 + > .../supported/nthw_fpga_reg_defs_pci_ta.h | 32 + > .../supported/nthw_fpga_reg_defs_pci_wr_tg.h | 40 + > .../nthw/supported/nthw_fpga_reg_defs_pcie3.h | 281 ++ > .../nthw_fpga_reg_defs_pcm_nt400dxx.h | 19 + > .../nthw_fpga_reg_defs_pcm_nt50b01_01.h | 19 + > .../nthw/supported/nthw_fpga_reg_defs_pcs.h | 92 + > .../supported/nthw_fpga_reg_defs_pcs100.h | 90 + > .../nthw/supported/nthw_fpga_reg_defs_pdb.h | 47 + > .../nthw/supported/nthw_fpga_reg_defs_pdi.h | 48 + > .../supported/nthw_fpga_reg_defs_phy_tile.h | 196 + > .../nthw_fpga_reg_defs_prm_nt400dxx.h | 19 + > .../nthw_fpga_reg_defs_prm_nt50b01_01.h | 19 + > .../nthw/supported/nthw_fpga_reg_defs_qsl.h | 65 + > .../nthw/supported/nthw_fpga_reg_defs_qspi.h | 89 + > .../nthw/supported/nthw_fpga_reg_defs_r2drp.h | 29 + > .../nthw/supported/nthw_fpga_reg_defs_rac.h | 72 + > .../nthw/supported/nthw_fpga_reg_defs_rfd.h | 37 + > .../nthw/supported/nthw_fpga_reg_defs_rmc.h | 35 + > .../nthw/supported/nthw_fpga_reg_defs_roa.h | 67 + > .../nthw/supported/nthw_fpga_reg_defs_rpf.h | 30 + > .../nthw/supported/nthw_fpga_reg_defs_rpl.h | 42 + > .../supported/nthw_fpga_reg_defs_rpp_lr.h | 36 + > .../supported/nthw_fpga_reg_defs_rst9563.h | 59 + > .../nthw/supported/nthw_fpga_reg_defs_sdc.h | 44 + > .../nthw/supported/nthw_fpga_reg_defs_slc.h | 33 + > .../supported/nthw_fpga_reg_defs_slc_lr.h | 22 + > .../nthw/supported/nthw_fpga_reg_defs_spim.h | 75 + > .../nthw/supported/nthw_fpga_reg_defs_spis.h | 50 + > .../nthw/supported/nthw_fpga_reg_defs_sta.h | 59 + > .../supported/nthw_fpga_reg_defs_tempmon.h | 29 + > .../nthw/supported/nthw_fpga_reg_defs_tint.h | 27 + > .../nthw/supported/nthw_fpga_reg_defs_tsm.h | 294 ++ > .../supported/nthw_fpga_reg_defs_tx_cpy.h | 22 + > .../supported/nthw_fpga_reg_defs_tx_csi.h | 22 + > .../supported/nthw_fpga_reg_defs_tx_cso.h | 22 + > .../supported/nthw_fpga_reg_defs_tx_ins.h | 22 + > .../supported/nthw_fpga_reg_defs_tx_rpl.h | 22 + > 80 files changed, 10177 insertions(+) > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h > create mode 100644 > drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h > > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c > b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c > new file mode 100644 > index 0000000000..a7ee892007 > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c > @@ -0,0 +1,3488 @@ > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +#include "nthw_register.h" > + > +static nthw_fpga_field_init_s cat_cct_ctrl_fields[] =3D { > + { CAT_CCT_CTRL_ADR, 8, 0, 0x0000 }, > + { CAT_CCT_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cct_data_fields[] =3D { > + { CAT_CCT_DATA_COLOR, 32, 0, 0x0000 }, > + { CAT_CCT_DATA_KM, 4, 32, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cfn_ctrl_fields[] =3D { > + { CAT_CFN_CTRL_ADR, 6, 0, 0x0000 }, > + { CAT_CFN_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cfn_data_fields[] =3D { > + { CAT_CFN_DATA_ENABLE, 1, 0, 0x0000 }, > + { CAT_CFN_DATA_ERR_CV, 2, 99, 0x0000 }, > + { CAT_CFN_DATA_ERR_FCS, 2, 101, 0x0000 }, > + { CAT_CFN_DATA_ERR_INV, 1, 98, 0x0000 }, > + { CAT_CFN_DATA_ERR_L3_CS, 2, 105, 0x0000 }, > + { CAT_CFN_DATA_ERR_L4_CS, 2, 107, 0x0000 }, > + { CAT_CFN_DATA_ERR_TNL_L3_CS, 2, 109, 0x0000 }, > + { CAT_CFN_DATA_ERR_TNL_L4_CS, 2, 111, 0x0000 }, > + { CAT_CFN_DATA_ERR_TNL_TTL_EXP, 2, 115, 0x0000 }, > + { CAT_CFN_DATA_ERR_TRUNC, 2, 103, 0x0000 }, > + { CAT_CFN_DATA_ERR_TTL_EXP, 2, 113, 0x0000 }, > + { CAT_CFN_DATA_INV, 1, 1, 0x0000 }, > + { CAT_CFN_DATA_KM0_OR, 3, 173, 0x0000 }, > + { CAT_CFN_DATA_KM1_OR, 3, 176, 0x0000 }, > + { CAT_CFN_DATA_LC, 8, 164, 0x0000 }, > + { CAT_CFN_DATA_LC_INV, 1, 172, 0x0000 }, > + { CAT_CFN_DATA_MAC_PORT, 2, 117, 0x0000 }, > + { CAT_CFN_DATA_PM_AND_INV, 1, 161, 0x0000 }, > + { CAT_CFN_DATA_PM_CMB, 4, 157, 0x0000 }, > + { CAT_CFN_DATA_PM_CMP, 32, 119, 0x0000 }, > + { CAT_CFN_DATA_PM_DCT, 2, 151, 0x0000 }, > + { CAT_CFN_DATA_PM_EXT_INV, 4, 153, 0x0000 }, > + { CAT_CFN_DATA_PM_INV, 1, 163, 0x0000 }, > + { CAT_CFN_DATA_PM_OR_INV, 1, 162, 0x0000 }, > + { CAT_CFN_DATA_PTC_CFP, 2, 5, 0x0000 }, > + { CAT_CFN_DATA_PTC_FRAG, 4, 36, 0x0000 }, > + { CAT_CFN_DATA_PTC_INV, 1, 2, 0x0000 }, > + { CAT_CFN_DATA_PTC_IP_PROT, 8, 40, 0x0000 }, > + { CAT_CFN_DATA_PTC_ISL, 2, 3, 0x0000 }, > + { CAT_CFN_DATA_PTC_L2, 7, 12, 0x0000 }, > + { CAT_CFN_DATA_PTC_L3, 3, 33, 0x0000 }, > + { CAT_CFN_DATA_PTC_L4, 5, 48, 0x0000 }, > + { CAT_CFN_DATA_PTC_MAC, 5, 7, 0x0000 }, > + { CAT_CFN_DATA_PTC_MPLS, 8, 25, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_FRAG, 4, 81, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_IP_PROT, 8, 85, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_L2, 2, 64, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_L3, 3, 78, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_L4, 5, 93, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_MPLS, 8, 70, 0x0000 }, > + { CAT_CFN_DATA_PTC_TNL_VLAN, 4, 66, 0x0000 }, > + { CAT_CFN_DATA_PTC_TUNNEL, 11, 53, 0x0000 }, > + { CAT_CFN_DATA_PTC_VLAN, 4, 21, 0x0000 }, > + { CAT_CFN_DATA_PTC_VNTAG, 2, 19, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cot_ctrl_fields[] =3D { > + { CAT_COT_CTRL_ADR, 6, 0, 0x0000 }, > + { CAT_COT_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cot_data_fields[] =3D { > + { CAT_COT_DATA_COLOR, 32, 0, 0x0000 }, > + { CAT_COT_DATA_KM, 4, 32, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cte_ctrl_fields[] =3D { > + { CAT_CTE_CTRL_ADR, 6, 0, 0x0000 }, > + { CAT_CTE_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cte_data_fields[] =3D { > + { CAT_CTE_DATA_COL_ENABLE, 1, 0, 0x0000 }, { > CAT_CTE_DATA_COR_ENABLE, 1, 1, 0x0000 }, > + { CAT_CTE_DATA_EPP_ENABLE, 1, 9, 0x0000 }, { > CAT_CTE_DATA_HSH_ENABLE, 1, 2, 0x0000 }, > + { CAT_CTE_DATA_HST_ENABLE, 1, 8, 0x0000 }, { > CAT_CTE_DATA_IPF_ENABLE, 1, 4, 0x0000 }, > + { CAT_CTE_DATA_MSK_ENABLE, 1, 7, 0x0000 }, { > CAT_CTE_DATA_PDB_ENABLE, 1, 6, 0x0000 }, > + { CAT_CTE_DATA_QSL_ENABLE, 1, 3, 0x0000 }, { > CAT_CTE_DATA_SLC_ENABLE, 1, 5, 0x0000 }, > + { CAT_CTE_DATA_TPE_ENABLE, 1, 10, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cts_ctrl_fields[] =3D { > + { CAT_CTS_CTRL_ADR, 9, 0, 0x0000 }, > + { CAT_CTS_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_cts_data_fields[] =3D { > + { CAT_CTS_DATA_CAT_A, 6, 0, 0x0000 }, > + { CAT_CTS_DATA_CAT_B, 6, 6, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_dct_ctrl_fields[] =3D { > + { CAT_DCT_CTRL_ADR, 13, 0, 0x0000 }, > + { CAT_DCT_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_dct_data_fields[] =3D { > + { CAT_DCT_DATA_RES, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_dct_sel_fields[] =3D { > + { CAT_DCT_SEL_LU, 2, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_exo_ctrl_fields[] =3D { > + { CAT_EXO_CTRL_ADR, 2, 0, 0x0000 }, > + { CAT_EXO_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_exo_data_fields[] =3D { > + { CAT_EXO_DATA_DYN, 5, 0, 0x0000 }, > + { CAT_EXO_DATA_OFS, 11, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_fte0_ctrl_fields[] =3D { > + { CAT_FTE0_CTRL_ADR, 9, 0, 0x0000 }, > + { CAT_FTE0_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_fte0_data_fields[] =3D { > + { CAT_FTE0_DATA_ENABLE, 8, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_fte1_ctrl_fields[] =3D { > + { CAT_FTE1_CTRL_ADR, 9, 0, 0x0000 }, > + { CAT_FTE1_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_fte1_data_fields[] =3D { > + { CAT_FTE1_DATA_ENABLE, 8, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_join_fields[] =3D { > + { CAT_JOIN_J1, 2, 0, 0x0000 }, > + { CAT_JOIN_J2, 1, 8, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcc_ctrl_fields[] =3D { > + { CAT_KCC_CTRL_ADR, 11, 0, 0x0000 }, > + { CAT_KCC_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcc_data_fields[] =3D { > + { CAT_KCC_DATA_CATEGORY, 8, 64, 0x0000 }, > + { CAT_KCC_DATA_ID, 12, 72, 0x0000 }, > + { CAT_KCC_DATA_KEY, 64, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kce0_ctrl_fields[] =3D { > + { CAT_KCE0_CTRL_ADR, 3, 0, 0x0000 }, > + { CAT_KCE0_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kce0_data_fields[] =3D { > + { CAT_KCE0_DATA_ENABLE, 8, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kce1_ctrl_fields[] =3D { > + { CAT_KCE1_CTRL_ADR, 3, 0, 0x0000 }, > + { CAT_KCE1_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kce1_data_fields[] =3D { > + { CAT_KCE1_DATA_ENABLE, 8, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcs0_ctrl_fields[] =3D { > + { CAT_KCS0_CTRL_ADR, 6, 0, 0x0000 }, > + { CAT_KCS0_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcs0_data_fields[] =3D { > + { CAT_KCS0_DATA_CATEGORY, 6, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcs1_ctrl_fields[] =3D { > + { CAT_KCS1_CTRL_ADR, 6, 0, 0x0000 }, > + { CAT_KCS1_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_kcs1_data_fields[] =3D { > + { CAT_KCS1_DATA_CATEGORY, 6, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_len_ctrl_fields[] =3D { > + { CAT_LEN_CTRL_ADR, 3, 0, 0x0000 }, > + { CAT_LEN_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_len_data_fields[] =3D { > + { CAT_LEN_DATA_DYN1, 5, 28, 0x0000 }, { CAT_LEN_DATA_DYN2, 5, > 33, 0x0000 }, > + { CAT_LEN_DATA_INV, 1, 38, 0x0000 }, { CAT_LEN_DATA_LOWER, 14, > 0, 0x0000 }, > + { CAT_LEN_DATA_UPPER, 14, 14, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_rck_ctrl_fields[] =3D { > + { CAT_RCK_CTRL_ADR, 8, 0, 0x0000 }, > + { CAT_RCK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cat_rck_data_fields[] =3D { > + { CAT_RCK_DATA_CM0U, 1, 1, 0x0000 }, { CAT_RCK_DATA_CM1U, 1, > 5, 0x0000 }, > + { CAT_RCK_DATA_CM2U, 1, 9, 0x0000 }, { CAT_RCK_DATA_CM3U, 1, > 13, 0x0000 }, > + { CAT_RCK_DATA_CM4U, 1, 17, 0x0000 }, { CAT_RCK_DATA_CM5U, 1, > 21, 0x0000 }, > + { CAT_RCK_DATA_CM6U, 1, 25, 0x0000 }, { CAT_RCK_DATA_CM7U, 1, > 29, 0x0000 }, > + { CAT_RCK_DATA_CML0, 1, 0, 0x0000 }, { CAT_RCK_DATA_CML1, 1, 4, > 0x0000 }, > + { CAT_RCK_DATA_CML2, 1, 8, 0x0000 }, { CAT_RCK_DATA_CML3, 1, > 12, 0x0000 }, > + { CAT_RCK_DATA_CML4, 1, 16, 0x0000 }, { CAT_RCK_DATA_CML5, 1, > 20, 0x0000 }, > + { CAT_RCK_DATA_CML6, 1, 24, 0x0000 }, { CAT_RCK_DATA_CML7, 1, > 28, 0x0000 }, > + { CAT_RCK_DATA_SEL0, 1, 2, 0x0000 }, { CAT_RCK_DATA_SEL1, 1, 6, > 0x0000 }, > + { CAT_RCK_DATA_SEL2, 1, 10, 0x0000 }, { CAT_RCK_DATA_SEL3, 1, 14, > 0x0000 }, > + { CAT_RCK_DATA_SEL4, 1, 18, 0x0000 }, { CAT_RCK_DATA_SEL5, 1, 22, > 0x0000 }, > + { CAT_RCK_DATA_SEL6, 1, 26, 0x0000 }, { CAT_RCK_DATA_SEL7, 1, 30, > 0x0000 }, > + { CAT_RCK_DATA_SEU0, 1, 3, 0x0000 }, { CAT_RCK_DATA_SEU1, 1, 7, > 0x0000 }, > + { CAT_RCK_DATA_SEU2, 1, 11, 0x0000 }, { CAT_RCK_DATA_SEU3, 1, > 15, 0x0000 }, > + { CAT_RCK_DATA_SEU4, 1, 19, 0x0000 }, { CAT_RCK_DATA_SEU5, 1, > 23, 0x0000 }, > + { CAT_RCK_DATA_SEU6, 1, 27, 0x0000 }, { CAT_RCK_DATA_SEU7, 1, > 31, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s cat_registers[] =3D { > + { CAT_CCT_CTRL, 30, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cct_ctrl_fields }, > + { CAT_CCT_DATA, 31, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cct_data_fields }, > + { CAT_CFN_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cfn_ctrl_fields }, > + { CAT_CFN_DATA, 11, 179, NTHW_FPGA_REG_TYPE_WO, 0, 44, > cat_cfn_data_fields }, > + { CAT_COT_CTRL, 28, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cot_ctrl_fields }, > + { CAT_COT_DATA, 29, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cot_data_fields }, > + { CAT_CTE_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cte_ctrl_fields }, > + { CAT_CTE_DATA, 25, 11, NTHW_FPGA_REG_TYPE_WO, 0, 11, > cat_cte_data_fields }, > + { CAT_CTS_CTRL, 26, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cts_ctrl_fields }, > + { CAT_CTS_DATA, 27, 12, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_cts_data_fields }, > + { CAT_DCT_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_dct_ctrl_fields }, > + { CAT_DCT_DATA, 7, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_dct_data_fields }, > + { CAT_DCT_SEL, 4, 2, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_dct_sel_fields }, > + { CAT_EXO_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_exo_ctrl_fields }, > + { CAT_EXO_DATA, 1, 27, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_exo_data_fields }, > + { CAT_FTE0_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_fte0_ctrl_fields }, > + { CAT_FTE0_DATA, 17, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_fte0_data_fields }, > + { CAT_FTE1_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_fte1_ctrl_fields }, > + { CAT_FTE1_DATA, 23, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_fte1_data_fields }, > + { CAT_JOIN, 5, 9, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_join_fields }, > + { CAT_KCC_CTRL, 32, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_kcc_ctrl_fields }, > + { CAT_KCC_DATA, 33, 84, NTHW_FPGA_REG_TYPE_WO, 0, 3, > cat_kcc_data_fields }, > + { CAT_KCE0_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_kce0_ctrl_fields }, > + { CAT_KCE0_DATA, 13, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_kce0_data_fields }, > + { CAT_KCE1_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_kce1_ctrl_fields }, > + { CAT_KCE1_DATA, 19, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_kce1_data_fields }, > + { CAT_KCS0_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_kcs0_ctrl_fields }, > + { CAT_KCS0_DATA, 15, 6, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_kcs0_data_fields }, > + { CAT_KCS1_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_kcs1_ctrl_fields }, > + { CAT_KCS1_DATA, 21, 6, NTHW_FPGA_REG_TYPE_WO, 0, 1, > cat_kcs1_data_fields }, > + { CAT_LEN_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_len_ctrl_fields }, > + { CAT_LEN_DATA, 9, 39, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cat_len_data_fields }, > + { CAT_RCK_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cat_rck_ctrl_fields }, > + { CAT_RCK_DATA, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 32, > cat_rck_data_fields }, > +}; > + > +static nthw_fpga_field_init_s cpy_packet_reader0_ctrl_fields[] =3D { > + { CPY_PACKET_READER0_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_PACKET_READER0_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_packet_reader0_data_fields[] =3D { > + { CPY_PACKET_READER0_DATA_DYN, 5, 10, 0x0000 }, > + { CPY_PACKET_READER0_DATA_OFS, 10, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer0_ctrl_fields[] =3D { > + { CPY_WRITER0_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER0_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer0_data_fields[] =3D { > + { CPY_WRITER0_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER0_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER0_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER0_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER0_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer0_mask_ctrl_fields[] =3D { > + { CPY_WRITER0_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER0_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer0_mask_data_fields[] =3D { > + { CPY_WRITER0_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer1_ctrl_fields[] =3D { > + { CPY_WRITER1_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER1_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer1_data_fields[] =3D { > + { CPY_WRITER1_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER1_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER1_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER1_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER1_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer1_mask_ctrl_fields[] =3D { > + { CPY_WRITER1_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER1_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer1_mask_data_fields[] =3D { > + { CPY_WRITER1_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer2_ctrl_fields[] =3D { > + { CPY_WRITER2_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER2_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer2_data_fields[] =3D { > + { CPY_WRITER2_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER2_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER2_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER2_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER2_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer2_mask_ctrl_fields[] =3D { > + { CPY_WRITER2_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER2_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer2_mask_data_fields[] =3D { > + { CPY_WRITER2_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer3_ctrl_fields[] =3D { > + { CPY_WRITER3_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER3_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer3_data_fields[] =3D { > + { CPY_WRITER3_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER3_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER3_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER3_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER3_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer3_mask_ctrl_fields[] =3D { > + { CPY_WRITER3_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER3_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer3_mask_data_fields[] =3D { > + { CPY_WRITER3_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer4_ctrl_fields[] =3D { > + { CPY_WRITER4_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER4_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer4_data_fields[] =3D { > + { CPY_WRITER4_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER4_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER4_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER4_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER4_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer4_mask_ctrl_fields[] =3D { > + { CPY_WRITER4_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER4_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer4_mask_data_fields[] =3D { > + { CPY_WRITER4_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer5_ctrl_fields[] =3D { > + { CPY_WRITER5_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER5_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer5_data_fields[] =3D { > + { CPY_WRITER5_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER5_DATA_LEN, 5, 22, 0x0000 }, > + { CPY_WRITER5_DATA_MASK_POINTER, 4, 27, 0x0000 }, { > CPY_WRITER5_DATA_OFS, 14, 3, 0x0000 }, > + { CPY_WRITER5_DATA_READER_SELECT, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer5_mask_ctrl_fields[] =3D { > + { CPY_WRITER5_MASK_CTRL_ADR, 4, 0, 0x0000 }, > + { CPY_WRITER5_MASK_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s cpy_writer5_mask_data_fields[] =3D { > + { CPY_WRITER5_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s cpy_registers[] =3D { > + { > + CPY_PACKET_READER0_CTRL, 24, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_packet_reader0_ctrl_fields > + }, > + { > + CPY_PACKET_READER0_DATA, 25, 15, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_packet_reader0_data_fields > + }, > + { CPY_WRITER0_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer0_ctrl_fields }, > + { CPY_WRITER0_DATA, 1, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer0_data_fields }, > + { > + CPY_WRITER0_MASK_CTRL, 2, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer0_mask_ctrl_fields > + }, > + { > + CPY_WRITER0_MASK_DATA, 3, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer0_mask_data_fields > + }, > + { CPY_WRITER1_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer1_ctrl_fields }, > + { CPY_WRITER1_DATA, 5, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer1_data_fields }, > + { > + CPY_WRITER1_MASK_CTRL, 6, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer1_mask_ctrl_fields > + }, > + { > + CPY_WRITER1_MASK_DATA, 7, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer1_mask_data_fields > + }, > + { CPY_WRITER2_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer2_ctrl_fields }, > + { CPY_WRITER2_DATA, 9, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer2_data_fields }, > + { > + CPY_WRITER2_MASK_CTRL, 10, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer2_mask_ctrl_fields > + }, > + { > + CPY_WRITER2_MASK_DATA, 11, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer2_mask_data_fields > + }, > + { CPY_WRITER3_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer3_ctrl_fields }, > + { CPY_WRITER3_DATA, 13, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer3_data_fields }, > + { > + CPY_WRITER3_MASK_CTRL, 14, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer3_mask_ctrl_fields > + }, > + { > + CPY_WRITER3_MASK_DATA, 15, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer3_mask_data_fields > + }, > + { CPY_WRITER4_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer4_ctrl_fields }, > + { CPY_WRITER4_DATA, 17, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer4_data_fields }, > + { > + CPY_WRITER4_MASK_CTRL, 18, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer4_mask_ctrl_fields > + }, > + { > + CPY_WRITER4_MASK_DATA, 19, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer4_mask_data_fields > + }, > + { CPY_WRITER5_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > cpy_writer5_ctrl_fields }, > + { CPY_WRITER5_DATA, 21, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, > cpy_writer5_data_fields }, > + { > + CPY_WRITER5_MASK_CTRL, 22, 32, > NTHW_FPGA_REG_TYPE_WO, 0, 2, > + cpy_writer5_mask_ctrl_fields > + }, > + { > + CPY_WRITER5_MASK_DATA, 23, 16, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + cpy_writer5_mask_data_fields > + }, > +}; > + > +static nthw_fpga_field_init_s csu_rcp_ctrl_fields[] =3D { > + { CSU_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { CSU_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s csu_rcp_data_fields[] =3D { > + { CSU_RCP_DATA_IL3_CMD, 2, 5, 0x0000 }, > + { CSU_RCP_DATA_IL4_CMD, 3, 7, 0x0000 }, > + { CSU_RCP_DATA_OL3_CMD, 2, 0, 0x0000 }, > + { CSU_RCP_DATA_OL4_CMD, 3, 2, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s csu_registers[] =3D { > + { CSU_RCP_CTRL, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > csu_rcp_ctrl_fields }, > + { CSU_RCP_DATA, 2, 10, NTHW_FPGA_REG_TYPE_WO, 0, 4, > csu_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] =3D { > + { DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_am_data_fields[] =3D { > + { DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { > DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 }, > + { DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_AM_DATA_INT, > 1, 74, 0x0000 }, > + { DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_control_fields[] =3D { > + { DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 > }, > + { DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CONTROL_QE, 1, 17, 0 }, > + { DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, > 13, 5 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] =3D { > + { DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] =3D { > + { DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_DR_DATA_HDR, > 1, 88, 0x0000 }, > + { DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_DR_DATA_PCKED, > 1, 87, 0x0000 }, > + { DBS_RX_DR_DATA_QS, 15, 72, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_idle_fields[] =3D { > + { DBS_RX_IDLE_BUSY, 1, 8, 0 }, > + { DBS_RX_IDLE_IDLE, 1, 0, 0x0000 }, > + { DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_init_fields[] =3D { > + { DBS_RX_INIT_BUSY, 1, 8, 0 }, > + { DBS_RX_INIT_INIT, 1, 0, 0x0000 }, > + { DBS_RX_INIT_QUEUE, 7, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_init_val_fields[] =3D { > + { DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 }, > + { DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_ptr_fields[] =3D { > + { DBS_RX_PTR_PTR, 16, 0, 0x0000 }, > + { DBS_RX_PTR_QUEUE, 7, 16, 0x0000 }, > + { DBS_RX_PTR_VALID, 1, 23, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] =3D { > + { DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] =3D { > + { DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_UW_DATA_HID, > 8, 64, 0x0000 }, > + { DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS_RX_UW_DATA_ISTK, > 1, 92, 0x0000 }, > + { DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { > DBS_RX_UW_DATA_QS, 15, 72, 0x0000 }, > + { DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] =3D { > + { DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_am_data_fields[] =3D { > + { DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { > DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 }, > + { DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_AM_DATA_INT, > 1, 74, 0x0000 }, > + { DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_control_fields[] =3D { > + { DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 > }, > + { DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CONTROL_QE, 1, 17, 0 }, > + { DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, > 13, 8 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] =3D { > + { DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] =3D { > + { DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_DR_DATA_HDR, > 1, 88, 0x0000 }, > + { DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_DR_DATA_PCKED, > 1, 87, 0x0000 }, > + { DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DBS_TX_DR_DATA_QS, > 15, 72, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_idle_fields[] =3D { > + { DBS_TX_IDLE_BUSY, 1, 8, 0 }, > + { DBS_TX_IDLE_IDLE, 1, 0, 0x0000 }, > + { DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_init_fields[] =3D { > + { DBS_TX_INIT_BUSY, 1, 8, 0 }, > + { DBS_TX_INIT_INIT, 1, 0, 0x0000 }, > + { DBS_TX_INIT_QUEUE, 7, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_init_val_fields[] =3D { > + { DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 }, > + { DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_ptr_fields[] =3D { > + { DBS_TX_PTR_PTR, 16, 0, 0x0000 }, > + { DBS_TX_PTR_QUEUE, 7, 16, 0x0000 }, > + { DBS_TX_PTR_VALID, 1, 23, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] =3D { > + { DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 }, > + { DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] =3D { > + { DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 }, > + { DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 }, > + { DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] =3D { > + { DBS_TX_QOS_RATE_DIV, 19, 16, 2 }, > + { DBS_TX_QOS_RATE_MUL, 16, 0, 1 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] =3D { > + { DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] =3D { > + { DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] =3D { > + { DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 }, > + { DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] =3D { > + { DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_UW_DATA_HID, > 8, 64, 0x0000 }, > + { DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS_TX_UW_DATA_INT, > 1, 88, 0x0000 }, > + { DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { > DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 }, > + { DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS_TX_UW_DATA_VEC, > 3, 89, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s dbs_registers[] =3D { > + { DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_rx_am_ctrl_fields }, > + { DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, > dbs_rx_am_data_fields }, > + { DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_RW, 43008, 6, > dbs_rx_control_fields }, > + { DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_rx_dr_ctrl_fields }, > + { DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE_WO, 0, 5, > dbs_rx_dr_data_fields }, > + { DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_rx_idle_fields }, > + { DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_rx_init_fields }, > + { DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_rx_init_val_fields }, > + { DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_rx_ptr_fields }, > + { DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_rx_uw_ctrl_fields }, > + { DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE_WO, 0, 7, > dbs_rx_uw_data_fields }, > + { DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_am_ctrl_fields }, > + { DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, > dbs_tx_am_data_fields }, > + { DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_RW, 66816, 6, > dbs_tx_control_fields }, > + { DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_dr_ctrl_fields }, > + { DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE_WO, 0, 6, > dbs_tx_dr_data_fields }, > + { DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_tx_idle_fields }, > + { DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_tx_init_fields }, > + { DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_init_val_fields }, > + { DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > dbs_tx_ptr_fields }, > + { DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_qos_ctrl_fields }, > + { DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYPE_WO, 0, 3, > dbs_tx_qos_data_fields }, > + { DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYPE_RW, 131073, > 2, dbs_tx_qos_rate_fields }, > + { DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_qp_ctrl_fields }, > + { DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, > dbs_tx_qp_data_fields }, > + { DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > dbs_tx_uw_ctrl_fields }, > + { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, > dbs_tx_uw_data_fields }, > +}; > + > +static nthw_fpga_field_init_s flm_buf_ctrl_fields[] =3D { > + { FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 }, > + { FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 }, > + { FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_control_fields[] =3D { > + { FLM_CONTROL_CRCRD, 1, 12, 0x0000 }, { FLM_CONTROL_CRCWR, > 1, 11, 0x0000 }, > + { FLM_CONTROL_EAB, 5, 18, 0 }, { FLM_CONTROL_ENABLE, 1, 0, 0 }, > + { FLM_CONTROL_INIT, 1, 1, 0x0000 }, { FLM_CONTROL_LDS, 1, 2, > 0x0000 }, > + { FLM_CONTROL_LFS, 1, 3, 0x0000 }, { FLM_CONTROL_LIS, 1, 4, > 0x0000 }, > + { FLM_CONTROL_PDS, 1, 9, 0x0000 }, { FLM_CONTROL_PIS, 1, 10, > 0x0000 }, > + { FLM_CONTROL_RBL, 4, 13, 0 }, { FLM_CONTROL_RDS, 1, 7, 0x0000 > }, > + { FLM_CONTROL_RIS, 1, 8, 0x0000 }, { > FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 }, > + { FLM_CONTROL_UDS, 1, 5, 0x0000 }, { FLM_CONTROL_UIS, 1, 6, > 0x0000 }, > + { FLM_CONTROL_WPD, 1, 17, 0 }, > +}; > + > +static nthw_fpga_field_init_s flm_inf_data_fields[] =3D { > + { FLM_INF_DATA_BYTES, 64, 0, 0x0000 }, { FLM_INF_DATA_CAUSE, 3, > 264, 0x0000 }, > + { FLM_INF_DATA_EOR, 1, 287, 0x0000 }, { FLM_INF_DATA_ID, 72, > 192, 0x0000 }, > + { FLM_INF_DATA_PACKETS, 64, 64, 0x0000 }, { FLM_INF_DATA_TS, > 64, 128, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_load_aps_fields[] =3D { > + { FLM_LOAD_APS_APS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_load_bin_fields[] =3D { > + { FLM_LOAD_BIN_BIN, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_load_lps_fields[] =3D { > + { FLM_LOAD_LPS_LPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_lrn_data_fields[] =3D { > + { FLM_LRN_DATA_ADJ, 32, 480, 0x0000 }, { FLM_LRN_DATA_COLOR, > 32, 448, 0x0000 }, > + { FLM_LRN_DATA_DSCP, 6, 734, 0x0000 }, { FLM_LRN_DATA_ENT, 1, > 729, 0x0000 }, > + { FLM_LRN_DATA_EOR, 1, 767, 0x0000 }, { FLM_LRN_DATA_FILL, 12, > 584, 0x0000 }, > + { FLM_LRN_DATA_FT, 4, 596, 0x0000 }, { FLM_LRN_DATA_FT_MBR, 4, > 600, 0x0000 }, > + { FLM_LRN_DATA_FT_MISS, 4, 604, 0x0000 }, { FLM_LRN_DATA_ID, > 72, 512, 0x0000 }, > + { FLM_LRN_DATA_KID, 8, 328, 0x0000 }, { FLM_LRN_DATA_MBR_ID1, > 28, 608, 0x0000 }, > + { FLM_LRN_DATA_MBR_ID2, 28, 636, 0x0000 }, { > FLM_LRN_DATA_MBR_ID3, 28, 664, 0x0000 }, > + { FLM_LRN_DATA_MBR_ID4, 28, 692, 0x0000 }, { > FLM_LRN_DATA_NAT_EN, 1, 747, 0x0000 }, > + { FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 }, { > FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 }, > + { FLM_LRN_DATA_NOFI, 1, 752, 0x0000 }, { FLM_LRN_DATA_OP, 4, > 730, 0x0000 }, > + { FLM_LRN_DATA_PRIO, 2, 727, 0x0000 }, { FLM_LRN_DATA_PROT, 8, > 320, 0x0000 }, > + { FLM_LRN_DATA_QFI, 6, 740, 0x0000 }, { FLM_LRN_DATA_QW0, > 128, 192, 0x0000 }, > + { FLM_LRN_DATA_QW4, 128, 64, 0x0000 }, { FLM_LRN_DATA_RATE, > 16, 416, 0x0000 }, > + { FLM_LRN_DATA_RQI, 1, 746, 0x0000 }, { > FLM_LRN_DATA_SCRUB_PROF, 4, 748, 0x0000 }, > + { FLM_LRN_DATA_SIZE, 16, 432, 0x0000 }, { > FLM_LRN_DATA_STAT_PROF, 4, 723, 0x0000 }, > + { FLM_LRN_DATA_SW8, 32, 32, 0x0000 }, { FLM_LRN_DATA_SW9, 32, > 0, 0x0000 }, > + { FLM_LRN_DATA_TEID, 32, 368, 0x0000 }, { > FLM_LRN_DATA_VOL_IDX, 3, 720, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_prio_fields[] =3D { > + { FLM_PRIO_FT0, 4, 4, 1 }, { FLM_PRIO_FT1, 4, 12, 1 }, { > FLM_PRIO_FT2, 4, 20, 1 }, > + { FLM_PRIO_FT3, 4, 28, 1 }, { FLM_PRIO_LIMIT0, 4, 0, 0 }, { > FLM_PRIO_LIMIT1, 4, 8, 0 }, > + { FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LIMIT3, 4, 24, 0 }, > +}; > + > +static nthw_fpga_field_init_s flm_pst_ctrl_fields[] =3D { > + { FLM_PST_CTRL_ADR, 4, 0, 0x0000 }, > + { FLM_PST_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_pst_data_fields[] =3D { > + { FLM_PST_DATA_BP, 5, 0, 0x0000 }, > + { FLM_PST_DATA_PP, 5, 5, 0x0000 }, > + { FLM_PST_DATA_TP, 5, 10, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_rcp_ctrl_fields[] =3D { > + { FLM_RCP_CTRL_ADR, 5, 0, 0x0000 }, > + { FLM_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_rcp_data_fields[] =3D { > + { FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x0000 }, > + { FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 }, > + { FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 }, > + { FLM_RCP_DATA_IPN, 1, 386, 0x0000 }, > + { FLM_RCP_DATA_KID, 8, 377, 0x0000 }, > + { FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 }, > + { FLM_RCP_DATA_MASK, 320, 57, 0x0000 }, > + { FLM_RCP_DATA_OPN, 1, 385, 0x0000 }, > + { FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 }, > + { FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 }, > + { FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 }, > + { FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 }, > + { FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 }, > + { FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 }, > + { FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 }, > + { FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 }, > + { FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 }, > + { FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 }, > + { FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_scan_fields[] =3D { > + { FLM_SCAN_I, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s flm_scrub_ctrl_fields[] =3D { > + { FLM_SCRUB_CTRL_ADR, 4, 0, 0x0000 }, > + { FLM_SCRUB_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_scrub_data_fields[] =3D { > + { FLM_SCRUB_DATA_T, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s flm_status_fields[] =3D { > + { FLM_STATUS_CALIBDONE, 1, 0, 0x0000 }, { FLM_STATUS_CRCERR, 1, > 5, 0x0000 }, > + { FLM_STATUS_CRITICAL, 1, 3, 0x0000 }, { FLM_STATUS_EFT_BP, 1, 6, > 0x0000 }, > + { FLM_STATUS_IDLE, 1, 2, 0x0000 }, { FLM_STATUS_INITDONE, 1, 1, > 0x0000 }, > + { FLM_STATUS_PANIC, 1, 4, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_aul_done_fields[] =3D { > + { FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_aul_fail_fields[] =3D { > + { FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_aul_ignore_fields[] =3D { > + { FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_csh_hit_fields[] =3D { > + { FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_csh_miss_fields[] =3D { > + { FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_csh_unh_fields[] =3D { > + { FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_cuc_move_fields[] =3D { > + { FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_cuc_start_fields[] =3D { > + { FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_flows_fields[] =3D { > + { FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_inf_done_fields[] =3D { > + { FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_inf_skip_fields[] =3D { > + { FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_lrn_done_fields[] =3D { > + { FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_lrn_fail_fields[] =3D { > + { FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_lrn_ignore_fields[] =3D { > + { FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_pck_dis_fields[] =3D { > + { FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_pck_hit_fields[] =3D { > + { FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_pck_miss_fields[] =3D { > + { FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_pck_unh_fields[] =3D { > + { FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_prb_done_fields[] =3D { > + { FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_prb_ignore_fields[] =3D { > + { FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_rel_done_fields[] =3D { > + { FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_rel_ignore_fields[] =3D { > + { FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_sta_done_fields[] =3D { > + { FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_tul_done_fields[] =3D { > + { FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_unl_done_fields[] =3D { > + { FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_stat_unl_ignore_fields[] =3D { > + { FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s flm_sta_data_fields[] =3D { > + { FLM_STA_DATA_EOR, 1, 95, 0x0000 }, { FLM_STA_DATA_ID, 72, 0, > 0x0000 }, > + { FLM_STA_DATA_LDS, 1, 72, 0x0000 }, { FLM_STA_DATA_LFS, 1, 73, > 0x0000 }, > + { FLM_STA_DATA_LIS, 1, 74, 0x0000 }, { FLM_STA_DATA_PDS, 1, 79, > 0x0000 }, > + { FLM_STA_DATA_PIS, 1, 80, 0x0000 }, { FLM_STA_DATA_RDS, 1, 77, > 0x0000 }, > + { FLM_STA_DATA_RIS, 1, 78, 0x0000 }, { FLM_STA_DATA_UDS, 1, 75, > 0x0000 }, > + { FLM_STA_DATA_UIS, 1, 76, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s flm_registers[] =3D { > + { FLM_BUF_CTRL, 14, 48, NTHW_FPGA_REG_TYPE_RW, 0, 3, > flm_buf_ctrl_fields }, > + { FLM_CONTROL, 0, 28, NTHW_FPGA_REG_TYPE_MIXED, 134217728, > 17, flm_control_fields }, > + { FLM_INF_DATA, 16, 288, NTHW_FPGA_REG_TYPE_RO, 0, 6, > flm_inf_data_fields }, > + { FLM_LOAD_APS, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_load_aps_fields }, > + { FLM_LOAD_BIN, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > flm_load_bin_fields }, > + { FLM_LOAD_LPS, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_load_lps_fields }, > + { FLM_LRN_DATA, 15, 768, NTHW_FPGA_REG_TYPE_WO, 0, 34, > flm_lrn_data_fields }, > + { FLM_PRIO, 6, 32, NTHW_FPGA_REG_TYPE_WO, 269488144, 8, > flm_prio_fields }, > + { FLM_PST_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > flm_pst_ctrl_fields }, > + { FLM_PST_DATA, 13, 15, NTHW_FPGA_REG_TYPE_WO, 0, 3, > flm_pst_data_fields }, > + { FLM_RCP_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > flm_rcp_ctrl_fields }, > + { FLM_RCP_DATA, 9, 403, NTHW_FPGA_REG_TYPE_WO, 0, 19, > flm_rcp_data_fields }, > + { FLM_SCAN, 2, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, > flm_scan_fields }, > + { FLM_SCRUB_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > flm_scrub_ctrl_fields }, > + { FLM_SCRUB_DATA, 11, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > flm_scrub_data_fields }, > + { FLM_STATUS, 1, 12, NTHW_FPGA_REG_TYPE_MIXED, 0, 7, > flm_status_fields }, > + { FLM_STAT_AUL_DONE, 41, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_aul_done_fields }, > + { FLM_STAT_AUL_FAIL, 43, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_aul_fail_fields }, > + { FLM_STAT_AUL_IGNORE, 42, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_aul_ignore_fields }, > + { FLM_STAT_CSH_HIT, 52, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_csh_hit_fields }, > + { FLM_STAT_CSH_MISS, 53, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_csh_miss_fields }, > + { FLM_STAT_CSH_UNH, 54, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_csh_unh_fields }, > + { FLM_STAT_CUC_MOVE, 56, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_cuc_move_fields }, > + { FLM_STAT_CUC_START, 55, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_cuc_start_fields }, > + { FLM_STAT_FLOWS, 18, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_flows_fields }, > + { FLM_STAT_INF_DONE, 46, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_inf_done_fields }, > + { FLM_STAT_INF_SKIP, 47, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_inf_skip_fields }, > + { FLM_STAT_LRN_DONE, 32, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_lrn_done_fields }, > + { FLM_STAT_LRN_FAIL, 34, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_lrn_fail_fields }, > + { FLM_STAT_LRN_IGNORE, 33, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_lrn_ignore_fields }, > + { FLM_STAT_PCK_DIS, 51, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_pck_dis_fields }, > + { FLM_STAT_PCK_HIT, 48, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_pck_hit_fields }, > + { FLM_STAT_PCK_MISS, 49, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_pck_miss_fields }, > + { FLM_STAT_PCK_UNH, 50, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_pck_unh_fields }, > + { FLM_STAT_PRB_DONE, 39, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_prb_done_fields }, > + { FLM_STAT_PRB_IGNORE, 40, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_prb_ignore_fields }, > + { FLM_STAT_REL_DONE, 37, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_rel_done_fields }, > + { FLM_STAT_REL_IGNORE, 38, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_rel_ignore_fields }, > + { FLM_STAT_STA_DONE, 45, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_sta_done_fields }, > + { FLM_STAT_TUL_DONE, 44, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_tul_done_fields }, > + { FLM_STAT_UNL_DONE, 35, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_unl_done_fields }, > + { FLM_STAT_UNL_IGNORE, 36, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > flm_stat_unl_ignore_fields }, > + { FLM_STA_DATA, 17, 96, NTHW_FPGA_REG_TYPE_RO, 0, 11, > flm_sta_data_fields }, > +}; > + > +static nthw_fpga_field_init_s gfg_burstsize0_fields[] =3D { > + { GFG_BURSTSIZE0_VAL, 24, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_burstsize1_fields[] =3D { > + { GFG_BURSTSIZE1_VAL, 24, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_ctrl0_fields[] =3D { > + { GFG_CTRL0_ENABLE, 1, 0, 0 }, > + { GFG_CTRL0_MODE, 3, 1, 0 }, > + { GFG_CTRL0_PRBS_EN, 1, 4, 0 }, > + { GFG_CTRL0_SIZE, 14, 16, 64 }, > +}; > + > +static nthw_fpga_field_init_s gfg_ctrl1_fields[] =3D { > + { GFG_CTRL1_ENABLE, 1, 0, 0 }, > + { GFG_CTRL1_MODE, 3, 1, 0 }, > + { GFG_CTRL1_PRBS_EN, 1, 4, 0 }, > + { GFG_CTRL1_SIZE, 14, 16, 64 }, > +}; > + > +static nthw_fpga_field_init_s gfg_run0_fields[] =3D { > + { GFG_RUN0_RUN, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_run1_fields[] =3D { > + { GFG_RUN1_RUN, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_sizemask0_fields[] =3D { > + { GFG_SIZEMASK0_VAL, 14, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_sizemask1_fields[] =3D { > + { GFG_SIZEMASK1_VAL, 14, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_streamid0_fields[] =3D { > + { GFG_STREAMID0_VAL, 8, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gfg_streamid1_fields[] =3D { > + { GFG_STREAMID1_VAL, 8, 0, 1 }, > +}; > + > +static nthw_fpga_register_init_s gfg_registers[] =3D { > + { GFG_BURSTSIZE0, 3, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gfg_burstsize0_fields }, > + { GFG_BURSTSIZE1, 8, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gfg_burstsize1_fields }, > + { GFG_CTRL0, 0, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, > gfg_ctrl0_fields }, > + { GFG_CTRL1, 5, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, > gfg_ctrl1_fields }, > + { GFG_RUN0, 1, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run0_fields > }, > + { GFG_RUN1, 6, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run1_fields > }, > + { GFG_SIZEMASK0, 4, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gfg_sizemask0_fields }, > + { GFG_SIZEMASK1, 9, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gfg_sizemask1_fields }, > + { GFG_STREAMID0, 2, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gfg_streamid0_fields }, > + { GFG_STREAMID1, 7, 8, NTHW_FPGA_REG_TYPE_WO, 1, 1, > gfg_streamid1_fields }, > +}; > + > +static nthw_fpga_field_init_s gmf_ctrl_fields[] =3D { > + { GMF_CTRL_ENABLE, 1, 0, 0 }, > + { GMF_CTRL_FCS_ALWAYS, 1, 1, 0 }, > + { GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 }, > + { GMF_CTRL_IFG_ENABLE, 1, 2, 0 }, > + { GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 }, > + { GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 }, > + { GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 }, > + { GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 }, > + { GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 }, > + { GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_debug_lane_marker_fields[] =3D { > + { GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 }, > +}; > + > +static nthw_fpga_field_init_s gmf_ifg_max_adjust_slack_fields[] =3D { > + { GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_fields[] =3D { > + { GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_adjust_fields[] = =3D { > + { GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_ifg_tx_now_on_ts_fields[] =3D { > + { GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_speed_fields[] =3D { > + { GMF_SPEED_IFG_SPEED, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_stat_data_buffer_fields[] =3D { > + { GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s gmf_stat_max_delayed_pkt_fields[] =3D { > + { GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_stat_next_pkt_fields[] =3D { > + { GMF_STAT_NEXT_PKT_NS, 64, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_stat_sticky_fields[] =3D { > + { GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 }, > + { GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s gmf_ts_inject_fields[] =3D { > + { GMF_TS_INJECT_OFFSET, 14, 0, 0 }, > + { GMF_TS_INJECT_POS, 2, 14, 0 }, > +}; > + > +static nthw_fpga_register_init_s gmf_registers[] =3D { > + { GMF_CTRL, 0, 10, NTHW_FPGA_REG_TYPE_WO, 0, 10, > gmf_ctrl_fields }, > + { > + GMF_DEBUG_LANE_MARKER, 7, 16, > NTHW_FPGA_REG_TYPE_WO, 16384, 1, > + gmf_debug_lane_marker_fields > + }, > + { > + GMF_IFG_MAX_ADJUST_SLACK, 4, 64, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + gmf_ifg_max_adjust_slack_fields > + }, > + { > + GMF_IFG_SET_CLOCK_DELTA, 2, 64, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + gmf_ifg_set_clock_delta_fields > + }, > + { > + GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, > NTHW_FPGA_REG_TYPE_WO, 0, 1, > + gmf_ifg_set_clock_delta_adjust_fields > + }, > + { GMF_IFG_TX_NOW_ON_TS, 5, 64, NTHW_FPGA_REG_TYPE_WO, 0, > 1, gmf_ifg_tx_now_on_ts_fields }, > + { GMF_SPEED, 1, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, > gmf_speed_fields }, > + { GMF_STAT_DATA_BUFFER, 9, 15, NTHW_FPGA_REG_TYPE_RO, 0, 1, > gmf_stat_data_buffer_fields }, > + { > + GMF_STAT_MAX_DELAYED_PKT, 11, 64, > NTHW_FPGA_REG_TYPE_RC1, 0, 1, > + gmf_stat_max_delayed_pkt_fields > + }, > + { GMF_STAT_NEXT_PKT, 10, 64, NTHW_FPGA_REG_TYPE_RO, 0, 1, > gmf_stat_next_pkt_fields }, > + { GMF_STAT_STICKY, 8, 2, NTHW_FPGA_REG_TYPE_RC1, 0, 2, > gmf_stat_sticky_fields }, > + { GMF_TS_INJECT, 6, 16, NTHW_FPGA_REG_TYPE_WO, 0, 2, > gmf_ts_inject_fields }, > +}; > + > +static nthw_fpga_field_init_s gpio_phy_cfg_fields[] =3D { > + { GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 }, { > GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 }, > + { GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 }, { > GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 }, > + { GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 }, { > GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 }, > + { GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 }, { > GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 }, > + { GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 }, { > GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 }, > +}; > + > +static nthw_fpga_field_init_s gpio_phy_gpio_fields[] =3D { > + { GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 }, { > GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 }, > + { GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 }, { > GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 }, > + { GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 }, { > GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 }, > + { GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 }, { > GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 }, > + { GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 }, { > GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 }, > +}; > + > +static nthw_fpga_register_init_s gpio_phy_registers[] =3D { > + { GPIO_PHY_CFG, 0, 10, NTHW_FPGA_REG_TYPE_RW, 170, 10, > gpio_phy_cfg_fields }, > + { GPIO_PHY_GPIO, 1, 10, NTHW_FPGA_REG_TYPE_RW, 17, 10, > gpio_phy_gpio_fields }, > +}; > + > +static nthw_fpga_field_init_s hfu_rcp_ctrl_fields[] =3D { > + { HFU_RCP_CTRL_ADR, 6, 0, 0x0000 }, > + { HFU_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s hfu_rcp_data_fields[] =3D { > + { HFU_RCP_DATA_LEN_A_ADD_DYN, 5, 15, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_ADD_OFS, 8, 20, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_OL4LEN, 1, 1, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_POS_DYN, 5, 2, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_POS_OFS, 8, 7, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_SUB_DYN, 5, 28, 0x0000 }, > + { HFU_RCP_DATA_LEN_A_WR, 1, 0, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_ADD_DYN, 5, 47, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_ADD_OFS, 8, 52, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_POS_DYN, 5, 34, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_POS_OFS, 8, 39, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_SUB_DYN, 5, 60, 0x0000 }, > + { HFU_RCP_DATA_LEN_B_WR, 1, 33, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_ADD_DYN, 5, 79, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_ADD_OFS, 8, 84, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_POS_DYN, 5, 66, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_POS_OFS, 8, 71, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_SUB_DYN, 5, 92, 0x0000 }, > + { HFU_RCP_DATA_LEN_C_WR, 1, 65, 0x0000 }, > + { HFU_RCP_DATA_TTL_POS_DYN, 5, 98, 0x0000 }, > + { HFU_RCP_DATA_TTL_POS_OFS, 8, 103, 0x0000 }, > + { HFU_RCP_DATA_TTL_WR, 1, 97, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s hfu_registers[] =3D { > + { HFU_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > hfu_rcp_ctrl_fields }, > + { HFU_RCP_DATA, 1, 111, NTHW_FPGA_REG_TYPE_WO, 0, 22, > hfu_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s hif_build_time_fields[] =3D { > + { HIF_BUILD_TIME_TIME, 32, 0, 1713859545 }, > +}; > + > +static nthw_fpga_field_init_s hif_config_fields[] =3D { > + { HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 }, > + { HIF_CONFIG_MAX_READ, 3, 3, 0x0000 }, > + { HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s hif_control_fields[] =3D { > + { HIF_CONTROL_BLESSED, 8, 4, 0 }, > + { HIF_CONTROL_FSR, 1, 12, 1 }, > + { HIF_CONTROL_WRAW, 4, 0, 1 }, > +}; > + > +static nthw_fpga_field_init_s hif_prod_id_ex_fields[] =3D { > + { HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 }, > + { HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 }, > + { HIF_PROD_ID_EX_RESERVED, 23, 8, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] =3D { > + { HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 }, > + { HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 }, > + { HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 }, > +}; > + > +static nthw_fpga_field_init_s hif_prod_id_msb_fields[] =3D { > + { HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 }, > + { HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 }, > +}; > + > +static nthw_fpga_field_init_s hif_sample_time_fields[] =3D { > + { HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s hif_status_fields[] =3D { > + { HIF_STATUS_RD_ERR, 1, 9, 0 }, > + { HIF_STATUS_TAGS_IN_USE, 8, 0, 0 }, > + { HIF_STATUS_WR_ERR, 1, 8, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_stat_ctrl_fields[] =3D { > + { HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 }, > + { HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_stat_refclk_fields[] =3D { > + { HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_stat_rx_fields[] =3D { > + { HIF_STAT_RX_COUNTER, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_stat_tx_fields[] =3D { > + { HIF_STAT_TX_COUNTER, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s hif_test0_fields[] =3D { > + { HIF_TEST0_DATA, 32, 0, 287454020 }, > +}; > + > +static nthw_fpga_field_init_s hif_test1_fields[] =3D { > + { HIF_TEST1_DATA, 32, 0, 2864434397 }, > +}; > + > +static nthw_fpga_field_init_s hif_uuid0_fields[] =3D { > + { HIF_UUID0_UUID0, 32, 0, 1237800326 }, > +}; > + > +static nthw_fpga_field_init_s hif_uuid1_fields[] =3D { > + { HIF_UUID1_UUID1, 32, 0, 3057550372 }, > +}; > + > +static nthw_fpga_field_init_s hif_uuid2_fields[] =3D { > + { HIF_UUID2_UUID2, 32, 0, 2445752330 }, > +}; > + > +static nthw_fpga_field_init_s hif_uuid3_fields[] =3D { > + { HIF_UUID3_UUID3, 32, 0, 1864147557 }, > +}; > + > +static nthw_fpga_register_init_s hif_registers[] =3D { > + { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, > 1713859545, 1, hif_build_time_fields }, > + { HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, 0, 3, > hif_config_fields }, > + { HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MIXED, 4097, 3, > hif_control_fields }, > + { HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYPE_RO, 1, 3, > hif_prod_id_ex_fields }, > + { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734887, > 3, hif_prod_id_lsb_fields }, > + { HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE_RO, 200, 2, > hif_prod_id_msb_fields }, > + { HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, > hif_sample_time_fields }, > + { HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > hif_status_fields }, > + { HIF_STAT_CTRL, 64, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, > hif_stat_ctrl_fields }, > + { HIF_STAT_REFCLK, 72, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > hif_stat_refclk_fields }, > + { HIF_STAT_RX, 88, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > hif_stat_rx_fields }, > + { HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > hif_stat_tx_fields }, > + { HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, 287454020, 1, > hif_test0_fields }, > + { HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, 2864434397, 1, > hif_test1_fields }, > + { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1237800326, 1, > hif_uuid0_fields }, > + { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 3057550372, 1, > hif_uuid1_fields }, > + { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 2445752330, 1, > hif_uuid2_fields }, > + { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 1864147557, 1, > hif_uuid3_fields }, > +}; > + > +static nthw_fpga_field_init_s hsh_rcp_ctrl_fields[] =3D { > + { HSH_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { HSH_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s hsh_rcp_data_fields[] =3D { > + { HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x0000 }, > + { HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 }, > + { HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 }, > + { HSH_RCP_DATA_K, 320, 422, 0x0000 }, > + { HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 }, > + { HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 }, > + { HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 }, > + { HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 }, > + { HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 }, > + { HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 }, > + { HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 }, > + { HSH_RCP_DATA_SEED, 32, 382, 0x0000 }, > + { HSH_RCP_DATA_SORT, 2, 4, 0x0000 }, > + { HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 }, > + { HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 }, > + { HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 }, > + { HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 }, > + { HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 }, > + { HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 }, > + { HSH_RCP_DATA_W9_P, 1, 60, 0x0000 }, > + { HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 }, > + { HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 }, > + { HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s hsh_registers[] =3D { > + { HSH_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > hsh_rcp_ctrl_fields }, > + { HSH_RCP_DATA, 1, 743, NTHW_FPGA_REG_TYPE_WO, 0, 23, > hsh_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s ifr_counters_ctrl_fields[] =3D { > + { IFR_COUNTERS_CTRL_ADR, 4, 0, 0x0000 }, > + { IFR_COUNTERS_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ifr_counters_data_fields[] =3D { > + { IFR_COUNTERS_DATA_DROP, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ifr_df_buf_ctrl_fields[] =3D { > + { IFR_DF_BUF_CTRL_AVAILABLE, 11, 0, 0x0000 }, > + { IFR_DF_BUF_CTRL_MTU_PROFILE, 16, 11, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ifr_df_buf_data_fields[] =3D { > + { IFR_DF_BUF_DATA_FIFO_DAT, 128, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ifr_rcp_ctrl_fields[] =3D { > + { IFR_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { IFR_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ifr_rcp_data_fields[] =3D { > + { IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0x0000 }, { > IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 }, > + { IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x0000 }, { > IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 }, > + { IFR_RCP_DATA_MTU, 14, 2, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s ifr_registers[] =3D { > + { IFR_COUNTERS_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > ifr_counters_ctrl_fields }, > + { IFR_COUNTERS_DATA, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > ifr_counters_data_fields }, > + { IFR_DF_BUF_CTRL, 2, 27, NTHW_FPGA_REG_TYPE_RO, 0, 2, > ifr_df_buf_ctrl_fields }, > + { IFR_DF_BUF_DATA, 3, 128, NTHW_FPGA_REG_TYPE_RO, 0, 1, > ifr_df_buf_data_fields }, > + { IFR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > ifr_rcp_ctrl_fields }, > + { IFR_RCP_DATA, 1, 18, NTHW_FPGA_REG_TYPE_WO, 0, 5, > ifr_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s iic_adr_fields[] =3D { > + { IIC_ADR_SLV_ADR, 7, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_cr_fields[] =3D { > + { IIC_CR_EN, 1, 0, 0 }, { IIC_CR_GC_EN, 1, 6, 0 }, { IIC_CR_MSMS, 1= , 2, > 0 }, > + { IIC_CR_RST, 1, 7, 0 }, { IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, = 3, 0 }, > + { IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_dgie_fields[] =3D { > + { IIC_DGIE_GIE, 1, 31, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_gpo_fields[] =3D { > + { IIC_GPO_GPO_VAL, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_ier_fields[] =3D { > + { IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 }, { IIC_IER_INT= 2, 1, 2, > 0 }, > + { IIC_IER_INT3, 1, 3, 0 }, { IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT= 5, 1, 5, > 0 }, > + { IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_isr_fields[] =3D { > + { IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 }, { IIC_ISR_INT= 2, 1, 2, > 0 }, > + { IIC_ISR_INT3, 1, 3, 0 }, { IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT= 5, 1, 5, > 0 }, > + { IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_rx_fifo_fields[] =3D { > + { IIC_RX_FIFO_RXDATA, 8, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_rx_fifo_ocy_fields[] =3D { > + { IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_rx_fifo_pirq_fields[] =3D { > + { IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_softr_fields[] =3D { > + { IIC_SOFTR_RKEY, 4, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s iic_sr_fields[] =3D { > + { IIC_SR_AAS, 1, 1, 0 }, { IIC_SR_ABGC, 1, 0, 0 }, { IIC_SR_BB, 1, = 2, 0 }, > + { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 }, { IIC_SR_RXFIFO_FULL, 1, 5, 0 }, = { > IIC_SR_SRW, 1, 3, 0 }, > + { IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tbuf_fields[] =3D { > + { IIC_TBUF_TBUF_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_ten_adr_fields[] =3D { > + { IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_thddat_fields[] =3D { > + { IIC_THDDAT_THDDAT_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_thdsta_fields[] =3D { > + { IIC_THDSTA_THDSTA_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_thigh_fields[] =3D { > + { IIC_THIGH_THIGH_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tlow_fields[] =3D { > + { IIC_TLOW_TLOW_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tsudat_fields[] =3D { > + { IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tsusta_fields[] =3D { > + { IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tsusto_fields[] =3D { > + { IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tx_fifo_fields[] =3D { > + { IIC_TX_FIFO_START, 1, 8, 0 }, > + { IIC_TX_FIFO_STOP, 1, 9, 0 }, > + { IIC_TX_FIFO_TXDATA, 8, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s iic_tx_fifo_ocy_fields[] =3D { > + { IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s iic_registers[] =3D { > + { IIC_ADR, 68, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_adr_fields }, > + { IIC_CR, 64, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_cr_fields }, > + { IIC_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_dgie_fields }, > + { IIC_GPO, 73, 1, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_gpo_fields }, > + { IIC_IER, 10, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_ier_fields }, > + { IIC_ISR, 8, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_isr_fields }, > + { IIC_RX_FIFO, 67, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, > iic_rx_fifo_fields }, > + { IIC_RX_FIFO_OCY, 70, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, > iic_rx_fifo_ocy_fields }, > + { IIC_RX_FIFO_PIRQ, 72, 4, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_rx_fifo_pirq_fields }, > + { IIC_SOFTR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, iic_softr_fields > }, > + { IIC_SR, 65, 8, NTHW_FPGA_REG_TYPE_RO, 192, 8, iic_sr_fields }, > + { IIC_TBUF, 78, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tbuf_fields }, > + { IIC_TEN_ADR, 71, 3, NTHW_FPGA_REG_TYPE_RO, 0, 1, > iic_ten_adr_fields }, > + { IIC_THDDAT, 81, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_thddat_fields }, > + { IIC_THDSTA, 76, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_thdsta_fields }, > + { IIC_THIGH, 79, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thigh_fields > }, > + { IIC_TLOW, 80, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tlow_fields > }, > + { IIC_TSUDAT, 77, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_tsudat_fields }, > + { IIC_TSUSTA, 74, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_tsusta_fields }, > + { IIC_TSUSTO, 75, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > iic_tsusto_fields }, > + { IIC_TX_FIFO, 66, 10, NTHW_FPGA_REG_TYPE_WO, 0, 3, > iic_tx_fifo_fields }, > + { IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, > iic_tx_fifo_ocy_fields }, > +}; > + > +static nthw_fpga_field_init_s ins_rcp_ctrl_fields[] =3D { > + { INS_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { INS_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s ins_rcp_data_fields[] =3D { > + { INS_RCP_DATA_DYN, 5, 0, 0x0000 }, > + { INS_RCP_DATA_LEN, 8, 15, 0x0000 }, > + { INS_RCP_DATA_OFS, 10, 5, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s ins_registers[] =3D { > + { INS_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > ins_rcp_ctrl_fields }, > + { INS_RCP_DATA, 1, 23, NTHW_FPGA_REG_TYPE_WO, 0, 3, > ins_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s km_cam_ctrl_fields[] =3D { > + { KM_CAM_CTRL_ADR, 13, 0, 0x0000 }, > + { KM_CAM_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_cam_data_fields[] =3D { > + { KM_CAM_DATA_FT0, 4, 192, 0x0000 }, { KM_CAM_DATA_FT1, 4, > 196, 0x0000 }, > + { KM_CAM_DATA_FT2, 4, 200, 0x0000 }, { KM_CAM_DATA_FT3, 4, > 204, 0x0000 }, > + { KM_CAM_DATA_FT4, 4, 208, 0x0000 }, { KM_CAM_DATA_FT5, 4, > 212, 0x0000 }, > + { KM_CAM_DATA_W0, 32, 0, 0x0000 }, { KM_CAM_DATA_W1, 32, 32, > 0x0000 }, > + { KM_CAM_DATA_W2, 32, 64, 0x0000 }, { KM_CAM_DATA_W3, 32, > 96, 0x0000 }, > + { KM_CAM_DATA_W4, 32, 128, 0x0000 }, { KM_CAM_DATA_W5, 32, > 160, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_rcp_ctrl_fields[] =3D { > + { KM_RCP_CTRL_ADR, 5, 0, 0x0000 }, > + { KM_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_rcp_data_fields[] =3D { > + { KM_RCP_DATA_BANK_A, 12, 694, 0x0000 }, { > KM_RCP_DATA_BANK_B, 12, 706, 0x0000 }, > + { KM_RCP_DATA_DUAL, 1, 651, 0x0000 }, { > KM_RCP_DATA_DW0_B_DYN, 5, 729, 0x0000 }, > + { KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 }, { > KM_RCP_DATA_DW10_DYN, 5, 55, 0x0000 }, > + { KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 }, { > KM_RCP_DATA_DW10_SEL_A, 2, 68, 0x0000 }, > + { KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 }, { > KM_RCP_DATA_DW2_B_DYN, 5, 742, 0x0000 }, > + { KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 }, { > KM_RCP_DATA_DW8_DYN, 5, 36, 0x0000 }, > + { KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 }, { > KM_RCP_DATA_DW8_SEL_A, 3, 49, 0x0000 }, > + { KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 }, { > KM_RCP_DATA_EL_A, 4, 653, 0x0000 }, > + { KM_RCP_DATA_EL_B, 3, 657, 0x0000 }, { KM_RCP_DATA_FTM_A, > 16, 662, 0x0000 }, > + { KM_RCP_DATA_FTM_B, 16, 678, 0x0000 }, { > KM_RCP_DATA_INFO_A, 1, 660, 0x0000 }, > + { KM_RCP_DATA_INFO_B, 1, 661, 0x0000 }, { > KM_RCP_DATA_KEYWAY_A, 1, 725, 0x0000 }, > + { KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 }, { > KM_RCP_DATA_KL_A, 4, 718, 0x0000 }, > + { KM_RCP_DATA_KL_B, 3, 722, 0x0000 }, { KM_RCP_DATA_MASK_A, > 384, 75, 0x0000 }, > + { KM_RCP_DATA_MASK_B, 192, 459, 0x0000 }, { > KM_RCP_DATA_PAIRED, 1, 652, 0x0000 }, > + { KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 }, { > KM_RCP_DATA_QW0_OFS, 8, 5, 0x0000 }, > + { KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 }, { > KM_RCP_DATA_QW0_SEL_B, 3, 16, 0x0000 }, > + { KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 }, { > KM_RCP_DATA_QW4_OFS, 8, 24, 0x0000 }, > + { KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 }, { > KM_RCP_DATA_QW4_SEL_B, 2, 34, 0x0000 }, > + { KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 }, { > KM_RCP_DATA_SW4_B_OFS, 8, 760, 0x0000 }, > + { KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 }, { > KM_RCP_DATA_SW5_B_OFS, 8, 773, 0x0000 }, > + { KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 }, { > KM_RCP_DATA_SWX_SEL_A, 1, 73, 0x0000 }, > + { KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 }, { > KM_RCP_DATA_SYNERGY_MODE, 2, 727, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_status_fields[] =3D { > + { KM_STATUS_TCQ_RDY, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tcam_ctrl_fields[] =3D { > + { KM_TCAM_CTRL_ADR, 14, 0, 0x0000 }, > + { KM_TCAM_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tcam_data_fields[] =3D { > + { KM_TCAM_DATA_T, 72, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tci_ctrl_fields[] =3D { > + { KM_TCI_CTRL_ADR, 10, 0, 0x0000 }, > + { KM_TCI_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tci_data_fields[] =3D { > + { KM_TCI_DATA_COLOR, 32, 0, 0x0000 }, > + { KM_TCI_DATA_FT, 4, 32, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tcq_ctrl_fields[] =3D { > + { KM_TCQ_CTRL_ADR, 7, 0, 0x0000 }, > + { KM_TCQ_CTRL_CNT, 5, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s km_tcq_data_fields[] =3D { > + { KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 }, > + { KM_TCQ_DATA_QUAL, 3, 12, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s km_registers[] =3D { > + { KM_CAM_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_cam_ctrl_fields }, > + { KM_CAM_DATA, 3, 216, NTHW_FPGA_REG_TYPE_WO, 0, 12, > km_cam_data_fields }, > + { KM_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_rcp_ctrl_fields }, > + { KM_RCP_DATA, 1, 781, NTHW_FPGA_REG_TYPE_WO, 0, 44, > km_rcp_data_fields }, > + { KM_STATUS, 10, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, > km_status_fields }, > + { KM_TCAM_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_tcam_ctrl_fields }, > + { KM_TCAM_DATA, 5, 72, NTHW_FPGA_REG_TYPE_WO, 0, 1, > km_tcam_data_fields }, > + { KM_TCI_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_tci_ctrl_fields }, > + { KM_TCI_DATA, 7, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_tci_data_fields }, > + { KM_TCQ_CTRL, 8, 21, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_tcq_ctrl_fields }, > + { KM_TCQ_DATA, 9, 15, NTHW_FPGA_REG_TYPE_WO, 0, 2, > km_tcq_data_fields }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] =3D { > + { MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_bip_err_fields[] =3D { > + { MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_block_lock_fields[] =3D { > + { MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_block_lock_chg_fields[] =3D { > + { MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_debounce_ctrl_fields[] =3D { > + { MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 }, > + { MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 }, > + { MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 }, > + { MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_drp_ctrl_fields[] =3D { > + { MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 }, { > MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 }, > + { MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 }, { > MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 }, > + { MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 }, { > MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_ctrl_fields[] =3D { > + { MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_cw_cnt_fields[] =3D { > + { MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_0_fields[] =3D { > + { MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_1_fields[] =3D { > + { MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_2_fields[] =3D { > + { MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_3_fields[] =3D { > + { MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_0_fields[] =3D { > + { MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_1_fields[] =3D { > + { MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_2_fields[] =3D { > + { MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_3_fields[] =3D { > + { MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_lane_map_fields[] =3D { > + { MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_stat_fields[] =3D { > + { MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 }, > + { MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 }, > + { MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 }, > + { MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 }, > + { MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 }, > + { MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 }, > + { MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 }, > + { MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 }, > + { MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 }, > + { MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 }, > + { MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_fec_ucw_cnt_fields[] =3D { > + { MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_ctl_rx_fields[] =3D { > + { MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 }, { > MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 }, > + { MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 }, { > MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 }, > + { MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 }, { > MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 }, > + { MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 }, { > MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 }, > + { MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 }, { > MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 }, > + { MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 }, { > MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 }, > + { MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 }, { > MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 }, > + { MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 }, { > MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 }, > + { MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 }, { > MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 }, > + { MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 }, { > MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_ctl_tx_fields[] =3D { > + { MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 }, { > MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 }, > + { MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 }, { > MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 }, > + { MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 }, { > MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 }, > + { MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 }, { > MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_diff_ctl_fields[] =3D { > + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 }, > + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 }, > + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 }, > + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_loop_fields[] =3D { > + { MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 }, > + { MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 }, > + { MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 }, > + { MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_post_cursor_fields[] =3D { > + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 }, > + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 }, > + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 }, > + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_prbs_sel_fields[] =3D { > + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 }, > + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_pre_cursor_fields[] =3D { > + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 }, > + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 }, > + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 }, > + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_rx_buf_stat_fields[] =3D { > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, > 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, > 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, > 0x0000 }, > + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, > 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_scan_ctl_fields[] =3D { > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 }, > + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_scan_stat_fields[] =3D { > + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 }, > + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_gty_stat_fields[] =3D { > + { MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 }, > + { MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 }, > + { MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 }, > + { MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 }, > + { MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_link_summary_fields[] =3D { > + { MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 }, > + { MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 }, > + { MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 }, > + { MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 }, > + { MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_mac_pcs_config_fields[] =3D { > + { MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 }, > + { MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_max_pkt_len_fields[] =3D { > + { MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_phymac_misc_fields[] =3D { > + { MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 }, > + { MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 }, > + { MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 }, > + { MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 }, > + { MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_phy_stat_fields[] =3D { > + { MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 }, > + { MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 }, > + { MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_fields[] =3D { > + { MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_latch_fields[] =3D { > + { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, > 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, > 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 }, > + { MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_stat_pcs_tx_fields[] =3D { > + { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, > 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, > 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 }, > + { MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_synced_fields[] =3D { > + { MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_synced_err_fields[] =3D { > + { MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_test_err_fields[] =3D { > + { MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_timestamp_comp_fields[] =3D { > + { MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 }, > + { MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_fields[] =3D { > + { MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_chg_fields[] =3D { > + { MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s mac_pcs_registers[] =3D { > + { MAC_PCS_BAD_CODE, 26, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_bad_code_fields }, > + { MAC_PCS_BIP_ERR, 31, 640, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_bip_err_fields }, > + { MAC_PCS_BLOCK_LOCK, 27, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_block_lock_fields }, > + { > + MAC_PCS_BLOCK_LOCK_CHG, 28, 20, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_block_lock_chg_fields > + }, > + { > + MAC_PCS_DEBOUNCE_CTRL, 1, 19, > NTHW_FPGA_REG_TYPE_RW, 264714, 4, > + mac_pcs_debounce_ctrl_fields > + }, > + { MAC_PCS_DRP_CTRL, 43, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 6, > mac_pcs_drp_ctrl_fields }, > + { MAC_PCS_FEC_CTRL, 2, 5, NTHW_FPGA_REG_TYPE_RW, 0, 1, > mac_pcs_fec_ctrl_fields }, > + { MAC_PCS_FEC_CW_CNT, 9, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_fec_cw_cnt_fields }, > + { > + MAC_PCS_FEC_ERR_CNT_0, 11, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_err_cnt_0_fields > + }, > + { > + MAC_PCS_FEC_ERR_CNT_1, 12, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_err_cnt_1_fields > + }, > + { > + MAC_PCS_FEC_ERR_CNT_2, 13, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_err_cnt_2_fields > + }, > + { > + MAC_PCS_FEC_ERR_CNT_3, 14, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_err_cnt_3_fields > + }, > + { > + MAC_PCS_FEC_LANE_DLY_0, 5, 14, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_lane_dly_0_fields > + }, > + { > + MAC_PCS_FEC_LANE_DLY_1, 6, 14, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_lane_dly_1_fields > + }, > + { > + MAC_PCS_FEC_LANE_DLY_2, 7, 14, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_lane_dly_2_fields > + }, > + { > + MAC_PCS_FEC_LANE_DLY_3, 8, 14, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_fec_lane_dly_3_fields > + }, > + { MAC_PCS_FEC_LANE_MAP, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_fec_lane_map_fields }, > + { MAC_PCS_FEC_STAT, 3, 11, NTHW_FPGA_REG_TYPE_RO, 0, 11, > mac_pcs_fec_stat_fields }, > + { MAC_PCS_FEC_UCW_CNT, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, > 1, mac_pcs_fec_ucw_cnt_fields }, > + { MAC_PCS_GTY_CTL_RX, 38, 28, NTHW_FPGA_REG_TYPE_RW, 0, 20, > mac_pcs_gty_ctl_rx_fields }, > + { MAC_PCS_GTY_CTL_TX, 39, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, > mac_pcs_gty_ctl_tx_fields }, > + { > + MAC_PCS_GTY_DIFF_CTL, 35, 20, > NTHW_FPGA_REG_TYPE_RW, 811800, 4, > + mac_pcs_gty_diff_ctl_fields > + }, > + { MAC_PCS_GTY_LOOP, 20, 12, NTHW_FPGA_REG_TYPE_RW, 0, 4, > mac_pcs_gty_loop_fields }, > + { > + MAC_PCS_GTY_POST_CURSOR, 36, 20, > NTHW_FPGA_REG_TYPE_RW, 676500, 4, > + mac_pcs_gty_post_cursor_fields > + }, > + { MAC_PCS_GTY_PRBS_SEL, 40, 32, NTHW_FPGA_REG_TYPE_RW, 0, > 8, mac_pcs_gty_prbs_sel_fields }, > + { > + MAC_PCS_GTY_PRE_CURSOR, 37, 20, > NTHW_FPGA_REG_TYPE_RW, 0, 4, > + mac_pcs_gty_pre_cursor_fields > + }, > + { > + MAC_PCS_GTY_RX_BUF_STAT, 34, 24, > NTHW_FPGA_REG_TYPE_RO, 0, 8, > + mac_pcs_gty_rx_buf_stat_fields > + }, > + { > + MAC_PCS_GTY_SCAN_CTL, 41, 16, > NTHW_FPGA_REG_TYPE_RW, 0, 16, > + mac_pcs_gty_scan_ctl_fields > + }, > + { > + MAC_PCS_GTY_SCAN_STAT, 42, 8, > NTHW_FPGA_REG_TYPE_RO, 0, 8, > + mac_pcs_gty_scan_stat_fields > + }, > + { MAC_PCS_GTY_STAT, 33, 16, NTHW_FPGA_REG_TYPE_RO, 0, 12, > mac_pcs_gty_stat_fields }, > + { MAC_PCS_LINK_SUMMARY, 0, 19, NTHW_FPGA_REG_TYPE_RO, 0, > 11, mac_pcs_link_summary_fields }, > + { > + MAC_PCS_MAC_PCS_CONFIG, 19, 12, > NTHW_FPGA_REG_TYPE_RW, 272, 12, > + mac_pcs_mac_pcs_config_fields > + }, > + { > + MAC_PCS_MAX_PKT_LEN, 17, 14, > NTHW_FPGA_REG_TYPE_RW, 10000, 1, > + mac_pcs_max_pkt_len_fields > + }, > + { MAC_PCS_PHYMAC_MISC, 16, 8, NTHW_FPGA_REG_TYPE_MIXED, > 9, 5, mac_pcs_phymac_misc_fields }, > + { MAC_PCS_PHY_STAT, 15, 3, NTHW_FPGA_REG_TYPE_RO, 0, 3, > mac_pcs_phy_stat_fields }, > + { MAC_PCS_STAT_PCS_RX, 21, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, > mac_pcs_stat_pcs_rx_fields }, > + { > + MAC_PCS_STAT_PCS_RX_LATCH, 22, 10, > NTHW_FPGA_REG_TYPE_RO, 0, 10, > + mac_pcs_stat_pcs_rx_latch_fields > + }, > + { MAC_PCS_STAT_PCS_TX, 23, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, > mac_pcs_stat_pcs_tx_fields }, > + { MAC_PCS_SYNCED, 24, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_synced_fields }, > + { MAC_PCS_SYNCED_ERR, 25, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_synced_err_fields }, > + { MAC_PCS_TEST_ERR, 32, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_test_err_fields }, > + { > + MAC_PCS_TIMESTAMP_COMP, 18, 32, > NTHW_FPGA_REG_TYPE_RW, 94373291, 2, > + mac_pcs_timestamp_comp_fields > + }, > + { MAC_PCS_VL_DEMUXED, 29, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_pcs_vl_demuxed_fields }, > + { > + MAC_PCS_VL_DEMUXED_CHG, 30, 20, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_pcs_vl_demuxed_chg_fields > + }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_bad_fcs_fields[] =3D { > + { MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_fragment_fields[] =3D { > + { MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_packet_bad_fcs_fields[] =3D { > + { MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_packet_small_fields[] =3D { > + { MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_total_bytes_fields[] =3D { > + { MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_total_good_bytes_fields[] =3D { > + { MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_total_good_packets_fields[] =3D { > + { MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_total_packets_fields[] =3D { > + { MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_rx_undersize_fields[] =3D { > + { MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s mac_rx_registers[] =3D { > + { MAC_RX_BAD_FCS, 0, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_bad_fcs_fields }, > + { MAC_RX_FRAGMENT, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_fragment_fields }, > + { > + MAC_RX_PACKET_BAD_FCS, 7, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_rx_packet_bad_fcs_fields > + }, > + { MAC_RX_PACKET_SMALL, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_packet_small_fields }, > + { MAC_RX_TOTAL_BYTES, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_total_bytes_fields }, > + { > + MAC_RX_TOTAL_GOOD_BYTES, 5, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_rx_total_good_bytes_fields > + }, > + { > + MAC_RX_TOTAL_GOOD_PACKETS, 2, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_rx_total_good_packets_fields > + }, > + { MAC_RX_TOTAL_PACKETS, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_total_packets_fields }, > + { MAC_RX_UNDERSIZE, 8, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_rx_undersize_fields }, > +}; > + > +static nthw_fpga_field_init_s mac_tx_packet_small_fields[] =3D { > + { MAC_TX_PACKET_SMALL_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_tx_total_bytes_fields[] =3D { > + { MAC_TX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_tx_total_good_bytes_fields[] =3D { > + { MAC_TX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_tx_total_good_packets_fields[] =3D { > + { MAC_TX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s mac_tx_total_packets_fields[] =3D { > + { MAC_TX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s mac_tx_registers[] =3D { > + { MAC_TX_PACKET_SMALL, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_tx_packet_small_fields }, > + { MAC_TX_TOTAL_BYTES, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_tx_total_bytes_fields }, > + { > + MAC_TX_TOTAL_GOOD_BYTES, 4, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_tx_total_good_bytes_fields > + }, > + { > + MAC_TX_TOTAL_GOOD_PACKETS, 1, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + mac_tx_total_good_packets_fields > + }, > + { MAC_TX_TOTAL_PACKETS, 0, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > mac_tx_total_packets_fields }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] =3D { > + { PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_rdaddr_fields[] =3D { > + { PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata0_fields[] =3D { > + { PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata1_fields[] =3D { > + { PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata2_fields[] =3D { > + { PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 }, > + { PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 }, > + { PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 }, > + { PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_rd_tg_tg_rd_run_fields[] =3D { > + { PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s pci_rd_tg_registers[] =3D { > + { PCI_RD_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_rd_tg_tg_ctrl_fields }, > + { PCI_RD_TG_TG_RDADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_rd_tg_tg_rdaddr_fields }, > + { PCI_RD_TG_TG_RDDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_rd_tg_tg_rddata0_fields }, > + { PCI_RD_TG_TG_RDDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_rd_tg_tg_rddata1_fields }, > + { PCI_RD_TG_TG_RDDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 4, > pci_rd_tg_tg_rddata2_fields }, > + { PCI_RD_TG_TG_RD_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_rd_tg_tg_rd_run_fields }, > +}; > + > +static nthw_fpga_field_init_s pci_ta_control_fields[] =3D { > + { PCI_TA_CONTROL_ENABLE, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_ta_length_error_fields[] =3D { > + { PCI_TA_LENGTH_ERROR_AMOUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s pci_ta_packet_bad_fields[] =3D { > + { PCI_TA_PACKET_BAD_AMOUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s pci_ta_packet_good_fields[] =3D { > + { PCI_TA_PACKET_GOOD_AMOUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s pci_ta_payload_error_fields[] =3D { > + { PCI_TA_PAYLOAD_ERROR_AMOUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s pci_ta_registers[] =3D { > + { PCI_TA_CONTROL, 0, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_ta_control_fields }, > + { PCI_TA_LENGTH_ERROR, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_ta_length_error_fields }, > + { PCI_TA_PACKET_BAD, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_ta_packet_bad_fields }, > + { PCI_TA_PACKET_GOOD, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_ta_packet_good_fields }, > + { PCI_TA_PAYLOAD_ERROR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_ta_payload_error_fields }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_ctrl_fields[] =3D { > + { PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_seq_fields[] =3D { > + { PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_wraddr_fields[] =3D { > + { PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata0_fields[] =3D { > + { PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata1_fields[] =3D { > + { PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata2_fields[] =3D { > + { PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 }, { > PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 }, > + { PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 }, { > PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 }, > + { PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 }, > +}; > + > +static nthw_fpga_field_init_s pci_wr_tg_tg_wr_run_fields[] =3D { > + { PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s pci_wr_tg_registers[] =3D { > + { PCI_WR_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, > pci_wr_tg_tg_ctrl_fields }, > + { PCI_WR_TG_TG_SEQ, 6, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, > pci_wr_tg_tg_seq_fields }, > + { PCI_WR_TG_TG_WRADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_wr_tg_tg_wraddr_fields }, > + { PCI_WR_TG_TG_WRDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 1, pci_wr_tg_tg_wrdata0_fields }, > + { PCI_WR_TG_TG_WRDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 1, pci_wr_tg_tg_wrdata1_fields }, > + { PCI_WR_TG_TG_WRDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 5, pci_wr_tg_tg_wrdata2_fields }, > + { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, > pci_wr_tg_tg_wr_run_fields }, > +}; > + > +static nthw_fpga_field_init_s pdb_config_fields[] =3D { > + { PDB_CONFIG_PORT_OFS, 6, 3, 0 }, > + { PDB_CONFIG_TS_FORMAT, 3, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pdb_rcp_ctrl_fields[] =3D { > + { PDB_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { PDB_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s pdb_rcp_data_fields[] =3D { > + { PDB_RCP_DATA_ALIGN, 1, 17, 0x0000 }, > + { PDB_RCP_DATA_CRC_OVERWRITE, 1, 16, 0x0000 }, > + { PDB_RCP_DATA_DESCRIPTOR, 4, 0, 0x0000 }, > + { PDB_RCP_DATA_DESC_LEN, 5, 4, 0 }, > + { PDB_RCP_DATA_DUPLICATE_BIT, 5, 61, 0x0000 }, > + { PDB_RCP_DATA_DUPLICATE_EN, 1, 60, 0x0000 }, > + { PDB_RCP_DATA_IP_PROT_TNL, 1, 57, 0x0000 }, > + { PDB_RCP_DATA_OFS0_DYN, 5, 18, 0x0000 }, > + { PDB_RCP_DATA_OFS0_REL, 8, 23, 0x0000 }, > + { PDB_RCP_DATA_OFS1_DYN, 5, 31, 0x0000 }, > + { PDB_RCP_DATA_OFS1_REL, 8, 36, 0x0000 }, > + { PDB_RCP_DATA_OFS2_DYN, 5, 44, 0x0000 }, > + { PDB_RCP_DATA_OFS2_REL, 8, 49, 0x0000 }, > + { PDB_RCP_DATA_PCAP_KEEP_FCS, 1, 66, 0x0000 }, > + { PDB_RCP_DATA_PPC_HSH, 2, 58, 0x0000 }, > + { PDB_RCP_DATA_TX_IGNORE, 1, 14, 0x0000 }, > + { PDB_RCP_DATA_TX_NOW, 1, 15, 0x0000 }, > + { PDB_RCP_DATA_TX_PORT, 5, 9, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s pdb_registers[] =3D { > + { PDB_CONFIG, 2, 10, NTHW_FPGA_REG_TYPE_WO, 0, 2, > pdb_config_fields }, > + { PDB_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > pdb_rcp_ctrl_fields }, > + { PDB_RCP_DATA, 1, 67, NTHW_FPGA_REG_TYPE_WO, 0, 18, > pdb_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s pdi_cr_fields[] =3D { > + { PDI_CR_EN, 1, 0, 0 }, { PDI_CR_PARITY, 1, 4, 0 }, { PDI_CR_RST, 1= , 1, 0 > }, > + { PDI_CR_RXRST, 1, 2, 0 }, { PDI_CR_STOP, 1, 5, 0 }, { PDI_CR_TXRST= , 1, > 3, 0 }, > +}; > + > +static nthw_fpga_field_init_s pdi_drr_fields[] =3D { > + { PDI_DRR_DRR, 8, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pdi_dtr_fields[] =3D { > + { PDI_DTR_DTR, 8, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s pdi_pre_fields[] =3D { > + { PDI_PRE_PRE, 7, 0, 3 }, > +}; > + > +static nthw_fpga_field_init_s pdi_sr_fields[] =3D { > + { PDI_SR_DISABLE_BUSY, 1, 2, 0 }, { PDI_SR_DONE, 1, 0, 0 }, > + { PDI_SR_ENABLE_BUSY, 1, 1, 0 }, { PDI_SR_FRAME_ERR, 1, 5, 0 }, > + { PDI_SR_OVERRUN_ERR, 1, 7, 0 }, { PDI_SR_PARITY_ERR, 1, 6, 0 }, > + { PDI_SR_RXLVL, 7, 8, 0 }, { PDI_SR_RX_BUSY, 1, 4, 0 }, > + { PDI_SR_TXLVL, 7, 15, 0 }, { PDI_SR_TX_BUSY, 1, 3, 0 }, > +}; > + > +static nthw_fpga_field_init_s pdi_srr_fields[] =3D { > + { PDI_SRR_RST, 4, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s pdi_registers[] =3D { > + { PDI_CR, 1, 6, NTHW_FPGA_REG_TYPE_WO, 0, 6, pdi_cr_fields }, > + { PDI_DRR, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, pdi_drr_fields }, > + { PDI_DTR, 3, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, pdi_dtr_fields }, > + { PDI_PRE, 5, 7, NTHW_FPGA_REG_TYPE_WO, 3, 1, pdi_pre_fields }, > + { PDI_SR, 2, 22, NTHW_FPGA_REG_TYPE_RO, 0, 10, pdi_sr_fields }, > + { PDI_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, pdi_srr_fields }, > +}; > + > +static nthw_fpga_field_init_s qsl_qen_ctrl_fields[] =3D { > + { QSL_QEN_CTRL_ADR, 5, 0, 0x0000 }, > + { QSL_QEN_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_qen_data_fields[] =3D { > + { QSL_QEN_DATA_EN, 4, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_qst_ctrl_fields[] =3D { > + { QSL_QST_CTRL_ADR, 12, 0, 0x0000 }, > + { QSL_QST_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_qst_data_fields[] =3D { > + { QSL_QST_DATA_LRE, 1, 9, 0x0000 }, { QSL_QST_DATA_QEN, 1, 7, > 0x0000 }, > + { QSL_QST_DATA_QUEUE, 7, 0, 0x0000 }, { QSL_QST_DATA_TCI, 16, > 10, 0x0000 }, > + { QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 }, { QSL_QST_DATA_VEN, 1, > 26, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_rcp_ctrl_fields[] =3D { > + { QSL_RCP_CTRL_ADR, 5, 0, 0x0000 }, > + { QSL_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_rcp_data_fields[] =3D { > + { QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 }, { QSL_RCP_DATA_DROP, 2, > 1, 0x0000 }, > + { QSL_RCP_DATA_LR, 2, 51, 0x0000 }, { QSL_RCP_DATA_TBL_HI, 12, > 15, 0x0000 }, > + { QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 }, { > QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 }, > + { QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 }, { QSL_RCP_DATA_TSA, > 1, 53, 0x0000 }, > + { QSL_RCP_DATA_VLI, 2, 54, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_unmq_ctrl_fields[] =3D { > + { QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 }, > + { QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qsl_unmq_data_fields[] =3D { > + { QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 }, > + { QSL_UNMQ_DATA_EN, 1, 7, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s qsl_registers[] =3D { > + { QSL_QEN_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > qsl_qen_ctrl_fields }, > + { QSL_QEN_DATA, 5, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, > qsl_qen_data_fields }, > + { QSL_QST_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > qsl_qst_ctrl_fields }, > + { QSL_QST_DATA, 3, 27, NTHW_FPGA_REG_TYPE_WO, 0, 6, > qsl_qst_data_fields }, > + { QSL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > qsl_rcp_ctrl_fields }, > + { QSL_RCP_DATA, 1, 56, NTHW_FPGA_REG_TYPE_WO, 0, 9, > qsl_rcp_data_fields }, > + { QSL_UNMQ_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > qsl_unmq_ctrl_fields }, > + { QSL_UNMQ_DATA, 7, 8, NTHW_FPGA_REG_TYPE_WO, 0, 2, > qsl_unmq_data_fields }, > +}; > + > +static nthw_fpga_field_init_s qspi_cr_fields[] =3D { > + { QSPI_CR_CPHA, 1, 4, 0 }, { QSPI_CR_CPOL, 1, 3, 0 }, > + { QSPI_CR_LOOP, 1, 0, 0 }, { QSPI_CR_LSBF, 1, 9, 0 }, > + { QSPI_CR_MSSAE, 1, 7, 1 }, { QSPI_CR_MST, 1, 2, 0 }, > + { QSPI_CR_MTI, 1, 8, 1 }, { QSPI_CR_RXFIFO_RST, 1, 6, 0 }, > + { QSPI_CR_SPE, 1, 1, 0 }, { QSPI_CR_TXFIFO_RST, 1, 5, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_dgie_fields[] =3D { > + { QSPI_DGIE_GIE, 1, 31, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_drr_fields[] =3D { > + { QSPI_DRR_DATA_VAL, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qspi_dtr_fields[] =3D { > + { QSPI_DTR_DATA_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_ier_fields[] =3D { > + { QSPI_IER_CMD_ERR, 1, 13, 0 }, { QSPI_IER_CPOL_CPHA_ERR, 1, 9, 0 > }, > + { QSPI_IER_DRR_FULL, 1, 4, 0 }, { QSPI_IER_DRR_NEMPTY, 1, 8, 0 }, > + { QSPI_IER_DRR_OR, 1, 5, 0 }, { QSPI_IER_DTR_EMPTY, 1, 2, 0 }, > + { QSPI_IER_DTR_UR, 1, 3, 0 }, { QSPI_IER_LOOP_ERR, 1, 12, 0 }, > + { QSPI_IER_MODF, 1, 0, 0 }, { QSPI_IER_MSB_ERR, 1, 11, 0 }, > + { QSPI_IER_SLV_ERR, 1, 10, 0 }, { QSPI_IER_SLV_MODF, 1, 1, 0 }, > + { QSPI_IER_SLV_MS, 1, 7, 0 }, { QSPI_IER_TXFIFO_HEMPTY, 1, 6, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_isr_fields[] =3D { > + { QSPI_ISR_CMD_ERR, 1, 13, 0 }, { QSPI_ISR_CPOL_CPHA_ERR, 1, 9, 0 > }, > + { QSPI_ISR_DRR_FULL, 1, 4, 0 }, { QSPI_ISR_DRR_NEMPTY, 1, 8, 0 }, > + { QSPI_ISR_DRR_OR, 1, 5, 0 }, { QSPI_ISR_DTR_EMPTY, 1, 2, 0 }, > + { QSPI_ISR_DTR_UR, 1, 3, 0 }, { QSPI_ISR_LOOP_ERR, 1, 12, 0 }, > + { QSPI_ISR_MODF, 1, 0, 0 }, { QSPI_ISR_MSB_ERR, 1, 11, 0 }, > + { QSPI_ISR_SLV_ERR, 1, 10, 0 }, { QSPI_ISR_SLV_MODF, 1, 1, 0 }, > + { QSPI_ISR_SLV_MS, 1, 7, 0 }, { QSPI_ISR_TXFIFO_HEMPTY, 1, 6, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_rx_fifo_ocy_fields[] =3D { > + { QSPI_RX_FIFO_OCY_OCY_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_sr_fields[] =3D { > + { QSPI_SR_CMD_ERR, 1, 10, 0 }, { QSPI_SR_CPOL_CPHA_ERR, 1, 6, 0 }, > + { QSPI_SR_LOOP_ERR, 1, 9, 0 }, { QSPI_SR_MODF, 1, 4, 0 }, > + { QSPI_SR_MSB_ERR, 1, 8, 0 }, { QSPI_SR_RXEMPTY, 1, 0, 1 }, > + { QSPI_SR_RXFULL, 1, 1, 0 }, { QSPI_SR_SLVMS, 1, 5, 1 }, > + { QSPI_SR_SLV_ERR, 1, 7, 0 }, { QSPI_SR_TXEMPTY, 1, 2, 1 }, > + { QSPI_SR_TXFULL, 1, 3, 0 }, > +}; > + > +static nthw_fpga_field_init_s qspi_srr_fields[] =3D { > + { QSPI_SRR_RST, 4, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s qspi_ssr_fields[] =3D { > + { QSPI_SSR_SEL_SLV, 32, 0, 4294967295 }, > +}; > + > +static nthw_fpga_field_init_s qspi_tx_fifo_ocy_fields[] =3D { > + { QSPI_TX_FIFO_OCY_OCY_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s qspi_registers[] =3D { > + { QSPI_CR, 24, 10, NTHW_FPGA_REG_TYPE_RW, 384, 10, > qspi_cr_fields }, > + { QSPI_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > qspi_dgie_fields }, > + { QSPI_DRR, 27, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, qspi_drr_fields > }, > + { QSPI_DTR, 26, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > qspi_dtr_fields }, > + { QSPI_IER, 10, 14, NTHW_FPGA_REG_TYPE_RW, 0, 14, qspi_ier_fields > }, > + { QSPI_ISR, 8, 14, NTHW_FPGA_REG_TYPE_RW, 0, 14, qspi_isr_fields > }, > + { QSPI_RX_FIFO_OCY, 30, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > qspi_rx_fifo_ocy_fields }, > + { QSPI_SR, 25, 11, NTHW_FPGA_REG_TYPE_RO, 37, 11, qspi_sr_fields > }, > + { QSPI_SRR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, qspi_srr_fields > }, > + { QSPI_SSR, 28, 32, NTHW_FPGA_REG_TYPE_RW, 4294967295, 1, > qspi_ssr_fields }, > + { QSPI_TX_FIFO_OCY, 29, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > qspi_tx_fifo_ocy_fields }, > +}; > + > +static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] =3D { > + { RAC_DBG_CTRL_C, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rac_dbg_data_fields[] =3D { > + { RAC_DBG_DATA_D, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_buf_free_fields[] =3D { > + { RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 }, { > RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 }, > + { RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 }, { > RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 }, > + { RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_buf_used_fields[] =3D { > + { RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 }, > + { RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 }, > + { RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ib_hi_fields[] =3D { > + { RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ib_lo_fields[] =3D { > + { RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ib_rd_fields[] =3D { > + { RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ib_wr_fields[] =3D { > + { RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ob_hi_fields[] =3D { > + { RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ob_lo_fields[] =3D { > + { RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_dma_ob_wr_fields[] =3D { > + { RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_ib_data_fields[] =3D { > + { RAC_RAB_IB_DATA_D, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_init_fields[] =3D { > + { RAC_RAB_INIT_RAB, 3, 0, 7 }, > +}; > + > +static nthw_fpga_field_init_s rac_rab_ob_data_fields[] =3D { > + { RAC_RAB_OB_DATA_D, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s rac_registers[] =3D { > + { RAC_DBG_CTRL, 4200, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > rac_dbg_ctrl_fields }, > + { RAC_DBG_DATA, 4208, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > rac_dbg_data_fields }, > + { > + RAC_RAB_BUF_FREE, 4176, 32, > NTHW_FPGA_REG_TYPE_MIXED, 33489407, 5, > + rac_rab_buf_free_fields > + }, > + { RAC_RAB_BUF_USED, 4184, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, > 3, rac_rab_buf_used_fields }, > + { RAC_RAB_DMA_IB_HI, 4360, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > rac_rab_dma_ib_hi_fields }, > + { RAC_RAB_DMA_IB_LO, 4352, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 1, rac_rab_dma_ib_lo_fields }, > + { RAC_RAB_DMA_IB_RD, 4424, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, > rac_rab_dma_ib_rd_fields }, > + { RAC_RAB_DMA_IB_WR, 4416, 16, NTHW_FPGA_REG_TYPE_WO, 0, > 1, rac_rab_dma_ib_wr_fields }, > + { RAC_RAB_DMA_OB_HI, 4376, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 1, rac_rab_dma_ob_hi_fields }, > + { RAC_RAB_DMA_OB_LO, 4368, 32, NTHW_FPGA_REG_TYPE_WO, 0, > 1, rac_rab_dma_ob_lo_fields }, > + { RAC_RAB_DMA_OB_WR, 4480, 16, NTHW_FPGA_REG_TYPE_RO, 0, > 1, rac_rab_dma_ob_wr_fields }, > + { RAC_RAB_IB_DATA, 4160, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > rac_rab_ib_data_fields }, > + { RAC_RAB_INIT, 4192, 3, NTHW_FPGA_REG_TYPE_RW, 7, 1, > rac_rab_init_fields }, > + { RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_TYPE_RC1, 0, 1, > rac_rab_ob_data_fields }, > +}; > + > +static nthw_fpga_field_init_s rfd_ctrl_fields[] =3D { > + { RFD_CTRL_CFP, 1, 2, 1 }, > + { RFD_CTRL_ISL, 1, 0, 1 }, > + { RFD_CTRL_PWMCW, 1, 1, 1 }, > +}; > + > +static nthw_fpga_field_init_s rfd_max_frame_size_fields[] =3D { > + { RFD_MAX_FRAME_SIZE_MAX, 14, 0, 9018 }, > +}; > + > +static nthw_fpga_field_init_s rfd_tnl_vlan_fields[] =3D { > + { RFD_TNL_VLAN_TPID0, 16, 0, 33024 }, > + { RFD_TNL_VLAN_TPID1, 16, 16, 33024 }, > +}; > + > +static nthw_fpga_field_init_s rfd_vlan_fields[] =3D { > + { RFD_VLAN_TPID0, 16, 0, 33024 }, > + { RFD_VLAN_TPID1, 16, 16, 33024 }, > +}; > + > +static nthw_fpga_field_init_s rfd_vxlan_fields[] =3D { > + { RFD_VXLAN_DP0, 16, 0, 4789 }, > + { RFD_VXLAN_DP1, 16, 16, 4789 }, > +}; > + > +static nthw_fpga_register_init_s rfd_registers[] =3D { > + { RFD_CTRL, 0, 3, NTHW_FPGA_REG_TYPE_WO, 7, 3, rfd_ctrl_fields }, > + { RFD_MAX_FRAME_SIZE, 1, 14, NTHW_FPGA_REG_TYPE_WO, 9018, > 1, rfd_max_frame_size_fields }, > + { RFD_TNL_VLAN, 3, 32, NTHW_FPGA_REG_TYPE_WO, 2164293888, > 2, rfd_tnl_vlan_fields }, > + { RFD_VLAN, 2, 32, NTHW_FPGA_REG_TYPE_WO, 2164293888, 2, > rfd_vlan_fields }, > + { RFD_VXLAN, 4, 32, NTHW_FPGA_REG_TYPE_WO, 313856693, 2, > rfd_vxlan_fields }, > +}; > + > +static nthw_fpga_field_init_s rmc_ctrl_fields[] =3D { > + { RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 }, { > RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 }, > + { RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 }, { > RMC_CTRL_BLOCK_STATT, 1, 0, 1 }, > + { RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 }, > +}; > + > +static nthw_fpga_field_init_s rmc_dbg_fields[] =3D { > + { RMC_DBG_MERGE, 31, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rmc_mac_if_fields[] =3D { > + { RMC_MAC_IF_ERR, 31, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rmc_status_fields[] =3D { > + { RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 }, > + { RMC_STATUS_SF_RAM_OF, 1, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s rmc_registers[] =3D { > + { RMC_CTRL, 0, 25, NTHW_FPGA_REG_TYPE_RW, 771, 5, > rmc_ctrl_fields }, > + { RMC_DBG, 2, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, rmc_dbg_fields > }, > + { RMC_MAC_IF, 3, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, > rmc_mac_if_fields }, > + { RMC_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, > rmc_status_fields }, > +}; > + > +static nthw_fpga_field_init_s rpl_ext_ctrl_fields[] =3D { > + { RPL_EXT_CTRL_ADR, 10, 0, 0x0000 }, > + { RPL_EXT_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpl_ext_data_fields[] =3D { > + { RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpl_rcp_ctrl_fields[] =3D { > + { RPL_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { RPL_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpl_rcp_data_fields[] =3D { > + { RPL_RCP_DATA_DYN, 5, 0, 0x0000 }, { > RPL_RCP_DATA_ETH_TYPE_WR, 1, 36, 0x0000 }, > + { RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 }, { RPL_RCP_DATA_LEN, 8, > 15, 0x0000 }, > + { RPL_RCP_DATA_OFS, 10, 5, 0x0000 }, { RPL_RCP_DATA_RPL_PTR, > 12, 23, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpl_rpl_ctrl_fields[] =3D { > + { RPL_RPL_CTRL_ADR, 12, 0, 0x0000 }, > + { RPL_RPL_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpl_rpl_data_fields[] =3D { > + { RPL_RPL_DATA_VALUE, 128, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s rpl_registers[] =3D { > + { RPL_EXT_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > rpl_ext_ctrl_fields }, > + { RPL_EXT_DATA, 3, 12, NTHW_FPGA_REG_TYPE_WO, 0, 1, > rpl_ext_data_fields }, > + { RPL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > rpl_rcp_ctrl_fields }, > + { RPL_RCP_DATA, 1, 37, NTHW_FPGA_REG_TYPE_WO, 0, 6, > rpl_rcp_data_fields }, > + { RPL_RPL_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > rpl_rpl_ctrl_fields }, > + { RPL_RPL_DATA, 5, 128, NTHW_FPGA_REG_TYPE_WO, 0, 1, > rpl_rpl_data_fields }, > +}; > + > +static nthw_fpga_field_init_s rpp_lr_ifr_rcp_ctrl_fields[] =3D { > + { RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpp_lr_ifr_rcp_data_fields[] =3D { > + { RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0x0000 }, > + { RPP_LR_IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 }, > + { RPP_LR_IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x0000 }, > + { RPP_LR_IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 }, > + { RPP_LR_IFR_RCP_DATA_MTU, 14, 2, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpp_lr_rcp_ctrl_fields[] =3D { > + { RPP_LR_RCP_CTRL_ADR, 4, 0, 0x0000 }, > + { RPP_LR_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rpp_lr_rcp_data_fields[] =3D { > + { RPP_LR_RCP_DATA_EXP, 14, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s rpp_lr_registers[] =3D { > + { RPP_LR_IFR_RCP_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > rpp_lr_ifr_rcp_ctrl_fields }, > + { RPP_LR_IFR_RCP_DATA, 3, 18, NTHW_FPGA_REG_TYPE_WO, 0, 5, > rpp_lr_ifr_rcp_data_fields }, > + { RPP_LR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > rpp_lr_rcp_ctrl_fields }, > + { RPP_LR_RCP_DATA, 1, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, > rpp_lr_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s rst9563_ctrl_fields[] =3D { > + { RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 }, > + { RST9563_CTRL_TS_CLKSEL, 1, 1, 1 }, > + { RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 }, > +}; > + > +static nthw_fpga_field_init_s rst9563_power_fields[] =3D { > + { RST9563_POWER_PU_NSEB, 1, 1, 0 }, > + { RST9563_POWER_PU_PHY, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s rst9563_rst_fields[] =3D { > + { RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, > 7 }, > + { RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_RST_PERIPH, 1, 13, 0 }, > + { RST9563_RST_PHY, 2, 7, 3 }, { RST9563_RST_PTP, 1, 11, 1 }, > + { RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST9563_RST_RPP, 1, 2, 1 }, > + { RST9563_RST_SDC, 1, 6, 1 }, { RST9563_RST_SYS, 1, 0, 1 }, > + { RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST9563_RST_TMC, 1, 1, 1 > }, > + { RST9563_RST_TS, 1, 12, 1 }, { RST9563_RST_TS_MMCM, 1, 17, 0 }, > +}; > + > +static nthw_fpga_field_init_s rst9563_stat_fields[] =3D { > + { RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 }, > + { RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 }, > + { RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 }, > + { RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 }, > + { RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 }, > + { RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s rst9563_sticky_fields[] =3D { > + { RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 }, > + { RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 }, > + { RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 }, > + { RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 }, > + { RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 }, > + { RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s rst9563_registers[] =3D { > + { RST9563_CTRL, 1, 3, NTHW_FPGA_REG_TYPE_RW, 7, 3, > rst9563_ctrl_fields }, > + { RST9563_POWER, 4, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, > rst9563_power_fields }, > + { RST9563_RST, 0, 18, NTHW_FPGA_REG_TYPE_RW, 8191, 14, > rst9563_rst_fields }, > + { RST9563_STAT, 2, 6, NTHW_FPGA_REG_TYPE_RO, 0, 6, > rst9563_stat_fields }, > + { RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, > rst9563_sticky_fields }, > +}; > + > +static nthw_fpga_field_init_s slc_rcp_ctrl_fields[] =3D { > + { SLC_RCP_CTRL_ADR, 6, 0, 0x0000 }, > + { SLC_RCP_CTRL_CNT, 16, 16, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s slc_rcp_data_fields[] =3D { > + { SLC_RCP_DATA_HEAD_DYN, 5, 1, 0x0000 }, { > SLC_RCP_DATA_HEAD_OFS, 8, 6, 0x0000 }, > + { SLC_RCP_DATA_HEAD_SLC_EN, 1, 0, 0x0000 }, { > SLC_RCP_DATA_PCAP, 1, 35, 0x0000 }, > + { SLC_RCP_DATA_TAIL_DYN, 5, 15, 0x0000 }, { > SLC_RCP_DATA_TAIL_OFS, 15, 20, 0x0000 }, > + { SLC_RCP_DATA_TAIL_SLC_EN, 1, 14, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s slc_registers[] =3D { > + { SLC_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > slc_rcp_ctrl_fields }, > + { SLC_RCP_DATA, 1, 36, NTHW_FPGA_REG_TYPE_WO, 0, 7, > slc_rcp_data_fields }, > +}; > + > +static nthw_fpga_field_init_s spim_cfg_fields[] =3D { > + { SPIM_CFG_PRE, 3, 0, 5 }, > +}; > + > +static nthw_fpga_field_init_s spim_cfg_clk_fields[] =3D { > + { SPIM_CFG_CLK_MODE, 2, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spim_cr_fields[] =3D { > + { SPIM_CR_EN, 1, 1, 0 }, > + { SPIM_CR_LOOP, 1, 0, 0 }, > + { SPIM_CR_RXRST, 1, 3, 0 }, > + { SPIM_CR_TXRST, 1, 2, 0 }, > +}; > + > +static nthw_fpga_field_init_s spim_drr_fields[] =3D { > + { SPIM_DRR_DRR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spim_dtr_fields[] =3D { > + { SPIM_DTR_DTR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spim_sr_fields[] =3D { > + { SPIM_SR_DONE, 1, 0, 0 }, { SPIM_SR_RXEMPTY, 1, 2, 1 }, { > SPIM_SR_RXFULL, 1, 4, 0 }, > + { SPIM_SR_RXLVL, 8, 16, 0 }, { SPIM_SR_TXEMPTY, 1, 1, 1 }, { > SPIM_SR_TXFULL, 1, 3, 0 }, > + { SPIM_SR_TXLVL, 8, 8, 0 }, > +}; > + > +static nthw_fpga_field_init_s spim_srr_fields[] =3D { > + { SPIM_SRR_RST, 4, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s spim_registers[] =3D { > + { SPIM_CFG, 5, 3, NTHW_FPGA_REG_TYPE_WO, 5, 1, spim_cfg_fields > }, > + { SPIM_CFG_CLK, 6, 2, NTHW_FPGA_REG_TYPE_WO, 0, 1, > spim_cfg_clk_fields }, > + { SPIM_CR, 1, 4, NTHW_FPGA_REG_TYPE_WO, 0, 4, spim_cr_fields }, > + { SPIM_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, spim_drr_fields > }, > + { SPIM_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, spim_dtr_fields > }, > + { SPIM_SR, 2, 24, NTHW_FPGA_REG_TYPE_RO, 6, 7, spim_sr_fields }, > + { SPIM_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, spim_srr_fields > }, > +}; > + > +static nthw_fpga_field_init_s spis_cr_fields[] =3D { > + { SPIS_CR_DEBUG, 1, 4, 0 }, { SPIS_CR_EN, 1, 1, 0 }, { SPIS_CR_LOOP= , > 1, 0, 0 }, > + { SPIS_CR_RXRST, 1, 3, 0 }, { SPIS_CR_TXRST, 1, 2, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_drr_fields[] =3D { > + { SPIS_DRR_DRR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_dtr_fields[] =3D { > + { SPIS_DTR_DTR, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_ram_ctrl_fields[] =3D { > + { SPIS_RAM_CTRL_ADR, 6, 0, 0 }, > + { SPIS_RAM_CTRL_CNT, 6, 6, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_ram_data_fields[] =3D { > + { SPIS_RAM_DATA_DATA, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_sr_fields[] =3D { > + { SPIS_SR_DONE, 1, 0, 0 }, { SPIS_SR_FRAME_ERR, 1, 24, 0 }, > + { SPIS_SR_READ_ERR, 1, 25, 0 }, { SPIS_SR_RXEMPTY, 1, 2, 1 }, > + { SPIS_SR_RXFULL, 1, 4, 0 }, { SPIS_SR_RXLVL, 8, 16, 0 }, > + { SPIS_SR_TXEMPTY, 1, 1, 1 }, { SPIS_SR_TXFULL, 1, 3, 0 }, > + { SPIS_SR_TXLVL, 8, 8, 0 }, { SPIS_SR_WRITE_ERR, 1, 26, 0 }, > +}; > + > +static nthw_fpga_field_init_s spis_srr_fields[] =3D { > + { SPIS_SRR_RST, 4, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s spis_registers[] =3D { > + { SPIS_CR, 1, 5, NTHW_FPGA_REG_TYPE_WO, 0, 5, spis_cr_fields }, > + { SPIS_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, spis_drr_fields }, > + { SPIS_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, spis_dtr_fields }, > + { SPIS_RAM_CTRL, 5, 12, NTHW_FPGA_REG_TYPE_RW, 0, 2, > spis_ram_ctrl_fields }, > + { SPIS_RAM_DATA, 6, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > spis_ram_data_fields }, > + { SPIS_SR, 2, 27, NTHW_FPGA_REG_TYPE_RO, 6, 10, spis_sr_fields }, > + { SPIS_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, spis_srr_fields }, > +}; > + > +static nthw_fpga_field_init_s sta_byte_fields[] =3D { > + { STA_BYTE_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_cfg_fields[] =3D { > + { STA_CFG_CNT_CLEAR, 1, 1, 0 }, > + { STA_CFG_DMA_ENA, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s sta_cv_err_fields[] =3D { > + { STA_CV_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_fcs_err_fields[] =3D { > + { STA_FCS_ERR_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_host_adr_lsb_fields[] =3D { > + { STA_HOST_ADR_LSB_LSB, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s sta_host_adr_msb_fields[] =3D { > + { STA_HOST_ADR_MSB_MSB, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_bin_fields[] =3D { > + { STA_LOAD_BIN_BIN, 32, 0, 8388607 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_bps_rx_0_fields[] =3D { > + { STA_LOAD_BPS_RX_0_BPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_bps_rx_1_fields[] =3D { > + { STA_LOAD_BPS_RX_1_BPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_bps_tx_0_fields[] =3D { > + { STA_LOAD_BPS_TX_0_BPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_bps_tx_1_fields[] =3D { > + { STA_LOAD_BPS_TX_1_BPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_pps_rx_0_fields[] =3D { > + { STA_LOAD_PPS_RX_0_PPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_pps_rx_1_fields[] =3D { > + { STA_LOAD_PPS_RX_1_PPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_pps_tx_0_fields[] =3D { > + { STA_LOAD_PPS_TX_0_PPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_load_pps_tx_1_fields[] =3D { > + { STA_LOAD_PPS_TX_1_PPS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_pckt_fields[] =3D { > + { STA_PCKT_CNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s sta_status_fields[] =3D { > + { STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s sta_registers[] =3D { > + { STA_BYTE, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_byte_fields }, > + { STA_CFG, 0, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, sta_cfg_fields }, > + { STA_CV_ERR, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_cv_err_fields }, > + { STA_FCS_ERR, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_fcs_err_fields }, > + { STA_HOST_ADR_LSB, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > sta_host_adr_lsb_fields }, > + { STA_HOST_ADR_MSB, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > sta_host_adr_msb_fields }, > + { STA_LOAD_BIN, 8, 32, NTHW_FPGA_REG_TYPE_WO, 8388607, 1, > sta_load_bin_fields }, > + { STA_LOAD_BPS_RX_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_bps_rx_0_fields }, > + { STA_LOAD_BPS_RX_1, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_bps_rx_1_fields }, > + { STA_LOAD_BPS_TX_0, 15, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_bps_tx_0_fields }, > + { STA_LOAD_BPS_TX_1, 17, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_bps_tx_1_fields }, > + { STA_LOAD_PPS_RX_0, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_pps_rx_0_fields }, > + { STA_LOAD_PPS_RX_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_pps_rx_1_fields }, > + { STA_LOAD_PPS_TX_0, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_pps_tx_0_fields }, > + { STA_LOAD_PPS_TX_1, 16, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > sta_load_pps_tx_1_fields }, > + { STA_PCKT, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_pckt_fields }, > + { STA_STATUS, 7, 1, NTHW_FPGA_REG_TYPE_RC1, 0, 1, > sta_status_fields }, > +}; > + > +static nthw_fpga_field_init_s tempmon_alarms_fields[] =3D { > + { TEMPMON_ALARMS_OT, 1, 1, 0x0000 }, > + { TEMPMON_ALARMS_OT_OVERWR, 1, 2, 0 }, > + { TEMPMON_ALARMS_OT_OVERWRVAL, 1, 3, 0 }, > + { TEMPMON_ALARMS_TEMP, 1, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tempmon_stat_fields[] =3D { > + { TEMPMON_STAT_TEMP, 12, 0, 0x0000 }, > +}; > + > +static nthw_fpga_register_init_s tempmon_registers[] =3D { > + { TEMPMON_ALARMS, 1, 4, NTHW_FPGA_REG_TYPE_MIXED, 0, 4, > tempmon_alarms_fields }, > + { TEMPMON_STAT, 0, 12, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tempmon_stat_fields }, > +}; > + > +static nthw_fpga_field_init_s tint_ctrl_fields[] =3D { > + { TINT_CTRL_INTERVAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tint_status_fields[] =3D { > + { TINT_STATUS_DELAYED, 8, 8, 0 }, > + { TINT_STATUS_SKIPPED, 8, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s tint_registers[] =3D { > + { TINT_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, tint_ctrl_fields > }, > + { TINT_STATUS, 1, 16, NTHW_FPGA_REG_TYPE_RC1, 0, 2, > tint_status_fields }, > +}; > + > +static nthw_fpga_field_init_s tsm_con0_config_fields[] =3D { > + { TSM_CON0_CONFIG_BLIND, 5, 8, 9 }, { > TSM_CON0_CONFIG_DC_SRC, 3, 5, 0 }, > + { TSM_CON0_CONFIG_PORT, 3, 0, 0 }, { > TSM_CON0_CONFIG_PPSIN_2_5V, 1, 13, 0 }, > + { TSM_CON0_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con0_interface_fields[] =3D { > + { TSM_CON0_INTERFACE_EX_TERM, 2, 0, 3 }, { > TSM_CON0_INTERFACE_IN_REF_PWM, 8, 12, 128 }, > + { TSM_CON0_INTERFACE_PWM_ENA, 1, 2, 0 }, { > TSM_CON0_INTERFACE_RESERVED, 1, 3, 0 }, > + { TSM_CON0_INTERFACE_VTERM_PWM, 8, 4, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con0_sample_hi_fields[] =3D { > + { TSM_CON0_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con0_sample_lo_fields[] =3D { > + { TSM_CON0_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con1_config_fields[] =3D { > + { TSM_CON1_CONFIG_BLIND, 5, 8, 9 }, { > TSM_CON1_CONFIG_DC_SRC, 3, 5, 0 }, > + { TSM_CON1_CONFIG_PORT, 3, 0, 0 }, { > TSM_CON1_CONFIG_PPSIN_2_5V, 1, 13, 0 }, > + { TSM_CON1_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con1_sample_hi_fields[] =3D { > + { TSM_CON1_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con1_sample_lo_fields[] =3D { > + { TSM_CON1_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con2_config_fields[] =3D { > + { TSM_CON2_CONFIG_BLIND, 5, 8, 9 }, { > TSM_CON2_CONFIG_DC_SRC, 3, 5, 0 }, > + { TSM_CON2_CONFIG_PORT, 3, 0, 0 }, { > TSM_CON2_CONFIG_PPSIN_2_5V, 1, 13, 0 }, > + { TSM_CON2_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con2_sample_hi_fields[] =3D { > + { TSM_CON2_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con2_sample_lo_fields[] =3D { > + { TSM_CON2_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con3_config_fields[] =3D { > + { TSM_CON3_CONFIG_BLIND, 5, 5, 26 }, > + { TSM_CON3_CONFIG_PORT, 3, 0, 1 }, > + { TSM_CON3_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con3_sample_hi_fields[] =3D { > + { TSM_CON3_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con3_sample_lo_fields[] =3D { > + { TSM_CON3_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con4_config_fields[] =3D { > + { TSM_CON4_CONFIG_BLIND, 5, 5, 26 }, > + { TSM_CON4_CONFIG_PORT, 3, 0, 1 }, > + { TSM_CON4_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con4_sample_hi_fields[] =3D { > + { TSM_CON4_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con4_sample_lo_fields[] =3D { > + { TSM_CON4_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con5_config_fields[] =3D { > + { TSM_CON5_CONFIG_BLIND, 5, 5, 26 }, > + { TSM_CON5_CONFIG_PORT, 3, 0, 1 }, > + { TSM_CON5_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con5_sample_hi_fields[] =3D { > + { TSM_CON5_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con5_sample_lo_fields[] =3D { > + { TSM_CON5_SAMPLE_LO_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con6_config_fields[] =3D { > + { TSM_CON6_CONFIG_BLIND, 5, 5, 26 }, > + { TSM_CON6_CONFIG_PORT, 3, 0, 1 }, > + { TSM_CON6_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con6_sample_hi_fields[] =3D { > + { TSM_CON6_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con6_sample_lo_fields[] =3D { > + { TSM_CON6_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con7_host_sample_hi_fields[] =3D { > + { TSM_CON7_HOST_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_con7_host_sample_lo_fields[] =3D { > + { TSM_CON7_HOST_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_config_fields[] =3D { > + { TSM_CONFIG_NTTS_SRC, 2, 5, 0 }, { TSM_CONFIG_NTTS_SYNC, 1, 4, > 0 }, > + { TSM_CONFIG_TIMESET_EDGE, 2, 8, 1 }, { > TSM_CONFIG_TIMESET_SRC, 3, 10, 0 }, > + { TSM_CONFIG_TIMESET_UP, 1, 7, 0 }, { TSM_CONFIG_TS_FORMAT, 4, > 0, 1 }, > +}; > + > +static nthw_fpga_field_init_s tsm_int_config_fields[] =3D { > + { TSM_INT_CONFIG_AUTO_DISABLE, 1, 0, 0 }, > + { TSM_INT_CONFIG_MASK, 19, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_int_stat_fields[] =3D { > + { TSM_INT_STAT_CAUSE, 19, 1, 0 }, > + { TSM_INT_STAT_ENABLE, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_led_fields[] =3D { > + { TSM_LED_LED0_BG_COLOR, 2, 3, 0 }, { TSM_LED_LED0_COLOR, 2, 1, > 0 }, > + { TSM_LED_LED0_MODE, 1, 0, 0 }, { TSM_LED_LED0_SRC, 4, 5, 0 }, > + { TSM_LED_LED1_BG_COLOR, 2, 12, 0 }, { TSM_LED_LED1_COLOR, 2, > 10, 0 }, > + { TSM_LED_LED1_MODE, 1, 9, 0 }, { TSM_LED_LED1_SRC, 4, 14, 1 }, > + { TSM_LED_LED2_BG_COLOR, 2, 21, 0 }, { TSM_LED_LED2_COLOR, 2, > 19, 0 }, > + { TSM_LED_LED2_MODE, 1, 18, 0 }, { TSM_LED_LED2_SRC, 4, 23, 2 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_config_fields[] =3D { > + { TSM_NTTS_CONFIG_AUTO_HARDSET, 1, 5, 1 }, > + { TSM_NTTS_CONFIG_EXT_CLK_ADJ, 1, 6, 0 }, > + { TSM_NTTS_CONFIG_HIGH_SAMPLE, 1, 4, 0 }, > + { TSM_NTTS_CONFIG_TS_SRC_FORMAT, 4, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_ext_stat_fields[] =3D { > + { TSM_NTTS_EXT_STAT_MASTER_ID, 8, 16, 0x0000 }, > + { TSM_NTTS_EXT_STAT_MASTER_REV, 8, 24, 0x0000 }, > + { TSM_NTTS_EXT_STAT_MASTER_STAT, 16, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_limit_hi_fields[] =3D { > + { TSM_NTTS_LIMIT_HI_SEC, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_limit_lo_fields[] =3D { > + { TSM_NTTS_LIMIT_LO_NS, 32, 0, 100000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_offset_fields[] =3D { > + { TSM_NTTS_OFFSET_NS, 30, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_sample_hi_fields[] =3D { > + { TSM_NTTS_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_sample_lo_fields[] =3D { > + { TSM_NTTS_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_stat_fields[] =3D { > + { TSM_NTTS_STAT_NTTS_VALID, 1, 0, 0 }, > + { TSM_NTTS_STAT_SIGNAL_LOST, 8, 1, 0 }, > + { TSM_NTTS_STAT_SYNC_LOST, 8, 9, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_ts_t0_hi_fields[] =3D { > + { TSM_NTTS_TS_T0_HI_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_ts_t0_lo_fields[] =3D { > + { TSM_NTTS_TS_T0_LO_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ntts_ts_t0_offset_fields[] =3D { > + { TSM_NTTS_TS_T0_OFFSET_COUNT, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pb_ctrl_fields[] =3D { > + { TSM_PB_CTRL_INSTMEM_WR, 1, 1, 0 }, > + { TSM_PB_CTRL_RST, 1, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pb_instmem_fields[] =3D { > + { TSM_PB_INSTMEM_MEM_ADDR, 14, 0, 0 }, > + { TSM_PB_INSTMEM_MEM_DATA, 18, 14, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pi_ctrl_i_fields[] =3D { > + { TSM_PI_CTRL_I_VAL, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pi_ctrl_ki_fields[] =3D { > + { TSM_PI_CTRL_KI_GAIN, 24, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pi_ctrl_kp_fields[] =3D { > + { TSM_PI_CTRL_KP_GAIN, 24, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_pi_ctrl_shl_fields[] =3D { > + { TSM_PI_CTRL_SHL_VAL, 4, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_stat_fields[] =3D { > + { TSM_STAT_HARD_SYNC, 8, 8, 0 }, { TSM_STAT_LINK_CON0, 1, 0, 0 }, > + { TSM_STAT_LINK_CON1, 1, 1, 0 }, { TSM_STAT_LINK_CON2, 1, 2, 0 }, > + { TSM_STAT_LINK_CON3, 1, 3, 0 }, { TSM_STAT_LINK_CON4, 1, 4, 0 }, > + { TSM_STAT_LINK_CON5, 1, 5, 0 }, { TSM_STAT_NTTS_INSYNC, 1, 6, 0 > }, > + { TSM_STAT_PTP_MI_PRESENT, 1, 7, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_timer_ctrl_fields[] =3D { > + { TSM_TIMER_CTRL_TIMER_EN_T0, 1, 0, 0 }, > + { TSM_TIMER_CTRL_TIMER_EN_T1, 1, 1, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_timer_t0_fields[] =3D { > + { TSM_TIMER_T0_MAX_COUNT, 30, 0, 50000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_timer_t1_fields[] =3D { > + { TSM_TIMER_T1_MAX_COUNT, 30, 0, 50000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_time_hardset_hi_fields[] =3D { > + { TSM_TIME_HARDSET_HI_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_time_hardset_lo_fields[] =3D { > + { TSM_TIME_HARDSET_LO_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_time_hi_fields[] =3D { > + { TSM_TIME_HI_SEC, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_time_lo_fields[] =3D { > + { TSM_TIME_LO_NS, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_time_rate_adj_fields[] =3D { > + { TSM_TIME_RATE_ADJ_FRACTION, 29, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_hi_fields[] =3D { > + { TSM_TS_HI_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_lo_fields[] =3D { > + { TSM_TS_LO_TIME, 32, 0, 0x0000 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_offset_fields[] =3D { > + { TSM_TS_OFFSET_NS, 30, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_fields[] =3D { > + { TSM_TS_STAT_OVERRUN, 1, 16, 0 }, > + { TSM_TS_STAT_SAMPLES, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_hi_offset_fields[] =3D { > + { TSM_TS_STAT_HI_OFFSET_NS, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_lo_offset_fields[] =3D { > + { TSM_TS_STAT_LO_OFFSET_NS, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_tar_hi_fields[] =3D { > + { TSM_TS_STAT_TAR_HI_SEC, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_tar_lo_fields[] =3D { > + { TSM_TS_STAT_TAR_LO_NS, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_x_fields[] =3D { > + { TSM_TS_STAT_X_NS, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_x2_hi_fields[] =3D { > + { TSM_TS_STAT_X2_HI_NS, 16, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_ts_stat_x2_lo_fields[] =3D { > + { TSM_TS_STAT_X2_LO_NS, 32, 0, 0 }, > +}; > + > +static nthw_fpga_field_init_s tsm_utc_offset_fields[] =3D { > + { TSM_UTC_OFFSET_SEC, 8, 0, 0 }, > +}; > + > +static nthw_fpga_register_init_s tsm_registers[] =3D { > + { TSM_CON0_CONFIG, 24, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, > tsm_con0_config_fields }, > + { > + TSM_CON0_INTERFACE, 25, 20, NTHW_FPGA_REG_TYPE_RW, > 524291, 5, > + tsm_con0_interface_fields > + }, > + { TSM_CON0_SAMPLE_HI, 27, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con0_sample_hi_fields }, > + { TSM_CON0_SAMPLE_LO, 26, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con0_sample_lo_fields }, > + { TSM_CON1_CONFIG, 28, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, > tsm_con1_config_fields }, > + { TSM_CON1_SAMPLE_HI, 30, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con1_sample_hi_fields }, > + { TSM_CON1_SAMPLE_LO, 29, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con1_sample_lo_fields }, > + { TSM_CON2_CONFIG, 31, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, > tsm_con2_config_fields }, > + { TSM_CON2_SAMPLE_HI, 33, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con2_sample_hi_fields }, > + { TSM_CON2_SAMPLE_LO, 32, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con2_sample_lo_fields }, > + { TSM_CON3_CONFIG, 34, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, > tsm_con3_config_fields }, > + { TSM_CON3_SAMPLE_HI, 36, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con3_sample_hi_fields }, > + { TSM_CON3_SAMPLE_LO, 35, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con3_sample_lo_fields }, > + { TSM_CON4_CONFIG, 37, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, > tsm_con4_config_fields }, > + { TSM_CON4_SAMPLE_HI, 39, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con4_sample_hi_fields }, > + { TSM_CON4_SAMPLE_LO, 38, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con4_sample_lo_fields }, > + { TSM_CON5_CONFIG, 40, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, > tsm_con5_config_fields }, > + { TSM_CON5_SAMPLE_HI, 42, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con5_sample_hi_fields }, > + { TSM_CON5_SAMPLE_LO, 41, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con5_sample_lo_fields }, > + { TSM_CON6_CONFIG, 43, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, > tsm_con6_config_fields }, > + { TSM_CON6_SAMPLE_HI, 45, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con6_sample_hi_fields }, > + { TSM_CON6_SAMPLE_LO, 44, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_con6_sample_lo_fields }, > + { > + TSM_CON7_HOST_SAMPLE_HI, 47, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + tsm_con7_host_sample_hi_fields > + }, > + { > + TSM_CON7_HOST_SAMPLE_LO, 46, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + tsm_con7_host_sample_lo_fields > + }, > + { TSM_CONFIG, 0, 13, NTHW_FPGA_REG_TYPE_RW, 257, 6, > tsm_config_fields }, > + { TSM_INT_CONFIG, 2, 20, NTHW_FPGA_REG_TYPE_RW, 0, 2, > tsm_int_config_fields }, > + { TSM_INT_STAT, 3, 20, NTHW_FPGA_REG_TYPE_MIXED, 0, 2, > tsm_int_stat_fields }, > + { TSM_LED, 4, 27, NTHW_FPGA_REG_TYPE_RW, 16793600, 12, > tsm_led_fields }, > + { TSM_NTTS_CONFIG, 13, 7, NTHW_FPGA_REG_TYPE_RW, 32, 4, > tsm_ntts_config_fields }, > + { TSM_NTTS_EXT_STAT, 15, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, > tsm_ntts_ext_stat_fields }, > + { TSM_NTTS_LIMIT_HI, 23, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_ntts_limit_hi_fields }, > + { TSM_NTTS_LIMIT_LO, 22, 32, NTHW_FPGA_REG_TYPE_RW, > 100000, 1, tsm_ntts_limit_lo_fields }, > + { TSM_NTTS_OFFSET, 21, 30, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_ntts_offset_fields }, > + { TSM_NTTS_SAMPLE_HI, 19, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ntts_sample_hi_fields }, > + { TSM_NTTS_SAMPLE_LO, 18, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ntts_sample_lo_fields }, > + { TSM_NTTS_STAT, 14, 17, NTHW_FPGA_REG_TYPE_RO, 0, 3, > tsm_ntts_stat_fields }, > + { TSM_NTTS_TS_T0_HI, 17, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ntts_ts_t0_hi_fields }, > + { TSM_NTTS_TS_T0_LO, 16, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ntts_ts_t0_lo_fields }, > + { > + TSM_NTTS_TS_T0_OFFSET, 20, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + tsm_ntts_ts_t0_offset_fields > + }, > + { TSM_PB_CTRL, 63, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, > tsm_pb_ctrl_fields }, > + { TSM_PB_INSTMEM, 64, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, > tsm_pb_instmem_fields }, > + { TSM_PI_CTRL_I, 54, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, > tsm_pi_ctrl_i_fields }, > + { TSM_PI_CTRL_KI, 52, 24, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_pi_ctrl_ki_fields }, > + { TSM_PI_CTRL_KP, 51, 24, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_pi_ctrl_kp_fields }, > + { TSM_PI_CTRL_SHL, 53, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, > tsm_pi_ctrl_shl_fields }, > + { TSM_STAT, 1, 16, NTHW_FPGA_REG_TYPE_RO, 0, 9, tsm_stat_fields > }, > + { TSM_TIMER_CTRL, 48, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, > tsm_timer_ctrl_fields }, > + { TSM_TIMER_T0, 49, 30, NTHW_FPGA_REG_TYPE_RW, 50000, 1, > tsm_timer_t0_fields }, > + { TSM_TIMER_T1, 50, 30, NTHW_FPGA_REG_TYPE_RW, 50000, 1, > tsm_timer_t1_fields }, > + { TSM_TIME_HARDSET_HI, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_time_hardset_hi_fields }, > + { TSM_TIME_HARDSET_LO, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_time_hardset_lo_fields }, > + { TSM_TIME_HI, 9, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_time_hi_fields }, > + { TSM_TIME_LO, 8, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_time_lo_fields }, > + { TSM_TIME_RATE_ADJ, 10, 29, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_time_rate_adj_fields }, > + { TSM_TS_HI, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_hi_fields }, > + { TSM_TS_LO, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_lo_fields }, > + { TSM_TS_OFFSET, 7, 30, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_ts_offset_fields }, > + { TSM_TS_STAT, 55, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, > tsm_ts_stat_fields }, > + { > + TSM_TS_STAT_HI_OFFSET, 62, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + tsm_ts_stat_hi_offset_fields > + }, > + { > + TSM_TS_STAT_LO_OFFSET, 61, 32, > NTHW_FPGA_REG_TYPE_RO, 0, 1, > + tsm_ts_stat_lo_offset_fields > + }, > + { TSM_TS_STAT_TAR_HI, 57, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_stat_tar_hi_fields }, > + { TSM_TS_STAT_TAR_LO, 56, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_stat_tar_lo_fields }, > + { TSM_TS_STAT_X, 58, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_stat_x_fields }, > + { TSM_TS_STAT_X2_HI, 60, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_stat_x2_hi_fields }, > + { TSM_TS_STAT_X2_LO, 59, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, > tsm_ts_stat_x2_lo_fields }, > + { TSM_UTC_OFFSET, 65, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, > tsm_utc_offset_fields }, > +}; > + > +static nthw_fpga_module_init_s fpga_modules[] =3D { > + { MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, > 34, cat_registers }, > + { MOD_CSU, 0, MOD_CSU, 0, 0, NTHW_FPGA_BUS_TYPE_RAB1, > 9728, 2, csu_registers }, > + { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, > 12832, 27, dbs_registers }, > + { MOD_FLM, 0, MOD_FLM, 0, 23, NTHW_FPGA_BUS_TYPE_RAB1, > 1280, 43, flm_registers }, > + { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, > 8704, 10, gfg_registers }, > + { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, > 9216, 12, gmf_registers }, > + { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, > 9728, 12, gmf_registers }, > + { > + MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, > NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2, > + gpio_phy_registers > + }, > + { MOD_HFU, 0, MOD_HFU, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, > 9472, 2, hfu_registers }, > + { MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_TYPE_PCI, 0, 18, > hif_registers }, > + { MOD_HSH, 0, MOD_HSH, 0, 5, NTHW_FPGA_BUS_TYPE_RAB1, > 1536, 2, hsh_registers }, > + { MOD_IFR, 0, MOD_IFR, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 9984, > 6, ifr_registers }, > + { MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 768, 22, > iic_registers }, > + { MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22, > iic_registers }, > + { MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, > 22, iic_registers }, > + { MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24960, > 22, iic_registers }, > + { MOD_KM, 0, MOD_KM, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1024, > 11, km_registers }, > + { > + MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, > NTHW_FPGA_BUS_TYPE_RAB2, 10240, 44, > + mac_pcs_registers > + }, > + { > + MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, > NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44, > + mac_pcs_registers > + }, > + { MOD_MAC_RX, 0, MOD_MAC_RX, 0, 0, > NTHW_FPGA_BUS_TYPE_RAB2, 10752, 9, mac_rx_registers }, > + { MOD_MAC_RX, 1, MOD_MAC_RX, 0, 0, > NTHW_FPGA_BUS_TYPE_RAB2, 12288, 9, mac_rx_registers }, > + { MOD_MAC_TX, 0, MOD_MAC_TX, 0, 0, > NTHW_FPGA_BUS_TYPE_RAB2, 11264, 5, mac_tx_registers }, > + { MOD_MAC_TX, 1, MOD_MAC_TX, 0, 0, > NTHW_FPGA_BUS_TYPE_RAB2, 12800, 5, mac_tx_registers }, > + { > + MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, > NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6, > + pci_rd_tg_registers > + }, > + { MOD_PCI_TA, 0, MOD_PCI_TA, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, > 2336, 5, pci_ta_registers }, > + { > + MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, > NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7, > + pci_wr_tg_registers > + }, > + { MOD_PDB, 0, MOD_PDB, 0, 9, NTHW_FPGA_BUS_TYPE_RAB1, > 2560, 3, pdb_registers }, > + { MOD_PDI, 0, MOD_PDI, 1, 1, NTHW_FPGA_BUS_TYPE_RAB0, 64, 6, > pdi_registers }, > + { MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1792, > 8, qsl_registers }, > + { MOD_QSPI, 0, MOD_QSPI, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, > 512, 11, qspi_registers }, > + { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, > 14, rac_registers }, > + { MOD_RFD, 0, MOD_RFD, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 256, > 5, rfd_registers }, > + { MOD_RMC, 0, MOD_RMC, 1, 3, NTHW_FPGA_BUS_TYPE_RAB0, > 12288, 4, rmc_registers }, > + { MOD_RPP_LR, 0, MOD_RPP_LR, 0, 2, > NTHW_FPGA_BUS_TYPE_RAB1, 2304, 4, rpp_lr_registers }, > + { MOD_RST9563, 0, MOD_RST9563, 0, 5, > NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers }, > + { MOD_SLC_LR, 0, MOD_SLC, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, > 2048, 2, slc_registers }, > + { MOD_SPIM, 0, MOD_SPIM, 1, 1, NTHW_FPGA_BUS_TYPE_RAB0, > 80, 7, spim_registers }, > + { MOD_SPIS, 0, MOD_SPIS, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 256, > 7, spis_registers }, > + { MOD_STA, 0, MOD_STA, 0, 9, NTHW_FPGA_BUS_TYPE_RAB0, 2048, > 17, sta_registers }, > + { > + MOD_TEMPMON, 0, MOD_TEMPMON, 0, 0, > NTHW_FPGA_BUS_TYPE_RAB0, 16384, 2, > + tempmon_registers > + }, > + { MOD_TINT, 0, MOD_TINT, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, > 1280, 2, tint_registers }, > + { MOD_TSM, 0, MOD_TSM, 0, 8, NTHW_FPGA_BUS_TYPE_RAB2, > 1024, 66, tsm_registers }, > + { MOD_TX_CPY, 0, MOD_CPY, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, > 9216, 26, cpy_registers }, > + { MOD_TX_INS, 0, MOD_INS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, > 8704, 2, ins_registers }, > + { MOD_TX_RPL, 0, MOD_RPL, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, > 8960, 6, rpl_registers }, > +}; > + > +static nthw_fpga_prod_param_s product_parameters[] =3D { > + { NT_BUILD_NUMBER, 0 }, > + { NT_BUILD_TIME, 1713859545 }, > + { NT_CATEGORIES, 64 }, > + { NT_CAT_DCT_PRESENT, 0 }, > + { NT_CAT_END_OFS_SUPPORT, 0 }, > + { NT_CAT_FUNCS, 64 }, > + { NT_CAT_KCC_BANKS, 3 }, > + { NT_CAT_KCC_PRESENT, 0 }, > + { NT_CAT_KCC_SIZE, 1536 }, > + { NT_CAT_KM_IF_CNT, 2 }, > + { NT_CAT_KM_IF_M0, 0 }, > + { NT_CAT_KM_IF_M1, 1 }, > + { NT_CAT_N_CMP, 8 }, > + { NT_CAT_N_EXT, 4 }, > + { NT_CAT_N_LEN, 8 }, > + { NT_CB_DEBUG, 0 }, > + { NT_COR_CATEGORIES, 16 }, > + { NT_COR_PRESENT, 0 }, > + { NT_CSU_PRESENT, 1 }, > + { NT_DBS_PRESENT, 1 }, > + { NT_DBS_RX_QUEUES, 128 }, > + { NT_DBS_TX_PORTS, 2 }, > + { NT_DBS_TX_QUEUES, 128 }, > + { NT_DDP_PRESENT, 0 }, > + { NT_DDP_TBL_DEPTH, 4096 }, > + { NT_EMI_SPLIT_STEPS, 16 }, > + { NT_EOF_TIMESTAMP_ONLY, 1 }, > + { NT_EPP_CATEGORIES, 32 }, > + { NT_FLM_CACHE, 1 }, > + { NT_FLM_CATEGORIES, 32 }, > + { NT_FLM_ENTRY_SIZE, 64 }, > + { NT_FLM_LOAD_APS_MAX, 260000000 }, > + { NT_FLM_LOAD_LPS_MAX, 300000000 }, > + { NT_FLM_PRESENT, 1 }, > + { NT_FLM_PRIOS, 4 }, > + { NT_FLM_PST_PROFILES, 16 }, > + { NT_FLM_SCRUB_PROFILES, 16 }, > + { NT_FLM_SIZE_MB, 12288 }, > + { NT_FLM_STATEFUL, 1 }, > + { NT_FLM_VARIANT, 2 }, > + { NT_GFG_PRESENT, 1 }, > + { NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 }, > + { NT_GMF_FCS_PRESENT, 0 }, > + { NT_GMF_IFG_SPEED_DIV, 33 }, > + { NT_GMF_IFG_SPEED_DIV100G, 33 }, > + { NT_GMF_IFG_SPEED_MUL, 20 }, > + { NT_GMF_IFG_SPEED_MUL100G, 20 }, > + { NT_GROUP_ID, 9563 }, > + { NT_HFU_PRESENT, 1 }, > + { NT_HIF_MSIX_BAR, 1 }, > + { NT_HIF_MSIX_PBA_OFS, 8192 }, > + { NT_HIF_MSIX_PRESENT, 1 }, > + { NT_HIF_MSIX_TBL_OFS, 0 }, > + { NT_HIF_MSIX_TBL_SIZE, 8 }, > + { NT_HIF_PER_PS, 4000 }, > + { NT_HIF_SRIOV_PRESENT, 1 }, > + { NT_HIF_VF_OFFSET, 4 }, > + { NT_HSH_CATEGORIES, 16 }, > + { NT_HSH_TOEPLITZ, 1 }, > + { NT_HST_CATEGORIES, 32 }, > + { NT_HST_PRESENT, 0 }, > + { NT_IOA_CATEGORIES, 1024 }, > + { NT_IOA_PRESENT, 0 }, > + { NT_IPF_PRESENT, 0 }, > + { NT_KM_CAM_BANKS, 3 }, > + { NT_KM_CAM_RECORDS, 2048 }, > + { NT_KM_CAM_REC_WORDS, 6 }, > + { NT_KM_CATEGORIES, 32 }, > + { NT_KM_END_OFS_SUPPORT, 0 }, > + { NT_KM_EXT_EXTRACTORS, 1 }, > + { NT_KM_FLOW_TYPES, 16 }, > + { NT_KM_PRESENT, 1 }, > + { NT_KM_SWX_PRESENT, 0 }, > + { NT_KM_SYNERGY_MATCH, 0 }, > + { NT_KM_TCAM_BANKS, 12 }, > + { NT_KM_TCAM_BANK_WIDTH, 72 }, > + { NT_KM_TCAM_HIT_QUAL, 0 }, > + { NT_KM_TCAM_KEYWAY, 1 }, > + { NT_KM_WIDE, 1 }, > + { NT_LR_PRESENT, 1 }, > + { NT_MCU_PRESENT, 0 }, > + { NT_MDG_DEBUG_FLOW_CONTROL, 0 }, > + { NT_MDG_DEBUG_REG_READ_BACK, 0 }, > + { NT_MSK_CATEGORIES, 32 }, > + { NT_MSK_PRESENT, 0 }, > + { NT_NFV_OVS_PRODUCT, 0 }, > + { NT_NIMS, 2 }, > + { NT_PCI_DEVICE_ID, 453 }, > + { NT_PCI_TA_TG_PRESENT, 1 }, > + { NT_PCI_VENDOR_ID, 6388 }, > + { NT_PDB_CATEGORIES, 16 }, > + { NT_PHY_ANEG_PRESENT, 0 }, > + { NT_PHY_KRFEC_PRESENT, 0 }, > + { NT_PHY_PORTS, 2 }, > + { NT_PHY_PORTS_PER_QUAD, 1 }, > + { NT_PHY_QUADS, 2 }, > + { NT_PHY_RSFEC_PRESENT, 1 }, > + { NT_QM_CELLS, 2097152 }, > + { NT_QM_CELL_SIZE, 6144 }, > + { NT_QM_PRESENT, 0 }, > + { NT_QSL_CATEGORIES, 32 }, > + { NT_QSL_COLOR_SEL_BW, 7 }, > + { NT_QSL_QST_SIZE, 4096 }, > + { NT_QUEUES, 128 }, > + { NT_RAC_RAB_INTERFACES, 3 }, > + { NT_RAC_RAB_OB_UPDATE, 0 }, > + { NT_REVISION_ID, 39 }, > + { NT_RMC_LAG_GROUPS, 1 }, > + { NT_RMC_PRESENT, 1 }, > + { NT_ROA_CATEGORIES, 1024 }, > + { NT_ROA_PRESENT, 0 }, > + { NT_RPF_MATURING_DEL_DEFAULT, -150 }, > + { NT_RPF_PRESENT, 0 }, > + { NT_RPP_PER_PS, 3333 }, > + { NT_RTX_PRESENT, 0 }, > + { NT_RX_HOST_BUFFERS, 128 }, > + { NT_RX_PORTS, 2 }, > + { NT_RX_PORT_REPLICATE, 0 }, > + { NT_SLB_PRESENT, 0 }, > + { NT_SLC_LR_PRESENT, 1 }, > + { NT_SLC_PRESENT, 0 }, > + { NT_STA_COLORS, 64 }, > + { NT_STA_LOAD_AVG_RX, 1 }, > + { NT_STA_LOAD_AVG_TX, 1 }, > + { NT_STA_RX_PORTS, 2 }, > + { NT_TBH_DEBUG_DLN, 1 }, > + { NT_TBH_PRESENT, 0 }, > + { NT_TFD_PRESENT, 1 }, > + { NT_TPE_CATEGORIES, 16 }, > + { NT_TSM_OST_ONLY, 0 }, > + { NT_TS_APPEND, 0 }, > + { NT_TS_INJECT_PRESENT, 0 }, > + { NT_TX_CPY_PACKET_READERS, 0 }, > + { NT_TX_CPY_PRESENT, 1 }, > + { NT_TX_CPY_SIDEBAND_READERS, 7 }, > + { NT_TX_CPY_VARIANT, 0 }, > + { NT_TX_CPY_WRITERS, 6 }, > + { NT_TX_HOST_BUFFERS, 128 }, > + { NT_TX_INS_OFS_ZERO, 1 }, > + { NT_TX_INS_PRESENT, 1 }, > + { NT_TX_MTU_PROFILE_IFR, 16 }, > + { NT_TX_ON_TIMESTAMP, 1 }, > + { NT_TX_PORTS, 2 }, > + { NT_TX_PORT_REPLICATE, 1 }, > + { NT_TX_RPL_DEPTH, 4096 }, > + { NT_TX_RPL_EXT_CATEGORIES, 1024 }, > + { NT_TX_RPL_OFS_ZERO, 1 }, > + { NT_TX_RPL_PRESENT, 1 }, > + { NT_TYPE_ID, 200 }, > + { NT_USE_TRIPLE_SPEED, 0 }, > + { NT_VERSION_ID, 55 }, > + { NT_VLI_PRESENT, 0 }, > + { 0, -1 }, /* END */ > +}; > + > +nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 =3D { > + 200, 9563, 55, 39, 0, 0, 1713859545, 152, product_parameters, 45, > fpga_modules, > +}; > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c > b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c > new file mode 100644 > index 0000000000..ea731ae979 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c > @@ -0,0 +1,6 @@ > + > + > +#include "nthw_fpga_instances.h" > +nthw_fpga_prod_init_s *nthw_fpga_instances[] =3D { > &nthw_fpga_9563_055_039_0000, NULL }; > + > +/* EOF */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h > new file mode 100644 > index 0000000000..c19b43c19b > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h > @@ -0,0 +1,7 @@ > + > + > +#include "fpga_model.h" > +extern nthw_fpga_prod_init_s *nthw_fpga_instances[]; > +extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000; > + > +/* EOF */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h > new file mode 100644 > index 0000000000..f2dba47488 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h > @@ -0,0 +1,93 @@ > +/* > + * nthw_fpga_mod_defs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_MOD_DEFS_H_ > +#define _NTHW_FPGA_MOD_DEFS_H_ > + > +#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the > first element */ > +#define MOD_CAT (0x30b447c2UL) > +#define MOD_CB (0x97db0a27UL) > +#define MOD_COR (0x4754cf79UL) > +#define MOD_CPY (0x1ddc186fUL) > +#define MOD_CSU (0x3f470787UL) > +#define MOD_DBS (0x80b29727UL) > +#define MOD_DDP (0x4fe1611bUL) > +#define MOD_EPP (0x608ddc79UL) > +#define MOD_EQM (0x1a9081e1UL) > +#define MOD_FHM (0x83d696a0UL) > +#define MOD_FLM (0xe7ba53a4UL) > +#define MOD_GFG (0xfc423807UL) > +#define MOD_GMF (0x68b1d15aUL) > +#define MOD_GPIO_PHY (0xbbe81659UL) > +#define MOD_GPIO_PHY_PORTS (0xea12bddaUL) > +#define MOD_GPIO_SFPP (0x628c8692UL) > +#define MOD_HFU (0x4a70e72UL) > +#define MOD_HIF (0x7815363UL) > +#define MOD_HSH (0x501484bfUL) > +#define MOD_I2CM (0x93bc7780UL) > +#define MOD_IFR (0x9b01f1e6UL) > +#define MOD_IGAM (0xf3b0bfb9UL) > +#define MOD_IIC (0x7629cddbUL) > +#define MOD_INS (0x24df4b78UL) > +#define MOD_IOA (0xce7d0b71UL) > +#define MOD_IPF (0x9d43904cUL) > +#define MOD_KM (0xcfbd9dbeUL) > +#define MOD_MAC (0xb9f9ef0fUL) > +#define MOD_MAC_PCS (0x7abe24c7UL) > +#define MOD_MAC_PCS_XXV (0x3ea7bfeaUL) > +#define MOD_MAC_RX (0x6347b490UL) > +#define MOD_MAC_TFG (0x1a1aac23UL) > +#define MOD_MAC_TX (0x351d1316UL) > +#define MOD_MSK (0xcfd617eeUL) > +#define MOD_PCIE3 (0xfbc48c18UL) > +#define MOD_PCI_RD_TG (0x9ad9eed2UL) > +#define MOD_PCI_TA (0xfb431997UL) > +#define MOD_PCI_WR_TG (0x274b69e1UL) > +#define MOD_PCS (0x8286adcaUL) > +#define MOD_PCS100 (0xa03da74fUL) > +#define MOD_PDB (0xa7771bffUL) > +#define MOD_PDI (0x30a5c277UL) > +#define MOD_PHY_TILE (0x4e0aef6eUL) > +#define MOD_QSL (0x448ed859UL) > +#define MOD_QSPI (0x29862c6cUL) > +#define MOD_R2DRP (0x8b673fa6UL) > +#define MOD_RAC (0xae830b42UL) > +#define MOD_RFD (0x7fa60826UL) > +#define MOD_RMC (0x236444eUL) > +#define MOD_ROA (0xde0e47e0UL) > +#define MOD_RPF (0x8d30dcddUL) > +#define MOD_RPL (0x6de535c3UL) > +#define MOD_RPP_LR (0xba7f945cUL) > +#define MOD_RST9563 (0x385d6d1dUL) > +#define MOD_SDC (0xd2369530UL) > +#define MOD_SLC (0x1aef1f38UL) > +#define MOD_SLC_LR (0x969fc50bUL) > +#define MOD_SPIM (0x1da437bfUL) > +#define MOD_SPIS (0xe7ab0adcUL) > +#define MOD_STA (0x76fae64dUL) > +#define MOD_TEMPMON (0x2f77020dUL) > +#define MOD_TINT (0xb8aea9feUL) > +#define MOD_TSM (0x35422a24UL) > +#define MOD_TX_CPY (0x60acf217UL) > +#define MOD_TX_CSI (0x5636b1b0UL) > +#define MOD_TX_CSO (0xbf551485UL) > +#define MOD_TX_INS (0x59afa100UL) > +#define MOD_TX_RPL (0x1095dfbbUL) > +#define MOD_IDX_COUNT (69) > + > +/* aliases - only aliases go below this point */ > +#define MOD_MAC10 (MOD_MAC10G) /* alias */ > + > +#endif /* _NTHW_FPGA_MOD_DEFS_H_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c > b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c > new file mode 100644 > index 0000000000..51e5cf4649 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c > @@ -0,0 +1,78 @@ > + > + > +#include "nthw_fpga_mod_str_map.h" > +const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] =3D { { > MOD_CAT, "CAT" }, > + { MOD_CB, "CB" }, > + { MOD_COR, "COR" }, > + { MOD_CPY, "CPY" }, > + { MOD_CSU, "CSU" }, > + { MOD_DBS, "DBS" }, > + { MOD_DDP, "DDP" }, > + { MOD_EPP, "EPP" }, > + { MOD_EQM, "EQM" }, > + { MOD_FHM, "FHM" }, > + { MOD_FLM, "FLM" }, > + { MOD_GFG, "GFG" }, > + { MOD_GMF, "GMF" }, > + { MOD_GPIO_PHY, "GPIO_PHY" }, > + { > + MOD_GPIO_PHY_PORTS, > + "GPIO_PHY_PORTS" > + }, > + { MOD_GPIO_SFPP, "GPIO_SFPP" }, > + { MOD_HFU, "HFU" }, > + { MOD_HIF, "HIF" }, > + { MOD_HSH, "HSH" }, > + { MOD_I2CM, "I2CM" }, > + { MOD_IFR, "IFR" }, > + { MOD_IGAM, "IGAM" }, > + { MOD_IIC, "IIC" }, > + { MOD_INS, "INS" }, > + { MOD_IOA, "IOA" }, > + { MOD_IPF, "IPF" }, > + { MOD_KM, "KM" }, > + { MOD_MAC, "MAC" }, > + { MOD_MAC_PCS, "MAC_PCS" }, > + { MOD_MAC_PCS_XXV, "MAC_PCS_XXV" }, > + { MOD_MAC_RX, "MAC_RX" }, > + { MOD_MAC_TFG, "MAC_TFG" }, > + { MOD_MAC_TX, "MAC_TX" }, > + { MOD_MSK, "MSK" }, > + { MOD_PCIE3, "PCIE3" }, > + { MOD_PCI_RD_TG, "PCI_RD_TG" }, > + { MOD_PCI_TA, "PCI_TA" }, > + { MOD_PCI_WR_TG, "PCI_WR_TG" }, > + { MOD_PCS, "PCS" }, > + { MOD_PCS100, "PCS100" }, > + { MOD_PDB, "PDB" }, > + { MOD_PDI, "PDI" }, > + { MOD_PHY_TILE, "PHY_TILE" }, > + { MOD_QSL, "QSL" }, > + { MOD_QSPI, "QSPI" }, > + { MOD_R2DRP, "R2DRP" }, > + { MOD_RAC, "RAC" }, > + { MOD_RFD, "RFD" }, > + { MOD_RMC, "RMC" }, > + { MOD_ROA, "ROA" }, > + { MOD_RPF, "RPF" }, > + { MOD_RPL, "RPL" }, > + { MOD_RPP_LR, "RPP_LR" }, > + { MOD_RST9563, "RST9563" }, > + { MOD_SDC, "SDC" }, > + { MOD_SLC, "SLC" }, > + { MOD_SLC_LR, "SLC_LR" }, > + { MOD_SPIM, "SPIM" }, > + { MOD_SPIS, "SPIS" }, > + { MOD_STA, "STA" }, > + { MOD_TEMPMON, "TEMPMON" }, > + { MOD_TINT, "TINT" }, > + { MOD_TSM, "TSM" }, > + { MOD_TX_CPY, "TX_CPY" }, > + { MOD_TX_CSI, "TX_CSI" }, > + { MOD_TX_CSO, "TX_CSO" }, > + { MOD_TX_INS, "TX_INS" }, > + { MOD_TX_RPL, "TX_RPL" }, > + { 0UL, NULL } > +}; > + > +/* EOF */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h > new file mode 100644 > index 0000000000..6bebe56329 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h > @@ -0,0 +1,11 @@ > + > + > +#include "nthw_fpga_mod_defs.h" > +#include "fpga_model.h" > +struct nthw_fpga_mod_str_s { > + const nthw_id_t a; > + const char *b; > +}; > +extern const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[]; > + > +/* EOF */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h > new file mode 100644 > index 0000000000..a51d8b3888 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h > @@ -0,0 +1,232 @@ > +/* > + * nthw_fpga_param_defs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_PARAM_DEFS_ > +#define _NTHW_FPGA_PARAM_DEFS_ > + > +#define NTHW_PARAM_UNKNOWN (0UL) > +#define NT_BUILD_NUMBER (0x489b50fbUL) > +#define NT_BUILD_TIME (0x6e66771fUL) > +#define NT_CATEGORIES (0xfdbcebdcUL) > +#define NT_CAT_CCT_SIZE (0x3a505ddaUL) > +#define NT_CAT_CTE_SIZE (0x50a32ea4UL) > +#define NT_CAT_CTS_SIZE (0x852ccf22UL) > +#define NT_CAT_DCT_PRESENT (0x898c5638UL) > +#define NT_CAT_DCT_SIZE (0x309554c3UL) > +#define NT_CAT_END_OFS_SUPPORT (0x925f11d9UL) > +#define NT_CAT_FPC (0x417fd17bUL) > +#define NT_CAT_FTE_SIZE (0x184320c0UL) > +#define NT_CAT_FUNCS (0x6af66e16UL) > +#define NT_CAT_KCC_BANKS (0x426534f3UL) > +#define NT_CAT_KCC_PRESENT (0xd2d58d46UL) > +#define NT_CAT_KCC_SIZE (0xf766744cUL) > +#define NT_CAT_KCE_SIZE (0x213f9751UL) > +#define NT_CAT_KM_IF_CNT (0x8c934524UL) > +#define NT_CAT_KM_IF_M0 (0x666dd699UL) > +#define NT_CAT_KM_IF_M1 (0x116ae60fUL) > +#define NT_CAT_N_CMP (0x3a692ad4UL) > +#define NT_CAT_N_EXT (0xe3c746bUL) > +#define NT_CAT_N_LEN (0x3e3da82UL) > +#define NT_CAT_RCK_SIZE (0x78c1dc21UL) > +#define NT_CAT_VALUES (0xec523dbbUL) > +#define NT_CB_DEBUG (0xa0bccd31UL) > +#define NT_COR_CATEGORIES (0x7392b58dUL) > +#define NT_COR_PRESENT (0xbe0d1fdeUL) > +#define NT_CPY_MASK_MEM (0x24f85e48UL) > +#define NT_CSU_PRESENT (0xe7fe1371UL) > +#define NT_DBS_PRESENT (0x75b395aeUL) > +#define NT_DBS_RX_QUEUES (0x927069fUL) > +#define NT_DBS_TX_PORTS (0xae2d6250UL) > +#define NT_DBS_TX_QUEUES (0x7a3d7f15UL) > +#define NT_DDP_PRESENT (0x4120d92cUL) > +#define NT_DDP_TBL_DEPTH (0xf52e011UL) > +#define NT_EMI_SPLIT_STEPS (0xe4b3210fUL) > +#define NT_EOF_TIMESTAMP_ONLY (0xe476891bUL) > +#define NT_EPP_CATEGORIES (0xf41c134bUL) > +#define NT_EXT_MEM_NUM (0x43a48169UL) > +#define NT_EXT_MEM_SINGLE_SIZE_GB (0x1817e71eUL) > +#define NT_FLM_CACHE (0x414157e4UL) > +#define NT_FLM_CATEGORIES (0x3477c5a3UL) > +#define NT_FLM_ENTRY_SIZE (0x9ca7f0b6UL) > +#define NT_FLM_LOAD_APS_MAX (0xe4d4f4edUL) > +#define NT_FLM_LOAD_LPS_MAX (0x8503952dUL) > +#define NT_FLM_PRESENT (0x5714853fUL) > +#define NT_FLM_PRIOS (0x92afe487UL) > +#define NT_FLM_PST_PROFILES (0xf4a0d627UL) > +#define NT_FLM_SCRUB_PROFILES (0x6b6f6b21UL) > +#define NT_FLM_SIZE_MB (0x5667a5deUL) > +#define NT_FLM_STATEFUL (0xc8bf17a8UL) > +#define NT_FLM_VARIANT (0x5beb9485UL) > +#define NT_GFG_PRESENT (0x149640a8UL) > +#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (0x7b5ad1e0UL) > +#define NT_GMF_FCS_PRESENT (0xc15365efUL) > +#define NT_GMF_IFG_SPEED_DIV (0xc06cdcbdUL) > +#define NT_GMF_IFG_SPEED_DIV100G (0x43e1fb80UL) > +#define NT_GMF_IFG_SPEED_DIV100M (0xa334129eUL) > +#define NT_GMF_IFG_SPEED_DIV10G (0x49197e96UL) > +#define NT_GMF_IFG_SPEED_DIV1G (0xb1324f18UL) > +#define NT_GMF_IFG_SPEED_DIV2 (0xafc51de0UL) > +#define NT_GMF_IFG_SPEED_DIV25G (0x3628348aUL) > +#define NT_GMF_IFG_SPEED_DIV3 (0xd8c22d76UL) > +#define NT_GMF_IFG_SPEED_DIV4 (0x46a6b8d5UL) > +#define NT_GMF_IFG_SPEED_DIV40G (0x4fd2bc7dUL) > +#define NT_GMF_IFG_SPEED_DIV50G (0x4e10d64aUL) > +#define NT_GMF_IFG_SPEED_MUL (0xd4a84315UL) > +#define NT_GMF_IFG_SPEED_MUL100G (0x883df390UL) > +#define NT_GMF_IFG_SPEED_MUL100M (0x68e81a8eUL) > +#define NT_GMF_IFG_SPEED_MUL10G (0xf4a2e226UL) > +#define NT_GMF_IFG_SPEED_MUL1G (0xb75ce3e8UL) > +#define NT_GMF_IFG_SPEED_MUL2 (0x77dcf2a5UL) > +#define NT_GMF_IFG_SPEED_MUL25G (0x8b93a83aUL) > +#define NT_GMF_IFG_SPEED_MUL3 (0xdbc233UL) > +#define NT_GMF_IFG_SPEED_MUL4 (0x9ebf5790UL) > +#define NT_GMF_IFG_SPEED_MUL40G (0xf26920cdUL) > +#define NT_GMF_IFG_SPEED_MUL50G (0xf3ab4afaUL) > +#define NT_GROUP_ID (0x113978c5UL) > +#define NT_HFU_PRESENT (0x558de99UL) > +#define NT_HIF_MSIX_BAR (0xc10014e9UL) > +#define NT_HIF_MSIX_PBA_OFS (0x900307fbUL) > +#define NT_HIF_MSIX_PRESENT (0x77a98665UL) > +#define NT_HIF_MSIX_TBL_OFS (0x9cdce759UL) > +#define NT_HIF_MSIX_TBL_SIZE (0x6ce7b76UL) > +#define NT_HIF_PER_PS (0x38c954b1UL) > +#define NT_HIF_SRIOV_PRESENT (0x49f8c203UL) > +#define NT_HIF_VF_OFFSET (0x9fb3c9b0UL) > +#define NT_HSH_CATEGORIES (0xf43894dcUL) > +#define NT_HSH_TOEPLITZ (0x603f96a3UL) > +#define NT_HST_CATEGORIES (0xfd2a34a1UL) > +#define NT_HST_PRESENT (0xd3a48076UL) > +#define NT_IOA_CATEGORIES (0xda23501aUL) > +#define NT_IOA_PRESENT (0xc9ef39eeUL) > +#define NT_IPF_PRESENT (0x7b2b8e42UL) > +#define NT_KM_CAM_BANKS (0x3cad3371UL) > +#define NT_KM_CAM_RECORDS (0x24256ab5UL) > +#define NT_KM_CAM_REC_WORDS (0xe8e0ef3UL) > +#define NT_KM_CATEGORIES (0x4d2a4c96UL) > +#define NT_KM_END_OFS_SUPPORT (0x4a90ff33UL) > +#define NT_KM_EXT_EXTRACTORS (0xf135193cUL) > +#define NT_KM_FLOW_SETS (0x359cddf3UL) > +#define NT_KM_FLOW_TYPES (0xb79ff984UL) > +#define NT_KM_PRESENT (0xb54eaee3UL) > +#define NT_KM_SWX_PRESENT (0x2715aebeUL) > +#define NT_KM_SYNERGY_MATCH (0x935e5b7fUL) > +#define NT_KM_TCAM_BANKS (0x6f6f0894UL) > +#define NT_KM_TCAM_BANK_WIDTH (0x4c5015aeUL) > +#define NT_KM_TCAM_HIT_QUAL (0xd3fb2aafUL) > +#define NT_KM_TCAM_KEYWAY (0x45318c61UL) > +#define NT_KM_WIDE (0x7ba773c4UL) > +#define NT_LR_PRESENT (0x24eb383aUL) > +#define NT_LTX_CATEGORIES (0x9cfff063UL) > +#define NT_MCU_DRAM_SIZE (0xe33d7922UL) > +#define NT_MCU_PRESENT (0x9226b99fUL) > +#define NT_MCU_TYPE (0xce45b840UL) > +#define NT_MDG_DEBUG_FLOW_CONTROL (0x4f199a18UL) > +#define NT_MDG_DEBUG_REG_READ_BACK (0xc674095UL) > +#define NT_MSK_CATEGORIES (0x7052841UL) > +#define NT_MSK_PRESENT (0xd18aa194UL) > +#define NT_NAME (0x224bb693UL) > +#define NT_NFV_OVS_PRODUCT (0xd8223124UL) > +#define NT_NIMS (0xd88c527aUL) > +#define NT_PATCH_NUMBER (0xecd14417UL) > +#define NT_PCI_DEVICE_ID (0x254dede8UL) > +#define NT_PCI_INT_AVR (0x40c50ef1UL) > +#define NT_PCI_INT_EQM (0x85853d1fUL) > +#define NT_PCI_INT_IIC0 (0xbf363717UL) > +#define NT_PCI_INT_IIC1 (0xc8310781UL) > +#define NT_PCI_INT_IIC2 (0x5138563bUL) > +#define NT_PCI_INT_IIC3 (0x263f66adUL) > +#define NT_PCI_INT_IIC4 (0xb85bf30eUL) > +#define NT_PCI_INT_IIC5 (0xcf5cc398UL) > +#define NT_PCI_INT_PORT (0x8facd5e1UL) > +#define NT_PCI_INT_PORT0 (0x2359a11aUL) > +#define NT_PCI_INT_PORT1 (0x545e918cUL) > +#define NT_PCI_INT_PPS (0x7c7c50a6UL) > +#define NT_PCI_INT_QSPI (0x731ce6cbUL) > +#define NT_PCI_INT_SPIM (0x473efd18UL) > +#define NT_PCI_INT_SPIS (0xbd31c07bUL) > +#define NT_PCI_INT_STA (0xe9ef5ab3UL) > +#define NT_PCI_INT_TIMER (0x14ad9f2fUL) > +#define NT_PCI_INT_TINT (0xe2346359UL) > +#define NT_PCI_TA_TG_PRESENT (0x3cc176a0UL) > +#define NT_PCI_VENDOR_ID (0x47eac44fUL) > +#define NT_PDB_CATEGORIES (0x8290fe65UL) > +#define NT_PHY_ANEG_PRESENT (0x626ddda5UL) > +#define NT_PHY_KRFEC_PRESENT (0x8ab2cf25UL) > +#define NT_PHY_PORTS (0x41986112UL) > +#define NT_PHY_PORTS_PER_QUAD (0xf4b396e6UL) > +#define NT_PHY_QUADS (0x17fef021UL) > +#define NT_PHY_RSFEC_PRESENT (0x22852f78UL) > +#define NT_PORTS (0x32e8ff06UL) > +#define NT_PROD_ID_LAYOUT_VERSION (0x42106495UL) > +#define NT_QM_BLOCKS (0xb735e210UL) > +#define NT_QM_CELLS (0x510e07f1UL) > +#define NT_QM_CELL_SIZE (0xbddf0f74UL) > +#define NT_QM_PRESENT (0x85c2bfc2UL) > +#define NT_QSL_CATEGORIES (0x3fda6c8fUL) > +#define NT_QSL_COLOR_SEL_BW (0x549c264dUL) > +#define NT_QSL_QST_SIZE (0x41d03837UL) > +#define NT_QUEUES (0xf8a94e49UL) > +#define NT_RAC_RAB_INTERFACES (0x7b742b2bUL) > +#define NT_RAC_RAB_OB_UPDATE (0x3a44d066UL) > +#define NT_REVISION_ID (0xd212229fUL) > +#define NT_RMC_LAG_GROUPS (0xa7d5b2fbUL) > +#define NT_RMC_PRESENT (0x6e3b82daUL) > +#define NT_ROA_CATEGORIES (0xf3a9579bUL) > +#define NT_ROA_PRESENT (0x44387a61UL) > +#define NT_RPF_MATURING_DEL_DEFAULT (0xd4e7e4d2UL) > +#define NT_RPF_PRESENT (0xf6fccdcdUL) > +#define NT_RPP_PER_PS (0xb2f28916UL) > +#define NT_RTX_PRESENT (0x9b15f454UL) > +#define NT_RX_HOST_BUFFERS (0x9207c413UL) > +#define NT_RX_PORTS (0x3639a86eUL) > +#define NT_RX_PORT_REPLICATE (0xed09d794UL) > +#define NT_SLB_PRESENT (0x570c2267UL) > +#define NT_SLC_LR_PRESENT (0xe600975aUL) > +#define NT_SLC_PRESENT (0x40773624UL) > +#define NT_STA_COLORS (0xe1e90b5bUL) > +#define NT_STA_LOAD_AVG_RX (0x94efbfa1UL) > +#define NT_STA_LOAD_AVG_TX (0xc2b51827UL) > +#define NT_STA_RX_PORTS (0x75da30f9UL) > +#define NT_TBH_DEBUG_DLN (0x1faf2e1dUL) > +#define NT_TBH_PRESENT (0xf5d08dc9UL) > +#define NT_TFD_PRESENT (0x1a0fdea7UL) > +#define NT_TPE_CATEGORIES (0x9b1a54bdUL) > +#define NT_TSM_OST_ONLY (0x4899103aUL) > +#define NT_TS_APPEND (0x4544c692UL) > +#define NT_TS_INJECT_PRESENT (0xb2aa4f0eUL) > +#define NT_TX_CPY_PACKET_READERS (0x37f470f0UL) > +#define NT_TX_CPY_PRESENT (0xe54af81cUL) > +#define NT_TX_CPY_SIDEBAND_READERS (0x52220d68UL) > +#define NT_TX_CPY_VARIANT (0xe9b5e9a6UL) > +#define NT_TX_CPY_WRITERS (0xd9dbd4UL) > +#define NT_TX_HOST_BUFFERS (0xb0fd10e1UL) > +#define NT_TX_INS_OFS_ZERO (0x5510aa2dUL) > +#define NT_TX_INS_PRESENT (0xabac9b5dUL) > +#define NT_TX_MTU_PROFILE_IFR (0x8d313bc2UL) > +#define NT_TX_ON_TIMESTAMP (0x51d7fce0UL) > +#define NT_TX_PORTS (0xf056a1e9UL) > +#define NT_TX_PORT_REPLICATE (0x4a3d609cUL) > +#define NT_TX_RPL_DEPTH (0x61f86eb9UL) > +#define NT_TX_RPL_EXT_CATEGORIES (0x421e973cUL) > +#define NT_TX_RPL_OFS_ZERO (0x2bfd677UL) > +#define NT_TX_RPL_PRESENT (0x6c65e429UL) > +#define NT_TYPE_ID (0xd03446b2UL) > +#define NT_USE_TRIPLE_SPEED (0x54350589UL) > +#define NT_UUID (0xad179833UL) > +#define NT_VERSION (0x92295f02UL) > +#define NT_VERSION_ID (0xb4becc51UL) > +#define NT_VLI_PRESENT (0xa40e10f8UL) > + > +#endif /* _NTHW_FPGA_PARAM_DEFS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h > new file mode 100644 > index 0000000000..9b24398183 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h > @@ -0,0 +1,94 @@ > +/* > + * nthw_fpga_reg_defs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_ > +#define _NTHW_FPGA_REG_DEFS_ > + > +#include "nthw_fpga_reg_defs_cat.h" > +#include "nthw_fpga_reg_defs_cb.h" > +#include "nthw_fpga_reg_defs_cor.h" > +#include "nthw_fpga_reg_defs_cpy.h" > +#include "nthw_fpga_reg_defs_csu.h" > +#include "nthw_fpga_reg_defs_dbs.h" > +#include "nthw_fpga_reg_defs_ddp.h" > +#include "nthw_fpga_reg_defs_epp.h" > +#include "nthw_fpga_reg_defs_eqm.h" > +#include "nthw_fpga_reg_defs_fhm.h" > +#include "nthw_fpga_reg_defs_flm.h" > +#include "nthw_fpga_reg_defs_gfg.h" > +#include "nthw_fpga_reg_defs_gmf.h" > +#include "nthw_fpga_reg_defs_gpio_phy.h" > +#include "nthw_fpga_reg_defs_gpio_phy_ports.h" > +#include "nthw_fpga_reg_defs_gpio_sfpp.h" > +#include "nthw_fpga_reg_defs_hfu.h" > +#include "nthw_fpga_reg_defs_hif.h" > +#include "nthw_fpga_reg_defs_hsh.h" > +#include "nthw_fpga_reg_defs_i2cm.h" > +#include "nthw_fpga_reg_defs_ifr.h" > +#include "nthw_fpga_reg_defs_igam.h" > +#include "nthw_fpga_reg_defs_iic.h" > +#include "nthw_fpga_reg_defs_ins.h" > +#include "nthw_fpga_reg_defs_ioa.h" > +#include "nthw_fpga_reg_defs_ipf.h" > +#include "nthw_fpga_reg_defs_km.h" > +#include "nthw_fpga_reg_defs_mac.h" > +#include "nthw_fpga_reg_defs_mac_pcs.h" > +#include "nthw_fpga_reg_defs_mac_pcs_xxv.h" > +#include "nthw_fpga_reg_defs_mac_rx.h" > +#include "nthw_fpga_reg_defs_mac_tfg.h" > +#include "nthw_fpga_reg_defs_mac_tx.h" > +#include "nthw_fpga_reg_defs_msk.h" > +#include "nthw_fpga_reg_defs_pcie3.h" > +#include "nthw_fpga_reg_defs_pci_rd_tg.h" > +#include "nthw_fpga_reg_defs_pci_ta.h" > +#include "nthw_fpga_reg_defs_pci_wr_tg.h" > +#include "nthw_fpga_reg_defs_pcm_nt400dxx.h" > +#include "nthw_fpga_reg_defs_pcm_nt50b01_01.h" > +#include "nthw_fpga_reg_defs_pcs.h" > +#include "nthw_fpga_reg_defs_pcs100.h" > +#include "nthw_fpga_reg_defs_pdb.h" > +#include "nthw_fpga_reg_defs_pdi.h" > +#include "nthw_fpga_reg_defs_phy_tile.h" > +#include "nthw_fpga_reg_defs_prm_nt400dxx.h" > +#include "nthw_fpga_reg_defs_prm_nt50b01_01.h" > +#include "nthw_fpga_reg_defs_qsl.h" > +#include "nthw_fpga_reg_defs_qspi.h" > +#include "nthw_fpga_reg_defs_r2drp.h" > +#include "nthw_fpga_reg_defs_rac.h" > +#include "nthw_fpga_reg_defs_rfd.h" > +#include "nthw_fpga_reg_defs_rmc.h" > +#include "nthw_fpga_reg_defs_roa.h" > +#include "nthw_fpga_reg_defs_rpf.h" > +#include "nthw_fpga_reg_defs_rpl.h" > +#include "nthw_fpga_reg_defs_rpp_lr.h" > +#include "nthw_fpga_reg_defs_rst9563.h" > +#include "nthw_fpga_reg_defs_sdc.h" > +#include "nthw_fpga_reg_defs_slc.h" > +#include "nthw_fpga_reg_defs_slc_lr.h" > +#include "nthw_fpga_reg_defs_spim.h" > +#include "nthw_fpga_reg_defs_spis.h" > +#include "nthw_fpga_reg_defs_sta.h" > +#include "nthw_fpga_reg_defs_tempmon.h" > +#include "nthw_fpga_reg_defs_tint.h" > +#include "nthw_fpga_reg_defs_tsm.h" > +#include "nthw_fpga_reg_defs_tx_cpy.h" > +#include "nthw_fpga_reg_defs_tx_csi.h" > +#include "nthw_fpga_reg_defs_tx_cso.h" > +#include "nthw_fpga_reg_defs_tx_ins.h" > +#include "nthw_fpga_reg_defs_tx_rpl.h" > + > +/* aliases */ > + > +#endif /* NTHW_FPGA_REG_DEFS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h > new file mode 100644 > index 0000000000..1748a6cbb5 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h > @@ -0,0 +1,237 @@ > +/* > + * nthw_fpga_reg_defs_cat.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_CAT_ > +#define _NTHW_FPGA_REG_DEFS_CAT_ > + > +/* CAT */ > +#define NTHW_MOD_CAT (0x30b447c2UL) > +#define CAT_CCT_CTRL (0x234d3a78UL) > +#define CAT_CCT_CTRL_ADR (0x6146f230UL) > +#define CAT_CCT_CTRL_CNT (0x714e6be1UL) > +#define CAT_CCT_DATA (0x8c9cb861UL) > +#define CAT_CCT_DATA_COLOR (0x27e29b73UL) > +#define CAT_CCT_DATA_KM (0x4ac2435fUL) > +#define CAT_CFN_CTRL (0xd3383422UL) > +#define CAT_CFN_CTRL_ADR (0x209d4f53UL) > +#define CAT_CFN_CTRL_CNT (0x3095d682UL) > +#define CAT_CFN_DATA (0x7ce9b63bUL) > +#define CAT_CFN_DATA_ENABLE (0xd2ae88e2UL) > +#define CAT_CFN_DATA_ERR_CV (0x22ca6722UL) > +#define CAT_CFN_DATA_ERR_FCS (0xc45c40bfUL) > +#define CAT_CFN_DATA_ERR_INV (0xac48d40UL) > +#define CAT_CFN_DATA_ERR_L3_CS (0x55fb7895UL) > +#define CAT_CFN_DATA_ERR_L4_CS (0xc82c402cUL) > +#define CAT_CFN_DATA_ERR_TNL_L3_CS (0x51e668edUL) > +#define CAT_CFN_DATA_ERR_TNL_L4_CS (0xcc315054UL) > +#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (0x948d9686UL) > +#define CAT_CFN_DATA_ERR_TRUNC (0x237fdf4fUL) > +#define CAT_CFN_DATA_ERR_TTL_EXP (0x6edc7101UL) > +#define CAT_CFN_DATA_FLM_OR (0xd82cf0b3UL) > +#define CAT_CFN_DATA_INV (0xc2e6afa4UL) > +#define CAT_CFN_DATA_KM0_OR (0xc087b29cUL) > +#define CAT_CFN_DATA_KM1_OR (0x783bd5f9UL) > +#define CAT_CFN_DATA_KM_OR (0x58fbb39eUL) > +#define CAT_CFN_DATA_LC (0x3dfcfb34UL) > +#define CAT_CFN_DATA_LC_INV (0x72af18aUL) > +#define CAT_CFN_DATA_MAC_PORT (0xcd340483UL) > +#define CAT_CFN_DATA_PM_AND_INV (0x3ae1c6afUL) > +#define CAT_CFN_DATA_PM_CMB (0xf06e8f63UL) > +#define CAT_CFN_DATA_PM_CMP (0x3d7fe2bUL) > +#define CAT_CFN_DATA_PM_DCT (0x9f760139UL) > +#define CAT_CFN_DATA_PM_EXT_INV (0x7bc194b8UL) > +#define CAT_CFN_DATA_PM_INV (0xcc0e8d0bUL) > +#define CAT_CFN_DATA_PM_OR_INV (0x7790b2fUL) > +#define CAT_CFN_DATA_PTC_CFP (0x98d6c9edUL) > +#define CAT_CFN_DATA_PTC_FRAG (0x9bb1ab3cUL) > +#define CAT_CFN_DATA_PTC_INV (0xb4fb6306UL) > +#define CAT_CFN_DATA_PTC_IP_PROT (0xfee4889bUL) > +#define CAT_CFN_DATA_PTC_ISL (0xb6f5f660UL) > +#define CAT_CFN_DATA_PTC_L2 (0xdb7388deUL) > +#define CAT_CFN_DATA_PTC_L3 (0xac74b848UL) > +#define CAT_CFN_DATA_PTC_L4 (0x32102debUL) > +#define CAT_CFN_DATA_PTC_MAC (0x59b733feUL) > +#define CAT_CFN_DATA_PTC_MPLS (0xe0405263UL) > +#define CAT_CFN_DATA_PTC_TNL_FRAG (0x76e4a788UL) > +#define CAT_CFN_DATA_PTC_TNL_IP_PROT (0x8b0734cdUL) > +#define CAT_CFN_DATA_PTC_TNL_L2 (0xec64285eUL) > +#define CAT_CFN_DATA_PTC_TNL_L3 (0x9b6318c8UL) > +#define CAT_CFN_DATA_PTC_TNL_L4 (0x5078d6bUL) > +#define CAT_CFN_DATA_PTC_TNL_MPLS (0xd155ed7UL) > +#define CAT_CFN_DATA_PTC_TNL_VLAN (0x4999c6c9UL) > +#define CAT_CFN_DATA_PTC_TUNNEL (0x2ac66873UL) > +#define CAT_CFN_DATA_PTC_VLAN (0xa4ccca7dUL) > +#define CAT_CFN_DATA_PTC_VNTAG (0x23d64f2aUL) > +#define CAT_COT_CTRL (0xe4ed500cUL) > +#define CAT_COT_CTRL_ADR (0x6b5c60f7UL) > +#define CAT_COT_CTRL_CNT (0x7b54f926UL) > +#define CAT_COT_DATA (0x4b3cd215UL) > +#define CAT_COT_DATA_COLOR (0xbd582288UL) > +#define CAT_COT_DATA_KM (0x50fea3d1UL) > +#define CAT_COT_DATA_NFV_SB (0x2219c864UL) > +#define CAT_CTE_CTRL (0x49be4906UL) > +#define CAT_CTE_CTRL_ADR (0x2ee7c9aeUL) > +#define CAT_CTE_CTRL_CNT (0x3eef507fUL) > +#define CAT_CTE_DATA (0xe66fcb1fUL) > +#define CAT_CTE_DATA_COL_ENABLE (0xa9ca226bUL) > +#define CAT_CTE_DATA_COR_ENABLE (0xc0fb0172UL) > +#define CAT_CTE_DATA_EPP_ENABLE (0xfcb9fbe8UL) > +#define CAT_CTE_DATA_HSH_ENABLE (0x9f946603UL) > +#define CAT_CTE_DATA_HST_ENABLE (0xb4804267UL) > +#define CAT_CTE_DATA_IPF_ENABLE (0x5c5123caUL) > +#define CAT_CTE_DATA_MSK_ENABLE (0xf732aaa4UL) > +#define CAT_CTE_DATA_PDB_ENABLE (0xf28c946fUL) > +#define CAT_CTE_DATA_QSL_ENABLE (0xc065c2dbUL) > +#define CAT_CTE_DATA_SLC_ENABLE (0x6ec98deaUL) > +#define CAT_CTE_DATA_TPE_ENABLE (0x8e2e71UL) > +#define CAT_CTE_DATA_TX_INS_ENABLE (0x585922e3UL) > +#define CAT_CTE_DATA_TX_RPL_ENABLE (0x468ee298UL) > +#define CAT_CTS_CTRL (0x9c31a880UL) > +#define CAT_CTS_CTRL_ADR (0x4573801UL) > +#define CAT_CTS_CTRL_CNT (0x145fa1d0UL) > +#define CAT_CTS_DATA (0x33e02a99UL) > +#define CAT_CTS_DATA_CAT_A (0xa698040aUL) > +#define CAT_CTS_DATA_CAT_B (0x3f9155b0UL) > +#define CAT_DCT_CTRL (0x29883361UL) > +#define CAT_DCT_CTRL_ADR (0x15de1bbfUL) > +#define CAT_DCT_CTRL_CNT (0x5d6826eUL) > +#define CAT_DCT_DATA (0x8659b178UL) > +#define CAT_DCT_DATA_RES (0x74489a9dUL) > +#define CAT_DCT_SEL (0xeb603410UL) > +#define CAT_DCT_SEL_LU (0x60e126beUL) > +#define CAT_EXO_CTRL (0xe9ea0993UL) > +#define CAT_EXO_CTRL_ADR (0xdce26e40UL) > +#define CAT_EXO_CTRL_CNT (0xcceaf791UL) > +#define CAT_EXO_DATA (0x463b8b8aUL) > +#define CAT_EXO_DATA_DYN (0x20ae0124UL) > +#define CAT_EXO_DATA_OFS (0x82a78c82UL) > +#define CAT_FCE_CTRL (0xa327e522UL) > +#define CAT_FCE_CTRL_ADR (0x31896ff6UL) > +#define CAT_FCE_CTRL_CNT (0x2181f627UL) > +#define CAT_FCE_DATA (0xcf6673bUL) > +#define CAT_FCE_DATA_ENABLE (0x8243e7a7UL) > +#define CAT_FCS_CTRL (0x76a804a4UL) > +#define CAT_FCS_CTRL_ADR (0x1b399e59UL) > +#define CAT_FCS_CTRL_CNT (0xb310788UL) > +#define CAT_FCS_DATA (0xd97986bdUL) > +#define CAT_FCS_DATA_CATEGORY (0x69d964f3UL) > +#define CAT_FTE0_CTRL (0x4f655742UL) > +#define CAT_FTE0_CTRL_ADR (0xa786315fUL) > +#define CAT_FTE0_CTRL_CNT (0xb78ea88eUL) > +#define CAT_FTE0_DATA (0xe0b4d55bUL) > +#define CAT_FTE0_DATA_ENABLE (0xe06dec95UL) > +#define CAT_FTE1_CTRL (0x843984e7UL) > +#define CAT_FTE1_CTRL_ADR (0x48445a61UL) > +#define CAT_FTE1_CTRL_CNT (0x584cc3b0UL) > +#define CAT_FTE1_DATA (0x2be806feUL) > +#define CAT_FTE1_DATA_ENABLE (0x3dfb3510UL) > +#define CAT_FTE_CTRL (0x15e4762UL) > +#define CAT_FTE_CTRL_ADR (0xb644bebeUL) > +#define CAT_FTE_CTRL_CNT (0xa64c276fUL) > +#define CAT_FTE_DATA (0xae8fc57bUL) > +#define CAT_FTE_DATA_ENABLE (0x813c710bUL) > +#define CAT_FTE_FLM_CTRL (0x4a63f99eUL) > +#define CAT_FTE_FLM_CTRL_ADR (0x3ed2141dUL) > +#define CAT_FTE_FLM_CTRL_CNT (0x2eda8dccUL) > +#define CAT_FTE_FLM_DATA (0xe5b27b87UL) > +#define CAT_FTE_FLM_DATA_ENABLE (0x1786f0a8UL) > +#define CAT_JOIN (0xf643707UL) > +#define CAT_JOIN_J1 (0x494d06b2UL) > +#define CAT_JOIN_J2 (0xd0445708UL) > +#define CAT_KCC (0x26068f04UL) > +#define CAT_KCC_CTRL (0xee7b13eeUL) > +#define CAT_KCC_CTRL_ADR (0xa2381e5fUL) > +#define CAT_KCC_CTRL_CNT (0xb230878eUL) > +#define CAT_KCC_DATA (0x41aa91f7UL) > +#define CAT_KCC_DATA_CATEGORY (0x3f0558aeUL) > +#define CAT_KCC_DATA_ID (0x734a5784UL) > +#define CAT_KCC_DATA_KEY (0x308cee9cUL) > +#define CAT_KCE0_CTRL (0xc8548827UL) > +#define CAT_KCE0_CTRL_ADR (0x982a5552UL) > +#define CAT_KCE0_CTRL_CNT (0x8822cc83UL) > +#define CAT_KCE0_DATA (0x67850a3eUL) > +#define CAT_KCE0_DATA_ENABLE (0x36443e99UL) > +#define CAT_KCE1_CTRL (0x3085b82UL) > +#define CAT_KCE1_CTRL_ADR (0x77e83e6cUL) > +#define CAT_KCE1_CTRL_CNT (0x67e0a7bdUL) > +#define CAT_KCE1_DATA (0xacd9d99bUL) > +#define CAT_KCE1_DATA_ENABLE (0xebd2e71cUL) > +#define CAT_KCE_CTRL (0x3822f0f3UL) > +#define CAT_KCE_CTRL_ADR (0xaf266e18UL) > +#define CAT_KCE_CTRL_CNT (0xbf2ef7c9UL) > +#define CAT_KCE_DATA (0x97f372eaUL) > +#define CAT_KCE_DATA_ENABLE (0x7e4d95abUL) > +#define CAT_KCS0_CTRL (0xcc5a21d3UL) > +#define CAT_KCS0_CTRL_ADR (0xde695bdaUL) > +#define CAT_KCS0_CTRL_CNT (0xce61c20bUL) > +#define CAT_KCS0_DATA (0x638ba3caUL) > +#define CAT_KCS0_DATA_CATEGORY (0x43dbd3eUL) > +#define CAT_KCS1_CTRL (0x706f276UL) > +#define CAT_KCS1_CTRL_ADR (0x31ab30e4UL) > +#define CAT_KCS1_CTRL_CNT (0x21a3a935UL) > +#define CAT_KCS1_DATA (0xa8d7706fUL) > +#define CAT_KCS1_DATA_CATEGORY (0xbdc666d6UL) > +#define CAT_KCS_CTRL (0xedad1175UL) > +#define CAT_KCS_CTRL_ADR (0x85969fb7UL) > +#define CAT_KCS_CTRL_CNT (0x959e0666UL) > +#define CAT_KCS_DATA (0x427c936cUL) > +#define CAT_KCS_DATA_CATEGORY (0x7b67c7e1UL) > +#define CAT_LEN_CTRL (0x3bf03c13UL) > +#define CAT_LEN_CTRL_ADR (0xcbebb623UL) > +#define CAT_LEN_CTRL_CNT (0xdbe32ff2UL) > +#define CAT_LEN_DATA (0x9421be0aUL) > +#define CAT_LEN_DATA_DYN1 (0x6b539c5dUL) > +#define CAT_LEN_DATA_DYN2 (0xf25acde7UL) > +#define CAT_LEN_DATA_INV (0x299056d4UL) > +#define CAT_LEN_DATA_LOWER (0x5f70c60fUL) > +#define CAT_LEN_DATA_UPPER (0x3fb562b0UL) > +#define CAT_RCK_CTRL (0x61dcbb83UL) > +#define CAT_RCK_CTRL_ADR (0x205e89c6UL) > +#define CAT_RCK_CTRL_CNT (0x30561017UL) > +#define CAT_RCK_DATA (0xce0d399aUL) > +#define CAT_RCK_DATA_CM0U (0xc643fdb9UL) > +#define CAT_RCK_DATA_CM1U (0xdf58ccf8UL) > +#define CAT_RCK_DATA_CM2U (0xf4759f3bUL) > +#define CAT_RCK_DATA_CM3U (0xed6eae7aUL) > +#define CAT_RCK_DATA_CM4U (0xa22f38bdUL) > +#define CAT_RCK_DATA_CM5U (0xbb3409fcUL) > +#define CAT_RCK_DATA_CM6U (0x90195a3fUL) > +#define CAT_RCK_DATA_CM7U (0x89026b7eUL) > +#define CAT_RCK_DATA_CML0 (0x78115e94UL) > +#define CAT_RCK_DATA_CML1 (0xf166e02UL) > +#define CAT_RCK_DATA_CML2 (0x961f3fb8UL) > +#define CAT_RCK_DATA_CML3 (0xe1180f2eUL) > +#define CAT_RCK_DATA_CML4 (0x7f7c9a8dUL) > +#define CAT_RCK_DATA_CML5 (0x87baa1bUL) > +#define CAT_RCK_DATA_CML6 (0x9172fba1UL) > +#define CAT_RCK_DATA_CML7 (0xe675cb37UL) > +#define CAT_RCK_DATA_SEL0 (0x261b58b3UL) > +#define CAT_RCK_DATA_SEL1 (0x511c6825UL) > +#define CAT_RCK_DATA_SEL2 (0xc815399fUL) > +#define CAT_RCK_DATA_SEL3 (0xbf120909UL) > +#define CAT_RCK_DATA_SEL4 (0x21769caaUL) > +#define CAT_RCK_DATA_SEL5 (0x5671ac3cUL) > +#define CAT_RCK_DATA_SEL6 (0xcf78fd86UL) > +#define CAT_RCK_DATA_SEL7 (0xb87fcd10UL) > +#define CAT_RCK_DATA_SEU0 (0xbd1bf1abUL) > +#define CAT_RCK_DATA_SEU1 (0xca1cc13dUL) > +#define CAT_RCK_DATA_SEU2 (0x53159087UL) > +#define CAT_RCK_DATA_SEU3 (0x2412a011UL) > +#define CAT_RCK_DATA_SEU4 (0xba7635b2UL) > +#define CAT_RCK_DATA_SEU5 (0xcd710524UL) > +#define CAT_RCK_DATA_SEU6 (0x5478549eUL) > +#define CAT_RCK_DATA_SEU7 (0x237f6408UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_CAT_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h > new file mode 100644 > index 0000000000..6389754e68 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h > @@ -0,0 +1,73 @@ > +/* > + * nthw_fpga_reg_defs_cb.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_CB_ > +#define _NTHW_FPGA_REG_DEFS_CB_ > + > +/* CB */ > +#define NTHW_MOD_CB (0x97db0a27UL) > +#define CB_CTRL (0xea0f0d6UL) > +#define CB_CTRL_BP (0x2fd8c552UL) > +#define CB_CTRL_BYPASS (0xe1a5ba2dUL) > +#define CB_CTRL_ENABLE (0xfd0df46bUL) > +#define CB_CTRL_QMA (0xb79f07a3UL) > +#define CB_CTRL_QME (0xb0f2c3baUL) > +#define CB_DBG_BP (0x92018b7UL) > +#define CB_DBG_BP_CNT (0x6f41db03UL) > +#define CB_DBG_DQ (0x287d8fa7UL) > +#define CB_DBG_DQ_MAX (0xc86c40UL) > +#define CB_DBG_EGS_QUEUE (0x98831815UL) > +#define CB_DBG_EGS_QUEUE_ADD (0x6edd6af5UL) > +#define CB_DBG_EGS_QUEUE_AND (0x9432827fUL) > +#define CB_DBG_FREE1200 (0x3ca31ccUL) > +#define CB_DBG_FREE1200_CNT (0xa0a77389UL) > +#define CB_DBG_FREE1800 (0xe5db41aUL) > +#define CB_DBG_FREE1800_CNT (0x4d72cc7UL) > +#define CB_DBG_FREE600 (0x44c0c493UL) > +#define CB_DBG_FREE600_CNT (0x9291e1ffUL) > +#define CB_DBG_H16 (0x39c5a313UL) > +#define CB_DBG_H16_CNT (0x619373a5UL) > +#define CB_DBG_H32 (0xc9e0588UL) > +#define CB_DBG_H32_CNT (0xd9db746eUL) > +#define CB_DBG_H64 (0x988a54f8UL) > +#define CB_DBG_H64_CNT (0x656107dUL) > +#define CB_DBG_HAVE (0x613fdd18UL) > +#define CB_DBG_HAVE_CNT (0x631e610fUL) > +#define CB_DBG_IGS_QUEUE (0x7eb7eb01UL) > +#define CB_DBG_IGS_QUEUE_ADD (0xf467d30eUL) > +#define CB_DBG_IGS_QUEUE_AND (0xe883b84UL) > +#define CB_DBG_QM_CELL_CNT (0x72b9e681UL) > +#define CB_DBG_QM_CELL_CNT_CNT (0x620fbb43UL) > +#define CB_DBG_QM_CELL_XOR (0x92b23e64UL) > +#define CB_DBG_QM_CELL_XOR_XOR (0xa3c18d97UL) > +#define CB_QPM_CTRL (0xd4e2d7ecUL) > +#define CB_QPM_CTRL_ADR (0xf81800a9UL) > +#define CB_QPM_CTRL_CNT (0xe8109978UL) > +#define CB_QPM_DATA (0x7b3355f5UL) > +#define CB_QPM_DATA_P (0x537f8197UL) > +#define CB_QUEUE_MAX (0x3edbf10bUL) > +#define CB_QUEUE_MAX_MAX (0x55932199UL) > +#define CB_STATUS (0x4de72da7UL) > +#define CB_STATUS_BP (0xa6c5a817UL) > +#define CB_STATUS_DB (0x3267ed9UL) > +#define CB_STATUS_EMPTY (0xdb77607dUL) > +#define CB_STATUS_IDLE (0xa0322cdUL) > +#define CB_STATUS_OVF (0x904a7f92UL) > +#define CB_TS_RATE (0xea3c6e96UL) > +#define CB_TS_RATE_CNT (0xf8c7e925UL) > +#define CB_TS_SAVE (0x60b66b71UL) > +#define CB_TS_SAVE_MAX (0xfd15355eUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_CB_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h > new file mode 100644 > index 0000000000..e033672590 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h > @@ -0,0 +1,81 @@ > +/* > + * nthw_fpga_reg_defs_cor.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_COR_ > +#define _NTHW_FPGA_REG_DEFS_COR_ > + > +/* COR */ > +#define NTHW_MOD_COR (0x4754cf79UL) > +#define COR_CTRL (0xa34106eaUL) > +#define COR_CTRL_EN (0x220ce67aUL) > +#define COR_DBG_COR_CNT (0xeb30470fUL) > +#define COR_DBG_COR_CNT_VAL (0x5ab8a0fcUL) > +#define COR_DBG_COR_ID (0x2b214123UL) > +#define COR_DBG_COR_ID_VAL (0x7c6c2d68UL) > +#define COR_DBG_COR_LO (0xc1846ceeUL) > +#define COR_DBG_COR_LO_VAL (0x5b718dcaUL) > +#define COR_DBG_COR_UP (0xd78cc803UL) > +#define COR_DBG_COR_UP_VAL (0x9d18decaUL) > +#define COR_DCEO (0xbb755e8aUL) > +#define COR_DCEO_VAL (0x75ad94beUL) > +#define COR_DCSO (0xa7edeb5dUL) > +#define COR_DCSO_VAL (0xa0227538UL) > +#define COR_DEEO (0xbff82238UL) > +#define COR_DEEO_VAL (0x167da184UL) > +#define COR_DEO (0xc7fcb744UL) > +#define COR_DEO_VAL (0xf6fef8b1UL) > +#define COR_DESO (0xa36097efUL) > +#define COR_DESO_VAL (0xc3f24002UL) > +#define COR_DSEO (0xa753fdfaUL) > +#define COR_DSEO_VAL (0x12730870UL) > +#define COR_DSO (0xdb640293UL) > +#define COR_DSO_VAL (0x23711937UL) > +#define COR_DSSO (0xbbcb482dUL) > +#define COR_DSSO_VAL (0xc7fce9f6UL) > +#define COR_RCP_CTRL (0x57a5129aUL) > +#define COR_RCP_CTRL_ADR (0xeaa1a01aUL) > +#define COR_RCP_CTRL_CNT (0xfaa939cbUL) > +#define COR_RCP_DATA (0xf8749083UL) > +#define COR_RCP_DATA_CBM1 (0x92fe79a8UL) > +#define COR_RCP_DATA_EN (0x14a2ff31UL) > +#define COR_RCP_DATA_END_PROT (0xd9954b3eUL) > +#define COR_RCP_DATA_END_STATIC (0xc6775c54UL) > +#define COR_RCP_DATA_IP_CHK (0xc1aee6c3UL) > +#define COR_RCP_DATA_IP_DSCP (0xfeb87db5UL) > +#define COR_RCP_DATA_IP_DST (0xe0df3629UL) > +#define COR_RCP_DATA_IP_ECN (0x56bdb735UL) > +#define COR_RCP_DATA_IP_FLAGS (0xef2854ecUL) > +#define COR_RCP_DATA_IP_FLOW (0x711a8bdcUL) > +#define COR_RCP_DATA_IP_HOP (0x8df5609UL) > +#define COR_RCP_DATA_IP_IDENT (0xe0636de4UL) > +#define COR_RCP_DATA_IP_NXTHDR (0xee1f8e7bUL) > +#define COR_RCP_DATA_IP_SRC (0x637e375aUL) > +#define COR_RCP_DATA_IP_TC (0x52c0454dUL) > +#define COR_RCP_DATA_IP_TTL (0xa0d49bc8UL) > +#define COR_RCP_DATA_MAX_LEN (0x4c6afabeUL) > +#define COR_RCP_DATA_PROT_OFS1 (0x875455efUL) > +#define COR_RCP_DATA_START_PROT (0xaf6a6510UL) > +#define COR_RCP_DATA_START_STATIC (0x11a62e48UL) > +#define COR_RCP_DATA_STTC_OFS1 (0x3bc9abaUL) > +#define COR_RCP_DATA_TCP_CHK (0xd0c0496UL) > +#define COR_RCP_DATA_TCP_DST (0x2c7dd47cUL) > +#define COR_RCP_DATA_TCP_SEQ (0x59e620d1UL) > +#define COR_RCP_DATA_TCP_SRC (0xafdcd50fUL) > +#define COR_RCP_DATA_TNL (0xe14689b4UL) > +#define COR_RCP_DATA_UDP_CHK (0xb67e3f9aUL) > +#define COR_RCP_DATA_UDP_DST (0x970fef70UL) > +#define COR_RCP_DATA_UDP_SRC (0x14aeee03UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_COR_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h > new file mode 100644 > index 0000000000..88b23c3de1 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h > @@ -0,0 +1,112 @@ > +/* > + * nthw_fpga_reg_defs_cpy.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_CPY_ > +#define _NTHW_FPGA_REG_DEFS_CPY_ > + > +/* CPY */ > +#define NTHW_MOD_CPY (0x1ddc186fUL) > +#define CPY_PACKET_READER0_CTRL (0x59359b7UL) > +#define CPY_PACKET_READER0_CTRL_ADR (0xc84f1475UL) > +#define CPY_PACKET_READER0_CTRL_CNT (0xd8478da4UL) > +#define CPY_PACKET_READER0_DATA (0xaa42dbaeUL) > +#define CPY_PACKET_READER0_DATA_DYN (0x34037b11UL) > +#define CPY_PACKET_READER0_DATA_OFS (0x960af6b7UL) > +#define CPY_WRITER0_CTRL (0xe9b3268eUL) > +#define CPY_WRITER0_CTRL_ADR (0x26f906c2UL) > +#define CPY_WRITER0_CTRL_CNT (0x36f19f13UL) > +#define CPY_WRITER0_DATA (0x4662a497UL) > +#define CPY_WRITER0_DATA_DYN (0xdab569a6UL) > +#define CPY_WRITER0_DATA_LEN (0x32d16543UL) > +#define CPY_WRITER0_DATA_MASK_POINTER (0x64db2b2dUL) > +#define CPY_WRITER0_DATA_OFS (0x78bce400UL) > +#define CPY_WRITER0_DATA_READER_SELECT (0x63a38cf9UL) > +#define CPY_WRITER0_MASK_CTRL (0xed52c5f9UL) > +#define CPY_WRITER0_MASK_CTRL_ADR (0x3bbdf6aaUL) > +#define CPY_WRITER0_MASK_CTRL_CNT (0x2bb56f7bUL) > +#define CPY_WRITER0_MASK_DATA (0x428347e0UL) > +#define CPY_WRITER0_MASK_DATA_BYTE_MASK (0xd1d0e256UL) > +#define CPY_WRITER1_CTRL (0x22eff52bUL) > +#define CPY_WRITER1_CTRL_ADR (0xc93b6dfcUL) > +#define CPY_WRITER1_CTRL_CNT (0xd933f42dUL) > +#define CPY_WRITER1_DATA (0x8d3e7732UL) > +#define CPY_WRITER1_DATA_DYN (0x35770298UL) > +#define CPY_WRITER1_DATA_LEN (0xdd130e7dUL) > +#define CPY_WRITER1_DATA_MASK_POINTER (0xb339ab75UL) > +#define CPY_WRITER1_DATA_OFS (0x977e8f3eUL) > +#define CPY_WRITER1_DATA_READER_SELECT (0x6c4b7bfUL) > +#define CPY_WRITER1_MASK_CTRL (0x2cdc1a39UL) > +#define CPY_WRITER1_MASK_CTRL_ADR (0x82462d42UL) > +#define CPY_WRITER1_MASK_CTRL_CNT (0x924eb493UL) > +#define CPY_WRITER1_MASK_DATA (0x830d9820UL) > +#define CPY_WRITER1_MASK_DATA_BYTE_MASK (0x4e0a61c8UL) > +#define CPY_WRITER2_CTRL (0xa47b8785UL) > +#define CPY_WRITER2_CTRL_ADR (0x220cd6ffUL) > +#define CPY_WRITER2_CTRL_CNT (0x32044f2eUL) > +#define CPY_WRITER2_DATA (0xbaa059cUL) > +#define CPY_WRITER2_DATA_DYN (0xde40b99bUL) > +#define CPY_WRITER2_DATA_LEN (0x3624b57eUL) > +#define CPY_WRITER2_DATA_MASK_POINTER (0x106f2ddcUL) > +#define CPY_WRITER2_DATA_OFS (0x7c49343dUL) > +#define CPY_WRITER2_DATA_READER_SELECT (0xa96dfa75UL) > +#define CPY_WRITER2_MASK_CTRL (0xb53e7c38UL) > +#define CPY_WRITER2_MASK_CTRL_ADR (0x933b473bUL) > +#define CPY_WRITER2_MASK_CTRL_CNT (0x8333deeaUL) > +#define CPY_WRITER2_MASK_DATA (0x1aeffe21UL) > +#define CPY_WRITER2_MASK_DATA_BYTE_MASK (0x3514e32bUL) > +#define CPY_WRITER3_CTRL (0x6f275420UL) > +#define CPY_WRITER3_CTRL_ADR (0xcdcebdc1UL) > +#define CPY_WRITER3_CTRL_CNT (0xddc62410UL) > +#define CPY_WRITER3_DATA (0xc0f6d639UL) > +#define CPY_WRITER3_DATA_DYN (0x3182d2a5UL) > +#define CPY_WRITER3_DATA_LEN (0xd9e6de40UL) > +#define CPY_WRITER3_DATA_MASK_POINTER (0xc78dad84UL) > +#define CPY_WRITER3_DATA_OFS (0x938b5f03UL) > +#define CPY_WRITER3_DATA_READER_SELECT (0xcc0ac133UL) > +#define CPY_WRITER3_MASK_CTRL (0x74b0a3f8UL) > +#define CPY_WRITER3_MASK_CTRL_ADR (0x2ac09cd3UL) > +#define CPY_WRITER3_MASK_CTRL_CNT (0x3ac80502UL) > +#define CPY_WRITER3_MASK_DATA (0xdb6121e1UL) > +#define CPY_WRITER3_MASK_DATA_BYTE_MASK (0xaace60b5UL) > +#define CPY_WRITER4_CTRL (0x72226498UL) > +#define CPY_WRITER4_CTRL_ADR (0x2f12a6b8UL) > +#define CPY_WRITER4_CTRL_CNT (0x3f1a3f69UL) > +#define CPY_WRITER4_DATA (0xddf3e681UL) > +#define CPY_WRITER4_DATA_DYN (0xd35ec9dcUL) > +#define CPY_WRITER4_DATA_LEN (0x3b3ac539UL) > +#define CPY_WRITER4_DATA_MASK_POINTER (0x8db326cfUL) > +#define CPY_WRITER4_DATA_OFS (0x7157447aUL) > +#define CPY_WRITER4_DATA_READER_SELECT (0x2d4e67a0UL) > +#define CPY_WRITER4_MASK_CTRL (0x5d8bb67bUL) > +#define CPY_WRITER4_MASK_CTRL_ADR (0xb1c193c9UL) > +#define CPY_WRITER4_MASK_CTRL_CNT (0xa1c90a18UL) > +#define CPY_WRITER4_MASK_DATA (0xf25a3462UL) > +#define CPY_WRITER4_MASK_DATA_BYTE_MASK (0xc329e6edUL) > +#define CPY_WRITER5_CTRL (0xb97eb73dUL) > +#define CPY_WRITER5_CTRL_ADR (0xc0d0cd86UL) > +#define CPY_WRITER5_CTRL_CNT (0xd0d85457UL) > +#define CPY_WRITER5_DATA (0x16af3524UL) > +#define CPY_WRITER5_DATA_DYN (0x3c9ca2e2UL) > +#define CPY_WRITER5_DATA_LEN (0xd4f8ae07UL) > +#define CPY_WRITER5_DATA_MASK_POINTER (0x5a51a697UL) > +#define CPY_WRITER5_DATA_OFS (0x9e952f44UL) > +#define CPY_WRITER5_DATA_READER_SELECT (0x48295ce6UL) > +#define CPY_WRITER5_MASK_CTRL (0x9c0569bbUL) > +#define CPY_WRITER5_MASK_CTRL_ADR (0x83a4821UL) > +#define CPY_WRITER5_MASK_CTRL_CNT (0x1832d1f0UL) > +#define CPY_WRITER5_MASK_DATA (0x33d4eba2UL) > +#define CPY_WRITER5_MASK_DATA_BYTE_MASK (0x5cf36573UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_CPY_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h > new file mode 100644 > index 0000000000..eb68ccab33 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h > @@ -0,0 +1,30 @@ > +/* > + * nthw_fpga_reg_defs_csu.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_CSU_ > +#define _NTHW_FPGA_REG_DEFS_CSU_ > + > +/* CSU */ > +#define NTHW_MOD_CSU (0x3f470787UL) > +#define CSU_RCP_CTRL (0x11955fefUL) > +#define CSU_RCP_CTRL_ADR (0x8efb3c71UL) > +#define CSU_RCP_CTRL_CNT (0x9ef3a5a0UL) > +#define CSU_RCP_DATA (0xbe44ddf6UL) > +#define CSU_RCP_DATA_IL3_CMD (0xdbac8e0dUL) > +#define CSU_RCP_DATA_IL4_CMD (0x698c521dUL) > +#define CSU_RCP_DATA_OL3_CMD (0xb87cbb37UL) > +#define CSU_RCP_DATA_OL4_CMD (0xa5c6727UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_CSU_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h > new file mode 100644 > index 0000000000..2ff31fdf4d > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h > @@ -0,0 +1,144 @@ > +/* > + * nthw_fpga_reg_defs_dbs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_DBS_ > +#define _NTHW_FPGA_REG_DEFS_DBS_ > + > +/* DBS */ > +#define NTHW_MOD_DBS (0x80b29727UL) > +#define DBS_RX_AM_CTRL (0x7359feUL) > +#define DBS_RX_AM_CTRL_ADR (0x4704a1UL) > +#define DBS_RX_AM_CTRL_CNT (0x104f9d70UL) > +#define DBS_RX_AM_DATA (0xafa2dbe7UL) > +#define DBS_RX_AM_DATA_ENABLE (0x11658278UL) > +#define DBS_RX_AM_DATA_GPA (0xbf307344UL) > +#define DBS_RX_AM_DATA_HID (0x5f0669eeUL) > +#define DBS_RX_AM_DATA_INT (0xc32857aUL) > +#define DBS_RX_AM_DATA_PCKED (0x7d840fb4UL) > +#define DBS_RX_CONTROL (0xb18b2866UL) > +#define DBS_RX_CONTROL_AME (0x1f9219acUL) > +#define DBS_RX_CONTROL_AMS (0xeb46acfdUL) > +#define DBS_RX_CONTROL_LQ (0xe65f90b2UL) > +#define DBS_RX_CONTROL_QE (0x3e928d3UL) > +#define DBS_RX_CONTROL_UWE (0xb490e8dbUL) > +#define DBS_RX_CONTROL_UWS (0x40445d8aUL) > +#define DBS_RX_DR_CTRL (0xa0cbc617UL) > +#define DBS_RX_DR_CTRL_ADR (0xa7b57286UL) > +#define DBS_RX_DR_CTRL_CNT (0xb7bdeb57UL) > +#define DBS_RX_DR_DATA (0xf1a440eUL) > +#define DBS_RX_DR_DATA_GPA (0x18c20563UL) > +#define DBS_RX_DR_DATA_HDR (0xb98ed4d5UL) > +#define DBS_RX_DR_DATA_HID (0xf8f41fc9UL) > +#define DBS_RX_DR_DATA_PCKED (0x1e27ce2aUL) > +#define DBS_RX_DR_DATA_QS (0xffb980ddUL) > +#define DBS_RX_IDLE (0x93c723bfUL) > +#define DBS_RX_IDLE_BUSY (0x8e043b5bUL) > +#define DBS_RX_IDLE_IDLE (0x9dba27ccUL) > +#define DBS_RX_IDLE_QUEUE (0xbbddab49UL) > +#define DBS_RX_INIT (0x899772deUL) > +#define DBS_RX_INIT_BUSY (0x8576d90aUL) > +#define DBS_RX_INIT_INIT (0x8c9894fcUL) > +#define DBS_RX_INIT_QUEUE (0xa7bab8c9UL) > +#define DBS_RX_INIT_VAL (0x7789b4d8UL) > +#define DBS_RX_INIT_VAL_IDX (0xead0e2beUL) > +#define DBS_RX_INIT_VAL_PTR (0x5330810eUL) > +#define DBS_RX_PTR (0x628ce523UL) > +#define DBS_RX_PTR_PTR (0x7f834481UL) > +#define DBS_RX_PTR_QUEUE (0x4f3fa6d1UL) > +#define DBS_RX_PTR_VALID (0xbcc5ec4dUL) > +#define DBS_RX_UW_CTRL (0x31afc0deUL) > +#define DBS_RX_UW_CTRL_ADR (0x2ee4a2c9UL) > +#define DBS_RX_UW_CTRL_CNT (0x3eec3b18UL) > +#define DBS_RX_UW_DATA (0x9e7e42c7UL) > +#define DBS_RX_UW_DATA_GPA (0x9193d52cUL) > +#define DBS_RX_UW_DATA_HID (0x71a5cf86UL) > +#define DBS_RX_UW_DATA_INT (0x22912312UL) > +#define DBS_RX_UW_DATA_ISTK (0xd469a7ddUL) > +#define DBS_RX_UW_DATA_PCKED (0xef15c665UL) > +#define DBS_RX_UW_DATA_QS (0x7d422f44UL) > +#define DBS_RX_UW_DATA_VEC (0x55cc9b53UL) > +#define DBS_STATUS (0xb5f35220UL) > +#define DBS_STATUS_OK (0xcf09a30fUL) > +#define DBS_TX_AM_CTRL (0xd6d29b9UL) > +#define DBS_TX_AM_CTRL_ADR (0xf8854f17UL) > +#define DBS_TX_AM_CTRL_CNT (0xe88dd6c6UL) > +#define DBS_TX_AM_DATA (0xa2bcaba0UL) > +#define DBS_TX_AM_DATA_ENABLE (0xb6513570UL) > +#define DBS_TX_AM_DATA_GPA (0x47f238f2UL) > +#define DBS_TX_AM_DATA_HID (0xa7c42258UL) > +#define DBS_TX_AM_DATA_INT (0xf4f0ceccUL) > +#define DBS_TX_AM_DATA_PCKED (0x2e156650UL) > +#define DBS_TX_CONTROL (0xbc955821UL) > +#define DBS_TX_CONTROL_AME (0xe750521aUL) > +#define DBS_TX_CONTROL_AMS (0x1384e74bUL) > +#define DBS_TX_CONTROL_LQ (0x46ba4f6fUL) > +#define DBS_TX_CONTROL_QE (0xa30cf70eUL) > +#define DBS_TX_CONTROL_UWE (0x4c52a36dUL) > +#define DBS_TX_CONTROL_UWS (0xb886163cUL) > +#define DBS_TX_DR_CTRL (0xadd5b650UL) > +#define DBS_TX_DR_CTRL_ADR (0x5f773930UL) > +#define DBS_TX_DR_CTRL_CNT (0x4f7fa0e1UL) > +#define DBS_TX_DR_DATA (0x2043449UL) > +#define DBS_TX_DR_DATA_GPA (0xe0004ed5UL) > +#define DBS_TX_DR_DATA_HDR (0x414c9f63UL) > +#define DBS_TX_DR_DATA_HID (0x36547fUL) > +#define DBS_TX_DR_DATA_PCKED (0x4db6a7ceUL) > +#define DBS_TX_DR_DATA_PORT (0xf306968cUL) > +#define DBS_TX_DR_DATA_QS (0x5f5c5f00UL) > +#define DBS_TX_IDLE (0xf0171685UL) > +#define DBS_TX_IDLE_BUSY (0x61399ebbUL) > +#define DBS_TX_IDLE_IDLE (0x7287822cUL) > +#define DBS_TX_IDLE_QUEUE (0x1b387494UL) > +#define DBS_TX_INIT (0xea4747e4UL) > +#define DBS_TX_INIT_BUSY (0x6a4b7ceaUL) > +#define DBS_TX_INIT_INIT (0x63a5311cUL) > +#define DBS_TX_INIT_QUEUE (0x75f6714UL) > +#define DBS_TX_INIT_VAL (0x9f3c7e9bUL) > +#define DBS_TX_INIT_VAL_IDX (0xc82a364cUL) > +#define DBS_TX_INIT_VAL_PTR (0x71ca55fcUL) > +#define DBS_TX_PTR (0xb4d5063eUL) > +#define DBS_TX_PTR_PTR (0x729d34c6UL) > +#define DBS_TX_PTR_QUEUE (0xa0020331UL) > +#define DBS_TX_PTR_VALID (0x53f849adUL) > +#define DBS_TX_QOS_CTRL (0x3b2c3286UL) > +#define DBS_TX_QOS_CTRL_ADR (0x666600acUL) > +#define DBS_TX_QOS_CTRL_CNT (0x766e997dUL) > +#define DBS_TX_QOS_DATA (0x94fdb09fUL) > +#define DBS_TX_QOS_DATA_BS (0x2c394071UL) > +#define DBS_TX_QOS_DATA_EN (0x7eba6fUL) > +#define DBS_TX_QOS_DATA_IR (0xb8caa92cUL) > +#define DBS_TX_QOS_DATA_MUL (0xd7407a67UL) > +#define DBS_TX_QOS_RATE (0xe6e27cc5UL) > +#define DBS_TX_QOS_RATE_DIV (0x8cd07ba3UL) > +#define DBS_TX_QOS_RATE_MUL (0x9814e40bUL) > +#define DBS_TX_QP_CTRL (0xd5fba432UL) > +#define DBS_TX_QP_CTRL_ADR (0x84238184UL) > +#define DBS_TX_QP_CTRL_CNT (0x942b1855UL) > +#define DBS_TX_QP_DATA (0x7a2a262bUL) > +#define DBS_TX_QP_DATA_VPORT (0xda741d67UL) > +#define DBS_TX_UW_CTRL (0x3cb1b099UL) > +#define DBS_TX_UW_CTRL_ADR (0xd626e97fUL) > +#define DBS_TX_UW_CTRL_CNT (0xc62e70aeUL) > +#define DBS_TX_UW_DATA (0x93603280UL) > +#define DBS_TX_UW_DATA_GPA (0x69519e9aUL) > +#define DBS_TX_UW_DATA_HID (0x89678430UL) > +#define DBS_TX_UW_DATA_INO (0x5036a148UL) > +#define DBS_TX_UW_DATA_INT (0xda5368a4UL) > +#define DBS_TX_UW_DATA_ISTK (0xf693732fUL) > +#define DBS_TX_UW_DATA_PCKED (0xbc84af81UL) > +#define DBS_TX_UW_DATA_QS (0xdda7f099UL) > +#define DBS_TX_UW_DATA_VEC (0xad0ed0e5UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_DBS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h > new file mode 100644 > index 0000000000..88ed30f494 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h > @@ -0,0 +1,34 @@ > +/* > + * nthw_fpga_reg_defs_ddp.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_DDP_ > +#define _NTHW_FPGA_REG_DEFS_DDP_ > + > +/* DDP */ > +#define NTHW_MOD_DDP (0x4fe1611bUL) > +#define DDP_AGING_CTRL (0x85ef88bbUL) > +#define DDP_AGING_CTRL_AGING_RATE (0x410fda66UL) > +#define DDP_AGING_CTRL_MAX_CNT (0x2d5ac5adUL) > +#define DDP_CTRL (0xe64bfa02UL) > +#define DDP_CTRL_INIT (0x8e86234cUL) > +#define DDP_CTRL_INIT_DONE (0x14a11a6bUL) > +#define DDP_RCP_CTRL (0x4e9ac6cUL) > +#define DDP_RCP_CTRL_ADR (0x28c23a3cUL) > +#define DDP_RCP_CTRL_CNT (0x38caa3edUL) > +#define DDP_RCP_DATA (0xab382e75UL) > +#define DDP_RCP_DATA_EN (0xa0c77e8dUL) > +#define DDP_RCP_DATA_GROUPID (0xc71ed409UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_DDP_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h > new file mode 100644 > index 0000000000..fc181e461b > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h > @@ -0,0 +1,64 @@ > +/* > + * nthw_fpga_reg_defs_epp.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_EPP_ > +#define _NTHW_FPGA_REG_DEFS_EPP_ > + > +/* EPP */ > +#define NTHW_MOD_EPP (0x608ddc79UL) > +#define EPP_QUEUE_MTU_CTRL (0xcfd3b1a4UL) > +#define EPP_QUEUE_MTU_CTRL_ADR (0xa6da09b7UL) > +#define EPP_QUEUE_MTU_CTRL_CNT (0xb6d29066UL) > +#define EPP_QUEUE_MTU_DATA (0x600233bdUL) > +#define EPP_QUEUE_MTU_DATA_MAX_MTU (0x4e1d70c4UL) > +#define EPP_QUEUE_VPORT_CTRL (0x5daeb386UL) > +#define EPP_QUEUE_VPORT_CTRL_ADR (0x2bf54fbfUL) > +#define EPP_QUEUE_VPORT_CTRL_CNT (0x3bfdd66eUL) > +#define EPP_QUEUE_VPORT_DATA (0xf27f319fUL) > +#define EPP_QUEUE_VPORT_DATA_VPORT (0x9a1ab23eUL) > +#define EPP_RCP_CTRL (0x8163574aUL) > +#define EPP_RCP_CTRL_ADR (0x48b45181UL) > +#define EPP_RCP_CTRL_CNT (0x58bcc850UL) > +#define EPP_RCP_DATA (0x2eb2d553UL) > +#define EPP_RCP_DATA_FIXED_18B_L2_MTU (0xf188c234UL) > +#define EPP_RCP_DATA_QUEUE_MTU_EPP_EN (0x6ff74333UL) > +#define EPP_RCP_DATA_QUEUE_QOS_EPP_EN (0xba9ff77eUL) > +#define EPP_RCP_DATA_SIZE_ADJUST_TXP (0xd4e82cc4UL) > +#define EPP_RCP_DATA_SIZE_ADJUST_VPORT (0x90128d47UL) > +#define EPP_RCP_DATA_TX_MTU_EPP_EN (0x377c3d8bUL) > +#define EPP_RCP_DATA_TX_QOS_EPP_EN (0xe21489c6UL) > +#define EPP_TXP_MTU_CTRL (0x30a7bec7UL) > +#define EPP_TXP_MTU_CTRL_ADR (0xe2444518UL) > +#define EPP_TXP_MTU_CTRL_CNT (0xf24cdcc9UL) > +#define EPP_TXP_MTU_DATA (0x9f763cdeUL) > +#define EPP_TXP_MTU_DATA_MAX_MTU (0xbce62f2eUL) > +#define EPP_TXP_QOS_CTRL (0xa833b18aUL) > +#define EPP_TXP_QOS_CTRL_ADR (0x6b9fd6adUL) > +#define EPP_TXP_QOS_CTRL_CNT (0x7b974f7cUL) > +#define EPP_TXP_QOS_DATA (0x7e23393UL) > +#define EPP_TXP_QOS_DATA_BS (0xb8857ffbUL) > +#define EPP_TXP_QOS_DATA_EN (0x94c285e5UL) > +#define EPP_TXP_QOS_DATA_IR (0x2c7696a6UL) > +#define EPP_TXP_QOS_DATA_IR_FRACTION (0x972b2506UL) > +#define EPP_VPORT_QOS_CTRL (0x24c5b00eUL) > +#define EPP_VPORT_QOS_CTRL_ADR (0xae8e14c6UL) > +#define EPP_VPORT_QOS_CTRL_CNT (0xbe868d17UL) > +#define EPP_VPORT_QOS_DATA (0x8b143217UL) > +#define EPP_VPORT_QOS_DATA_BS (0x137caa43UL) > +#define EPP_VPORT_QOS_DATA_EN (0x3f3b505dUL) > +#define EPP_VPORT_QOS_DATA_IR (0x878f431eUL) > +#define EPP_VPORT_QOS_DATA_IR_FRACTION (0xa857a1dcUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_EPP_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h > new file mode 100644 > index 0000000000..5f1fa85001 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h > @@ -0,0 +1,45 @@ > +/* > + * nthw_fpga_reg_defs_eqm.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_EQM_ > +#define _NTHW_FPGA_REG_DEFS_EQM_ > + > +/* EQM */ > +#define NTHW_MOD_EQM (0x1a9081e1UL) > +#define EQM_CTRL (0xa04f58b0UL) > +#define EQM_CTRL_DBG_CRC_ERR (0xbe59fcc9UL) > +#define EQM_CTRL_DBG_FORCE_ERR (0x1195289fUL) > +#define EQM_CTRL_DBG_RMT_ERR (0x5fb0906fUL) > +#define EQM_CTRL_DBG_SYNC_ERR (0xf49ef23fUL) > +#define EQM_CTRL_ENABLE (0xe714200fUL) > +#define EQM_CTRL_MODE (0xf3774a36UL) > +#define EQM_CTRL_PP_RST (0x60d53774UL) > +#define EQM_DBG (0x3edaff33UL) > +#define EQM_DBG_FIFO_OF (0x29e8a88aUL) > +#define EQM_DBG_LCL_EGS_QKA_OF (0x3074364UL) > +#define EQM_DBG_LCL_EGS_QLVL_OF (0x47ec3248UL) > +#define EQM_DBG_QBLK_CREDITS (0xcf0f2e3eUL) > +#define EQM_STATUS (0xa64d64b3UL) > +#define EQM_STATUS_LCL_EGS_OF_ERR (0x613933faUL) > +#define EQM_STATUS_NIF_CRC_ERR (0x916ce965UL) > +#define EQM_STATUS_NIF_PP_LOOP_LCK (0xffa2b3c4UL) > +#define EQM_STATUS_NIF_RX_OF_ERR (0xa81de080UL) > +#define EQM_STATUS_NIF_SYNC_ERR (0x2bd128e9UL) > +#define EQM_STATUS_QM_CRC_ERR (0xd4dbf0f2UL) > +#define EQM_STATUS_RMT_EGS_OF_ERR (0x3ce2cda4UL) > +#define EQM_STATUS_RMT_ERR (0xc037b2cdUL) > +#define EQM_STATUS_RMT_IGS_OF_ERR (0x26de2d2aUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_EQM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h > new file mode 100644 > index 0000000000..26da7100b3 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h > @@ -0,0 +1,48 @@ > +/* > + * nthw_fpga_reg_defs_fhm.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_FHM_ > +#define _NTHW_FPGA_REG_DEFS_FHM_ > + > +/* FHM */ > +#define NTHW_MOD_FHM (0x83d696a0UL) > +#define FHM_BACK_PRESSURE (0x7eeb6d04UL) > +#define FHM_BACK_PRESSURE_NIF (0x60f30e0aUL) > +#define FHM_BACK_PRESSURE_RMC (0x61c96595UL) > +#define FHM_BACK_PRESSURE_RMC_S (0xbf76d96bUL) > +#define FHM_CRC_ERROR_NIF (0x7b140652UL) > +#define FHM_CRC_ERROR_NIF_CNT (0x9d790794UL) > +#define FHM_CRC_ERROR_SDC (0xaa2ebcb3UL) > +#define FHM_CRC_ERROR_SDC_CNT (0xef0e6634UL) > +#define FHM_CTRL (0xdc86864eUL) > +#define FHM_CTRL_CNT_CLR (0x6fdab4c8UL) > +#define FHM_CTRL_ENABLE (0x3e8d895aUL) > +#define FHM_CTRL_MODE (0xdf0cf195UL) > +#define FHM_DEBUG_CRC (0xdaa801daUL) > +#define FHM_DEBUG_CRC_FORCE_ERROR (0xebcc0719UL) > +#define FHM_DEBUG_SDRAM_SIZE (0x13b07f7bUL) > +#define FHM_DEBUG_SDRAM_SIZE_MASK (0xc9824976UL) > +#define FHM_FILL_LEVEL (0x7244a4d9UL) > +#define FHM_FILL_LEVEL_CELLS (0x1b463c75UL) > +#define FHM_MAC_MICRO_DROP (0x643f5329UL) > +#define FHM_MAC_MICRO_DROP_CNT (0xb0483cceUL) > +#define FHM_MAX_FILL_LEVEL (0x7a5980a6UL) > +#define FHM_MAX_FILL_LEVEL_CELLS (0x7913d45fUL) > +#define FHM_PKT_DROP (0xa8f4d538UL) > +#define FHM_PKT_DROP_CNT (0x789eb18UL) > +#define FHM_PKT_DROP_BYTES (0xbba69523UL) > +#define FHM_PKT_DROP_BYTES_CNT (0xfc38c84eUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_FHM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h > new file mode 100644 > index 0000000000..67f9a5c1e9 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h > @@ -0,0 +1,237 @@ > +/* > + * nthw_fpga_reg_defs_flm.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_FLM_ > +#define _NTHW_FPGA_REG_DEFS_FLM_ > + > +/* FLM */ > +#define NTHW_MOD_FLM (0xe7ba53a4UL) > +#define FLM_BUF_CTRL (0x2d7ba0b7UL) > +#define FLM_BUF_CTRL_INF_AVAIL (0x55993c46UL) > +#define FLM_BUF_CTRL_LRN_FREE (0x60b97a24UL) > +#define FLM_BUF_CTRL_STA_AVAIL (0x44abe7c4UL) > +#define FLM_CONTROL (0xdbb393a2UL) > +#define FLM_CONTROL_CRCRD (0x35ba7f13UL) > +#define FLM_CONTROL_CRCWR (0xbc193e07UL) > +#define FLM_CONTROL_EAB (0xa09637c2UL) > +#define FLM_CONTROL_ENABLE (0x5d80d95eUL) > +#define FLM_CONTROL_INIT (0x69b06e85UL) > +#define FLM_CONTROL_LDS (0xb880d8faUL) > +#define FLM_CONTROL_LFS (0x8ab6ba78UL) > +#define FLM_CONTROL_LIS (0xd2ea6b7UL) > +#define FLM_CONTROL_PDS (0xadbc82eeUL) > +#define FLM_CONTROL_PIS (0x1812fca3UL) > +#define FLM_CONTROL_RBL (0x756afcf3UL) > +#define FLM_CONTROL_RDS (0xae385680UL) > +#define FLM_CONTROL_RIS (0x1b9628cdUL) > +#define FLM_CONTROL_SPLIT_SDRAM_USAGE (0x71e7a8a4UL) > +#define FLM_CONTROL_UDS (0xab774005UL) > +#define FLM_CONTROL_UIS (0x1ed93e48UL) > +#define FLM_CONTROL_WPD (0x58ec6f9UL) > +#define FLM_INF_DATA (0xba19f6ccUL) > +#define FLM_INF_DATA_BYTES (0x480dab67UL) > +#define FLM_INF_DATA_BYT_A (0xb9920f4UL) > +#define FLM_INF_DATA_BYT_B (0x9290714eUL) > +#define FLM_INF_DATA_CAUSE (0x94e9716UL) > +#define FLM_INF_DATA_EOR (0xd81a867eUL) > +#define FLM_INF_DATA_ID (0x23a04258UL) > +#define FLM_INF_DATA_PACKETS (0x33a4ab9eUL) > +#define FLM_INF_DATA_PCK_A (0x3967b7a0UL) > +#define FLM_INF_DATA_PCK_B (0xa06ee61aUL) > +#define FLM_INF_DATA_RTX_A (0x900996cfUL) > +#define FLM_INF_DATA_RTX_B (0x900c775UL) > +#define FLM_INF_DATA_TCP_A (0xdc945df1UL) > +#define FLM_INF_DATA_TCP_B (0x459d0c4bUL) > +#define FLM_INF_DATA_TS (0x5f1fab83UL) > +#define FLM_LOAD_APS (0x4e7601e5UL) > +#define FLM_LOAD_APS_APS (0x504ad426UL) > +#define FLM_LOAD_BIN (0xb4367a7dUL) > +#define FLM_LOAD_BIN_BIN (0x274bb543UL) > +#define FLM_LOAD_LPS (0x46ae92b6UL) > +#define FLM_LOAD_LPS_LPS (0x394526b5UL) > +#define FLM_LRN_CTRL (0x11050e66UL) > +#define FLM_LRN_CTRL_FREE (0x4193813dUL) > +#define FLM_LRN_DATA (0xbed48c7fUL) > +#define FLM_LRN_DATA_ADJ (0x130ed7UL) > +#define FLM_LRN_DATA_COLOR (0x33d0a7f2UL) > +#define FLM_LRN_DATA_DSCP (0x5eab148eUL) > +#define FLM_LRN_DATA_ENT (0x7fa73e2UL) > +#define FLM_LRN_DATA_EOR (0xf782e796UL) > +#define FLM_LRN_DATA_FILL (0x768aba23UL) > +#define FLM_LRN_DATA_FT (0x4e9221cfUL) > +#define FLM_LRN_DATA_FT_MBR (0x48f095acUL) > +#define FLM_LRN_DATA_FT_MISS (0xea062e35UL) > +#define FLM_LRN_DATA_GFI (0xafa1415dUL) > +#define FLM_LRN_DATA_ID (0xd4bd2d64UL) > +#define FLM_LRN_DATA_KID (0x5f92d84bUL) > +#define FLM_LRN_DATA_MBR_ID1 (0x9931440eUL) > +#define FLM_LRN_DATA_MBR_ID2 (0x3815b4UL) > +#define FLM_LRN_DATA_MBR_ID3 (0x773f2522UL) > +#define FLM_LRN_DATA_MBR_ID4 (0xe95bb081UL) > +#define FLM_LRN_DATA_NAT_EN (0x9f4035a4UL) > +#define FLM_LRN_DATA_NAT_IP (0xc9fa47cbUL) > +#define FLM_LRN_DATA_NAT_PORT (0x5f8f57d0UL) > +#define FLM_LRN_DATA_NOFI (0x3d36f27bUL) > +#define FLM_LRN_DATA_OP (0x983d5e9fUL) > +#define FLM_LRN_DATA_PRIO (0xf7f55b0eUL) > +#define FLM_LRN_DATA_PROT (0x2bca3564UL) > +#define FLM_LRN_DATA_QFI (0xb70a9e9fUL) > +#define FLM_LRN_DATA_QW0 (0xcd0a7417UL) > +#define FLM_LRN_DATA_QW4 (0xca67b00eUL) > +#define FLM_LRN_DATA_RATE (0x5c250baeUL) > +#define FLM_LRN_DATA_RQI (0xb0cfa450UL) > +#define FLM_LRN_DATA_SCRUB_PROF (0xc3730f6bUL) > +#define FLM_LRN_DATA_SIZE (0x740910fdUL) > +#define FLM_LRN_DATA_STAT_PROF (0xded894eaUL) > +#define FLM_LRN_DATA_SW8 (0xc055284bUL) > +#define FLM_LRN_DATA_SW9 (0xb75218ddUL) > +#define FLM_LRN_DATA_TAU (0xea8196fcUL) > +#define FLM_LRN_DATA_TEID (0xf62ca024UL) > +#define FLM_LRN_DATA_TTL (0xb95fd828UL) > +#define FLM_LRN_DATA_VOL_IDX (0xabc86ffbUL) > +#define FLM_PRIO (0x5ed7bcbeUL) > +#define FLM_PRIO_FT0 (0x9ef34f69UL) > +#define FLM_PRIO_FT1 (0xe9f47fffUL) > +#define FLM_PRIO_FT2 (0x70fd2e45UL) > +#define FLM_PRIO_FT3 (0x7fa1ed3UL) > +#define FLM_PRIO_LIMIT0 (0xcce9cfe8UL) > +#define FLM_PRIO_LIMIT1 (0xbbeeff7eUL) > +#define FLM_PRIO_LIMIT2 (0x22e7aec4UL) > +#define FLM_PRIO_LIMIT3 (0x55e09e52UL) > +#define FLM_PST_CTRL (0x3e2b004bUL) > +#define FLM_PST_CTRL_ADR (0xfa8565c1UL) > +#define FLM_PST_CTRL_CNT (0xea8dfc10UL) > +#define FLM_PST_DATA (0x91fa8252UL) > +#define FLM_PST_DATA_BP (0x5f53d50fUL) > +#define FLM_PST_DATA_PP (0x27a7a5dcUL) > +#define FLM_PST_DATA_TP (0x43cb60d8UL) > +#define FLM_RCP_CTRL (0x8041d9eeUL) > +#define FLM_RCP_CTRL_ADR (0xb1a39fefUL) > +#define FLM_RCP_CTRL_CNT (0xa1ab063eUL) > +#define FLM_RCP_DATA (0x2f905bf7UL) > +#define FLM_RCP_DATA_A (0xec41ba43UL) > +#define FLM_RCP_DATA_AUTO_IPV4_MASK (0xa7818261UL) > +#define FLM_RCP_DATA_B (0x7548ebf9UL) > +#define FLM_RCP_DATA_BYT_DYN (0x28334583UL) > +#define FLM_RCP_DATA_BYT_OFS (0x8a3ac825UL) > +#define FLM_RCP_DATA_IPN (0x94f5d891UL) > +#define FLM_RCP_DATA_ITF (0xfe4295a7UL) > +#define FLM_RCP_DATA_KID (0xeca44cf9UL) > +#define FLM_RCP_DATA_LOOKUP (0x5d0f2e84UL) > +#define FLM_RCP_DATA_MASK (0xd97a1393UL) > +#define FLM_RCP_DATA_OPN (0x9078a423UL) > +#define FLM_RCP_DATA_QW0_DYN (0x28bd732dUL) > +#define FLM_RCP_DATA_QW0_OFS (0x8ab4fe8bUL) > +#define FLM_RCP_DATA_QW0_SEL (0x39adfaa9UL) > +#define FLM_RCP_DATA_QW4_DYN (0xdd3dd5edUL) > +#define FLM_RCP_DATA_QW4_OFS (0x7f34584bUL) > +#define FLM_RCP_DATA_SW8_DYN (0x8f5229c5UL) > +#define FLM_RCP_DATA_SW8_OFS (0x2d5ba463UL) > +#define FLM_RCP_DATA_SW8_SEL (0x9e42a041UL) > +#define FLM_RCP_DATA_SW9_DYN (0xb2320075UL) > +#define FLM_RCP_DATA_SW9_OFS (0x103b8dd3UL) > +#define FLM_RCP_DATA_TXPLM (0xbe56af35UL) > +#define FLM_SCAN (0xee586089UL) > +#define FLM_SCAN_I (0xe22d4ee5UL) > +#define FLM_SCRUB (0x690c7a66UL) > +#define FLM_SCRUB_I (0xc6a9dfe8UL) > +#define FLM_SCRUB_CTRL (0xc647074aUL) > +#define FLM_SCRUB_CTRL_ADR (0x3d584aa4UL) > +#define FLM_SCRUB_CTRL_CNT (0x2d50d375UL) > +#define FLM_SCRUB_DATA (0x69968553UL) > +#define FLM_SCRUB_DATA_T (0x2a9c9e90UL) > +#define FLM_STAT (0xa532c06UL) > +#define FLM_STAT_I (0x215c23d1UL) > +#define FLM_STATUS (0x10f57a96UL) > +#define FLM_STATUS_CALIBDONE (0x47680c22UL) > +#define FLM_STATUS_CRCERR (0xcd852b33UL) > +#define FLM_STATUS_CRITICAL (0xe9e1b478UL) > +#define FLM_STATUS_EFT_BP (0xf60fc391UL) > +#define FLM_STATUS_EFT_EVICT_BP (0xf4dd216fUL) > +#define FLM_STATUS_IDLE (0xd02fd0e7UL) > +#define FLM_STATUS_INITDONE (0xdd6bdbd8UL) > +#define FLM_STATUS_PANIC (0xf676390fUL) > +#define FLM_STAT_AUL_DONE (0x747800bbUL) > +#define FLM_STAT_AUL_DONE_CNT (0x6b744caeUL) > +#define FLM_STAT_AUL_FAIL (0xe272cb59UL) > +#define FLM_STAT_AUL_FAIL_CNT (0x697b6247UL) > +#define FLM_STAT_AUL_IGNORE (0x49aa46f4UL) > +#define FLM_STAT_AUL_IGNORE_CNT (0x37721e3bUL) > +#define FLM_STAT_CSH_HIT (0xd0dca28cUL) > +#define FLM_STAT_CSH_HIT_CNT (0xc7a41ba4UL) > +#define FLM_STAT_CSH_MISS (0xbc219a9fUL) > +#define FLM_STAT_CSH_MISS_CNT (0x4a66e57eUL) > +#define FLM_STAT_CSH_UNH (0x9f625827UL) > +#define FLM_STAT_CSH_UNH_CNT (0x79b8ac91UL) > +#define FLM_STAT_CUC_MOVE (0x381862c0UL) > +#define FLM_STAT_CUC_MOVE_CNT (0x868e1261UL) > +#define FLM_STAT_CUC_START (0x617a68acUL) > +#define FLM_STAT_CUC_START_CNT (0xbf953f79UL) > +#define FLM_STAT_FLOWS (0x3072544fUL) > +#define FLM_STAT_FLOWS_CNT (0x829b2631UL) > +#define FLM_STAT_INF_DONE (0x63dff05cUL) > +#define FLM_STAT_INF_DONE_CNT (0xf78de916UL) > +#define FLM_STAT_INF_SKIP (0x8b84458aUL) > +#define FLM_STAT_INF_SKIP_CNT (0xc0b9dd7dUL) > +#define FLM_STAT_LRN_DONE (0x67128aefUL) > +#define FLM_STAT_LRN_DONE_CNT (0xd81588feUL) > +#define FLM_STAT_LRN_FAIL (0xf118410dUL) > +#define FLM_STAT_LRN_FAIL_CNT (0xda1aa617UL) > +#define FLM_STAT_LRN_IGNORE (0x9a10a7f0UL) > +#define FLM_STAT_LRN_IGNORE_CNT (0x11c0f6a7UL) > +#define FLM_STAT_PCK_DIS (0x55e23053UL) > +#define FLM_STAT_PCK_DIS_CNT (0x9b13b227UL) > +#define FLM_STAT_PCK_HIT (0xc29c5c94UL) > +#define FLM_STAT_PCK_HIT_CNT (0xee930443UL) > +#define FLM_STAT_PCK_MISS (0xaf5f4237UL) > +#define FLM_STAT_PCK_MISS_CNT (0x7421a5baUL) > +#define FLM_STAT_PCK_UNH (0x8d22a63fUL) > +#define FLM_STAT_PCK_UNH_CNT (0x508fb376UL) > +#define FLM_STAT_PRB_DONE (0x3bc46ef0UL) > +#define FLM_STAT_PRB_DONE_CNT (0xcb3bc80dUL) > +#define FLM_STAT_PRB_IGNORE (0xf02dd3d9UL) > +#define FLM_STAT_PRB_IGNORE_CNT (0x588d1667UL) > +#define FLM_STAT_REL_DONE (0xe192aabdUL) > +#define FLM_STAT_REL_DONE_CNT (0xbe04b769UL) > +#define FLM_STAT_REL_IGNORE (0x29f33e6eUL) > +#define FLM_STAT_REL_IGNORE_CNT (0x99a6a156UL) > +#define FLM_STAT_STA_DONE (0x500f2e87UL) > +#define FLM_STAT_STA_DONE_CNT (0xbf276bbdUL) > +#define FLM_STAT_TUL_DONE (0x40233ff4UL) > +#define FLM_STAT_TUL_DONE_CNT (0xffcfd642UL) > +#define FLM_STAT_UNL_DONE (0xe950f75eUL) > +#define FLM_STAT_UNL_DONE_CNT (0xe9bdd9a2UL) > +#define FLM_STAT_UNL_IGNORE (0x497abbcaUL) > +#define FLM_STAT_UNL_IGNORE_CNT (0x1ba2b435UL) > +#define FLM_STA_DATA (0x89c92817UL) > +#define FLM_STA_DATA_EOR (0x90b004d5UL) > +#define FLM_STA_DATA_ID (0x3b14a2ffUL) > +#define FLM_STA_DATA_LDS (0xb92d607UL) > +#define FLM_STA_DATA_LFS (0x39a4b485UL) > +#define FLM_STA_DATA_LIS (0xbe3ca84aUL) > +#define FLM_STA_DATA_PDS (0x1eae8c13UL) > +#define FLM_STA_DATA_PIS (0xab00f25eUL) > +#define FLM_STA_DATA_RDS (0x1d2a587dUL) > +#define FLM_STA_DATA_RIS (0xa8842630UL) > +#define FLM_STA_DATA_UDS (0x18654ef8UL) > +#define FLM_STA_DATA_UIS (0xadcb30b5UL) > +#define FLM_TIMEOUT (0xb729ca7bUL) > +#define FLM_TIMEOUT_T (0x91a2b284UL) > +#define FLM_TRSWIN (0xff97af47UL) > +#define FLM_TRSWIN_S (0x41ed83b1UL) > +#define FLM_TRTWIN (0x624097feUL) > +#define FLM_TRTWIN_T (0xc28c26aaUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_FLM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h > new file mode 100644 > index 0000000000..6ee75c571e > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h > @@ -0,0 +1,126 @@ > +/* > + * nthw_fpga_reg_defs_gfg.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_GFG_ > +#define _NTHW_FPGA_REG_DEFS_GFG_ > + > +/* GFG */ > +#define NTHW_MOD_GFG (0xfc423807UL) > +#define GFG_BURSTSIZE0 (0xd62af404UL) > +#define GFG_BURSTSIZE0_VAL (0xa2e4d17eUL) > +#define GFG_BURSTSIZE1 (0xa12dc492UL) > +#define GFG_BURSTSIZE1_VAL (0x9f84f8ceUL) > +#define GFG_BURSTSIZE2 (0x38249528UL) > +#define GFG_BURSTSIZE2_VAL (0xd824821eUL) > +#define GFG_BURSTSIZE3 (0x4f23a5beUL) > +#define GFG_BURSTSIZE3_VAL (0xe544abaeUL) > +#define GFG_BURSTSIZE4 (0xd147301dUL) > +#define GFG_BURSTSIZE4_VAL (0x576477beUL) > +#define GFG_BURSTSIZE5 (0xa640008bUL) > +#define GFG_BURSTSIZE5_VAL (0x6a045e0eUL) > +#define GFG_BURSTSIZE6 (0x3f495131UL) > +#define GFG_BURSTSIZE6_VAL (0x2da424deUL) > +#define GFG_BURSTSIZE7 (0x484e61a7UL) > +#define GFG_BURSTSIZE7_VAL (0x10c40d6eUL) > +#define GFG_CTRL0 (0xc3e26c0fUL) > +#define GFG_CTRL0_ENABLE (0xfe65937UL) > +#define GFG_CTRL0_MODE (0x81d94c52UL) > +#define GFG_CTRL0_PRBS_EN (0xb43e6c6UL) > +#define GFG_CTRL0_SIZE (0xe1d32f93UL) > +#define GFG_CTRL1 (0xb4e55c99UL) > +#define GFG_CTRL1_ENABLE (0xc34c59a9UL) > +#define GFG_CTRL1_MODE (0x4a859ff7UL) > +#define GFG_CTRL1_PRBS_EN (0x1c38f285UL) > +#define GFG_CTRL1_SIZE (0x2a8ffc36UL) > +#define GFG_CTRL2 (0x2dec0d23UL) > +#define GFG_CTRL2_ENABLE (0x4dc35e4aUL) > +#define GFG_CTRL2_MODE (0xcc11ed59UL) > +#define GFG_CTRL2_PRBS_EN (0x25b5ce40UL) > +#define GFG_CTRL2_SIZE (0xac1b8e98UL) > +#define GFG_CTRL3 (0x5aeb3db5UL) > +#define GFG_CTRL3_ENABLE (0x81695ed4UL) > +#define GFG_CTRL3_MODE (0x74d3efcUL) > +#define GFG_CTRL3_PRBS_EN (0x32ceda03UL) > +#define GFG_CTRL3_SIZE (0x67475d3dUL) > +#define GFG_CTRL4 (0xc48fa816UL) > +#define GFG_CTRL4_ENABLE (0x8bac57cdUL) > +#define GFG_CTRL4_MODE (0x1a480e44UL) > +#define GFG_CTRL4_PRBS_EN (0x56afb7caUL) > +#define GFG_CTRL4_SIZE (0x7a426d85UL) > +#define GFG_CTRL5 (0xb3889880UL) > +#define GFG_CTRL5_ENABLE (0x47065753UL) > +#define GFG_CTRL5_MODE (0xd114dde1UL) > +#define GFG_CTRL5_PRBS_EN (0x41d4a389UL) > +#define GFG_CTRL5_SIZE (0xb11ebe20UL) > +#define GFG_CTRL6 (0x2a81c93aUL) > +#define GFG_CTRL6_ENABLE (0xc98950b0UL) > +#define GFG_CTRL6_MODE (0x5780af4fUL) > +#define GFG_CTRL6_PRBS_EN (0x78599f4cUL) > +#define GFG_CTRL6_SIZE (0x378acc8eUL) > +#define GFG_CTRL7 (0x5d86f9acUL) > +#define GFG_CTRL7_ENABLE (0x523502eUL) > +#define GFG_CTRL7_MODE (0x9cdc7ceaUL) > +#define GFG_CTRL7_PRBS_EN (0x6f228b0fUL) > +#define GFG_CTRL7_SIZE (0xfcd61f2bUL) > +#define GFG_RUN0 (0xb72be46cUL) > +#define GFG_RUN0_RUN (0xa457d3c8UL) > +#define GFG_RUN1 (0xc02cd4faUL) > +#define GFG_RUN1_RUN (0x9937fa78UL) > +#define GFG_RUN2 (0x59258540UL) > +#define GFG_RUN2_RUN (0xde9780a8UL) > +#define GFG_RUN3 (0x2e22b5d6UL) > +#define GFG_RUN3_RUN (0xe3f7a918UL) > +#define GFG_RUN4 (0xb0462075UL) > +#define GFG_RUN4_RUN (0x51d77508UL) > +#define GFG_RUN5 (0xc74110e3UL) > +#define GFG_RUN5_RUN (0x6cb75cb8UL) > +#define GFG_RUN6 (0x5e484159UL) > +#define GFG_RUN6_RUN (0x2b172668UL) > +#define GFG_RUN7 (0x294f71cfUL) > +#define GFG_RUN7_RUN (0x16770fd8UL) > +#define GFG_SIZEMASK0 (0x7015abe3UL) > +#define GFG_SIZEMASK0_VAL (0xe9c7ed93UL) > +#define GFG_SIZEMASK1 (0x7129b75UL) > +#define GFG_SIZEMASK1_VAL (0xd4a7c423UL) > +#define GFG_SIZEMASK2 (0x9e1bcacfUL) > +#define GFG_SIZEMASK2_VAL (0x9307bef3UL) > +#define GFG_SIZEMASK3 (0xe91cfa59UL) > +#define GFG_SIZEMASK3_VAL (0xae679743UL) > +#define GFG_SIZEMASK4 (0x77786ffaUL) > +#define GFG_SIZEMASK4_VAL (0x1c474b53UL) > +#define GFG_SIZEMASK5 (0x7f5f6cUL) > +#define GFG_SIZEMASK5_VAL (0x212762e3UL) > +#define GFG_SIZEMASK6 (0x99760ed6UL) > +#define GFG_SIZEMASK6_VAL (0x66871833UL) > +#define GFG_SIZEMASK7 (0xee713e40UL) > +#define GFG_SIZEMASK7_VAL (0x5be73183UL) > +#define GFG_STREAMID0 (0xbd4ba9aeUL) > +#define GFG_STREAMID0_VAL (0x42d077caUL) > +#define GFG_STREAMID1 (0xca4c9938UL) > +#define GFG_STREAMID1_VAL (0x7fb05e7aUL) > +#define GFG_STREAMID2 (0x5345c882UL) > +#define GFG_STREAMID2_VAL (0x381024aaUL) > +#define GFG_STREAMID3 (0x2442f814UL) > +#define GFG_STREAMID3_VAL (0x5700d1aUL) > +#define GFG_STREAMID4 (0xba266db7UL) > +#define GFG_STREAMID4_VAL (0xb750d10aUL) > +#define GFG_STREAMID5 (0xcd215d21UL) > +#define GFG_STREAMID5_VAL (0x8a30f8baUL) > +#define GFG_STREAMID6 (0x54280c9bUL) > +#define GFG_STREAMID6_VAL (0xcd90826aUL) > +#define GFG_STREAMID7 (0x232f3c0dUL) > +#define GFG_STREAMID7_VAL (0xf0f0abdaUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_GFG_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h > new file mode 100644 > index 0000000000..be3c12d177 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h > @@ -0,0 +1,68 @@ > +/* > + * nthw_fpga_reg_defs_gmf.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_GMF_ > +#define _NTHW_FPGA_REG_DEFS_GMF_ > + > +/* GMF */ > +#define NTHW_MOD_GMF (0x68b1d15aUL) > +#define GMF_CTRL (0x28d359b4UL) > +#define GMF_CTRL_ENABLE (0xe41c837cUL) > +#define GMF_CTRL_FCS_ALWAYS (0x8f36cec1UL) > +#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (0x5b5669b0UL) > +#define GMF_CTRL_IFG_ENABLE (0x995f1bfbUL) > +#define GMF_CTRL_IFG_TX_NOW_ALWAYS (0xb11744c2UL) > +#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (0xe9e4ee2aUL) > +#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK > (0x32dc6426UL) > +#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (0x21dcad67UL) > +#define GMF_CTRL_TS_INJECT_ALWAYS (0x353fa4aaUL) > +#define GMF_CTRL_TS_INJECT_DUAL_STEP (0xc4c0195cUL) > +#define GMF_DEBUG_LANE_MARKER (0xa51eb8a9UL) > +#define GMF_DEBUG_LANE_MARKER_COMPENSATION (0x4f44f92aUL) > +#define GMF_IFG_MAX_ADJUST_SLACK (0xe49f3408UL) > +#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (0x9a2de1f7UL) > +#define GMF_IFG_SET_CLOCK_DELTA (0x8a614d6fUL) > +#define GMF_IFG_SET_CLOCK_DELTA_DELTA (0x1da821d6UL) > +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (0xaa468304UL) > +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (0x2c165992UL) > +#define GMF_IFG_TX_NOW_ON_TS (0xd32fab5eUL) > +#define GMF_IFG_TX_NOW_ON_TS_TS (0x612771f4UL) > +#define GMF_SPEED (0x48bec0a1UL) > +#define GMF_SPEED_IFG_SPEED (0x273c8281UL) > +#define GMF_STAT (0xa49d7efUL) > +#define GMF_STAT_CTRL_EMPTY (0x3f6e8adcUL) > +#define GMF_STAT_DATA_CTRL_EMPTY (0xc18fc6e9UL) > +#define GMF_STAT_SB_EMPTY (0x99314d52UL) > +#define GMF_STAT_CTRL (0xfd31633eUL) > +#define GMF_STAT_CTRL_FILL_LEVEL (0xe8cd56d6UL) > +#define GMF_STAT_DATA0 (0x51838aabUL) > +#define GMF_STAT_DATA0_EMPTY (0xcfcad9c0UL) > +#define GMF_STAT_DATA1 (0x2684ba3dUL) > +#define GMF_STAT_DATA1_EMPTY (0x69bdd274UL) > +#define GMF_STAT_DATA_BUFFER (0xa6431f34UL) > +#define GMF_STAT_DATA_BUFFER_FREE (0x3476e461UL) > +#define GMF_STAT_DATA_BUFFER_USED (0x1f46b1UL) > +#define GMF_STAT_MAX_DELAYED_PKT (0x3fb5c76dUL) > +#define GMF_STAT_MAX_DELAYED_PKT_NS (0x2eb58efbUL) > +#define GMF_STAT_NEXT_PKT (0x558ee30dUL) > +#define GMF_STAT_NEXT_PKT_NS (0x26814d33UL) > +#define GMF_STAT_STICKY (0x5a0f2ef7UL) > +#define GMF_STAT_STICKY_DATA_UNDERFLOWED (0x9a3dfcb6UL) > +#define GMF_STAT_STICKY_IFG_ADJUSTED (0xea849a5fUL) > +#define GMF_TS_INJECT (0x66e57281UL) > +#define GMF_TS_INJECT_OFFSET (0x8c2c9cb6UL) > +#define GMF_TS_INJECT_POS (0xdded481UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_GMF_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h > new file mode 100644 > index 0000000000..6574263d50 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h > @@ -0,0 +1,48 @@ > +/* > + * nthw_fpga_reg_defs_gpio_phy.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_ > +#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_ > + > +/* GPIO_PHY */ > +#define NTHW_MOD_GPIO_PHY (0xbbe81659UL) > +#define GPIO_PHY_CFG (0x39548432UL) > +#define GPIO_PHY_CFG_E_PORT0_RXLOS (0x2dfe5bUL) > +#define GPIO_PHY_CFG_E_PORT1_RXLOS (0xa65af5efUL) > +#define GPIO_PHY_CFG_PORT0_INT_B (0xa882887cUL) > +#define GPIO_PHY_CFG_PORT0_LPMODE (0x65df41beUL) > +#define GPIO_PHY_CFG_PORT0_MODPRS_B (0x6aef8e94UL) > +#define GPIO_PHY_CFG_PORT0_PLL_INTR (0xbf1f8c5dUL) > +#define GPIO_PHY_CFG_PORT0_RESET_B (0x1ef06a6cUL) > +#define GPIO_PHY_CFG_PORT1_INT_B (0xef583c8UL) > +#define GPIO_PHY_CFG_PORT1_LPMODE (0xa9754120UL) > +#define GPIO_PHY_CFG_PORT1_MODPRS_B (0x852de5aaUL) > +#define GPIO_PHY_CFG_PORT1_PLL_INTR (0x50dde763UL) > +#define GPIO_PHY_CFG_PORT1_RESET_B (0x98b7e2fUL) > +#define GPIO_PHY_GPIO (0xf5c5d393UL) > +#define GPIO_PHY_GPIO_E_PORT0_RXLOS (0xfb05c9faUL) > +#define GPIO_PHY_GPIO_E_PORT1_RXLOS (0x5d72c24eUL) > +#define GPIO_PHY_GPIO_PORT0_INT_B (0x6aceab27UL) > +#define GPIO_PHY_GPIO_PORT0_LPMODE (0x99a485e1UL) > +#define GPIO_PHY_GPIO_PORT0_MODPRS_B (0xcbc535ddUL) > +#define GPIO_PHY_GPIO_PORT0_PLL_INTR (0x1e353714UL) > +#define GPIO_PHY_GPIO_PORT0_RESET_B (0xe5d85dcdUL) > +#define GPIO_PHY_GPIO_PORT1_INT_B (0xccb9a093UL) > +#define GPIO_PHY_GPIO_PORT1_LPMODE (0x550e857fUL) > +#define GPIO_PHY_GPIO_PORT1_MODPRS_B (0x24075ee3UL) > +#define GPIO_PHY_GPIO_PORT1_PLL_INTR (0xf1f75c2aUL) > +#define GPIO_PHY_GPIO_PORT1_RESET_B (0xf2a3498eUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_GPIO_PHY_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h > new file mode 100644 > index 0000000000..c90a4d3209 > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h > @@ -0,0 +1,72 @@ > +/* > + * nthw_fpga_reg_defs_gpio_phy_ports.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_ > +#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_ > + > +/* GPIO_PHY_PORTS */ > +#define NTHW_MOD_GPIO_PHY_PORTS (0xea12bddaUL) > +#define GPIO_PHY_PORTS_CFG (0xe1aa4733UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT0_RXLOS (0x252ff3abUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT0_TXDISABLE (0xc9d467abUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT0_TXFAULT (0xd56642aaUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT1_RXLOS (0x8358f81fUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT1_TXDISABLE (0x85ab86bUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT1_TXFAULT (0xc21d56e9UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT2_RXLOS (0xb2b0e282UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT2_TXDISABLE (0x91b8de6aUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT2_TXFAULT (0xfb906a2cUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT3_RXLOS (0x14c7e936UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT3_TXDISABLE (0x503601aaUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT3_TXFAULT (0xeceb7e6fUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT4_RXLOS (0xd160d7b8UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT4_TXDISABLE (0x790d1429UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT4_TXFAULT (0x888a13a6UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT5_RXLOS (0x7717dc0cUL) > +#define GPIO_PHY_PORTS_CFG_E_PORT5_TXDISABLE (0xb883cbe9UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT5_TXFAULT (0x9ff107e5UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT6_RXLOS (0x46ffc691UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT6_TXDISABLE (0x2161ade8UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT6_TXFAULT (0xa67c3b20UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT7_RXLOS (0xe088cd25UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT7_TXDISABLE (0xe0ef7228UL) > +#define GPIO_PHY_PORTS_CFG_E_PORT7_TXFAULT (0xb1072f63UL) > +#define GPIO_PHY_PORTS_GPIO (0x821a1dc6UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT0_RXLOS (0x469d39ebUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXDISABLE (0xccb0d0d8UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXFAULT (0x5eae45b3UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT1_RXLOS (0xe0ea325fUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXDISABLE (0xd3e0f18UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXFAULT (0x49d551f0UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT2_RXLOS (0xd10228c2UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXDISABLE (0x94dc6919UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXFAULT (0x70586d35UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT3_RXLOS (0x77752376UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXDISABLE (0x5552b6d9UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXFAULT (0x67237976UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT4_RXLOS (0xb2d21df8UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXDISABLE (0x7c69a35aUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXFAULT (0x34214bfUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT5_RXLOS (0x14a5164cUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXDISABLE (0xbde77c9aUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXFAULT (0x143900fcUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT6_RXLOS (0x254d0cd1UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXDISABLE (0x24051a9bUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXFAULT (0x2db43c39UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT7_RXLOS (0x833a0765UL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXDISABLE (0xe58bc55bUL) > +#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXFAULT (0x3acf287aUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h > new file mode 100644 > index 0000000000..f271b0cd46 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h > @@ -0,0 +1,34 @@ > +/* > + * nthw_fpga_reg_defs_gpio_sfpp.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_SFPP_ > +#define _NTHW_FPGA_REG_DEFS_GPIO_SFPP_ > + > +/* GPIO_SFPP */ > +#define NTHW_MOD_GPIO_SFPP (0x628c8692UL) > +#define GPIO_SFPP_CFG (0x9b959116UL) > +#define GPIO_SFPP_CFG_ABS (0xc2942338UL) > +#define GPIO_SFPP_CFG_RS (0x47e98ea9UL) > +#define GPIO_SFPP_CFG_RXLOS (0x7e3cf082UL) > +#define GPIO_SFPP_CFG_TXDISABLE (0x8bfef0a8UL) > +#define GPIO_SFPP_CFG_TXFAULT (0x829d7e8UL) > +#define GPIO_SFPP_GPIO (0xc964f657UL) > +#define GPIO_SFPP_GPIO_ABS (0x246621e1UL) > +#define GPIO_SFPP_GPIO_RS (0xd6b756e6UL) > +#define GPIO_SFPP_GPIO_RXLOS (0xc0c8090aUL) > +#define GPIO_SFPP_GPIO_TXDISABLE (0x450f9c11UL) > +#define GPIO_SFPP_GPIO_TXFAULT (0x3f1231e7UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_GPIO_SFPP_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h > new file mode 100644 > index 0000000000..19589f7900 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h > @@ -0,0 +1,48 @@ > +/* > + * nthw_fpga_reg_defs_hfu.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_HFU_ > +#define _NTHW_FPGA_REG_DEFS_HFU_ > + > +/* HFU */ > +#define NTHW_MOD_HFU (0x4a70e72UL) > +#define HFU_RCP_CTRL (0xbfa69368UL) > +#define HFU_RCP_CTRL_ADR (0xa3c53608UL) > +#define HFU_RCP_CTRL_CNT (0xb3cdafd9UL) > +#define HFU_RCP_DATA (0x10771171UL) > +#define HFU_RCP_DATA_LEN_A_ADD_DYN (0xf48e5cadUL) > +#define HFU_RCP_DATA_LEN_A_ADD_OFS (0x5687d10bUL) > +#define HFU_RCP_DATA_LEN_A_OL4LEN (0xb06eaffcUL) > +#define HFU_RCP_DATA_LEN_A_POS_DYN (0x8d207086UL) > +#define HFU_RCP_DATA_LEN_A_POS_OFS (0x2f29fd20UL) > +#define HFU_RCP_DATA_LEN_A_SUB_DYN (0x4305f5d4UL) > +#define HFU_RCP_DATA_LEN_A_WR (0x22d5466UL) > +#define HFU_RCP_DATA_LEN_B_ADD_DYN (0xcd036068UL) > +#define HFU_RCP_DATA_LEN_B_ADD_OFS (0x6f0aedceUL) > +#define HFU_RCP_DATA_LEN_B_POS_DYN (0xb4ad4c43UL) > +#define HFU_RCP_DATA_LEN_B_POS_OFS (0x16a4c1e5UL) > +#define HFU_RCP_DATA_LEN_B_SUB_DYN (0x7a88c911UL) > +#define HFU_RCP_DATA_LEN_B_WR (0x1098fb88UL) > +#define HFU_RCP_DATA_LEN_C_ADD_DYN (0xda78742bUL) > +#define HFU_RCP_DATA_LEN_C_ADD_OFS (0x7871f98dUL) > +#define HFU_RCP_DATA_LEN_C_POS_DYN (0xa3d65800UL) > +#define HFU_RCP_DATA_LEN_C_POS_OFS (0x1dfd5a6UL) > +#define HFU_RCP_DATA_LEN_C_SUB_DYN (0x6df3dd52UL) > +#define HFU_RCP_DATA_LEN_C_WR (0xa8249cedUL) > +#define HFU_RCP_DATA_TTL_POS_DYN (0x92a70913UL) > +#define HFU_RCP_DATA_TTL_POS_OFS (0x30ae84b5UL) > +#define HFU_RCP_DATA_TTL_WR (0x7a1aaf7UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_HFU_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h > new file mode 100644 > index 0000000000..4bd2ca52c9 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h > @@ -0,0 +1,79 @@ > +/* > + * nthw_fpga_reg_defs_hif.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_HIF_ > +#define _NTHW_FPGA_REG_DEFS_HIF_ > + > +/* HIF */ > +#define NTHW_MOD_HIF (0x7815363UL) > +#define HIF_BUILD_TIME (0x1eaf6ab8UL) > +#define HIF_BUILD_TIME_TIME (0xb2dfbda5UL) > +#define HIF_CONFIG (0xb64b595cUL) > +#define HIF_CONFIG_EXT_TAG (0x57e685bUL) > +#define HIF_CONFIG_MAX_READ (0x7d56ce45UL) > +#define HIF_CONFIG_MAX_TLP (0xe1c563e4UL) > +#define HIF_CONTROL (0xedb9ed3dUL) > +#define HIF_CONTROL_BLESSED (0x680018b7UL) > +#define HIF_CONTROL_FSR (0x498a2097UL) > +#define HIF_CONTROL_WRAW (0xc1a7bc42UL) > +#define HIF_PROD_ID_EX (0xc9c9efb2UL) > +#define HIF_PROD_ID_EX_LAYOUT (0xc6564c80UL) > +#define HIF_PROD_ID_EX_LAYOUT_VERSION (0x9803a0e2UL) > +#define HIF_PROD_ID_EX_RESERVED (0x1189af8aUL) > +#define HIF_PROD_ID_EXT (0x9ba2612fUL) > +#define HIF_PROD_ID_EXT_LAYOUT (0xe315afa1UL) > +#define HIF_PROD_ID_EXT_LAYOUT_VERSION (0x1f7aa616UL) > +#define HIF_PROD_ID_EXT_RESERVED (0xa4152ce8UL) > +#define HIF_PROD_ID_LSB (0x8353363aUL) > +#define HIF_PROD_ID_LSB_GROUP_ID (0xbb9614f7UL) > +#define HIF_PROD_ID_LSB_REV_ID (0x5458192eUL) > +#define HIF_PROD_ID_LSB_VER_ID (0x40abcc6fUL) > +#define HIF_PROD_ID_MSB (0x82915c0dUL) > +#define HIF_PROD_ID_MSB_BUILD_NO (0x1135f11bUL) > +#define HIF_PROD_ID_MSB_PATCH_NO (0xcbf446bcUL) > +#define HIF_PROD_ID_MSB_TYPE_ID (0xb49af41cUL) > +#define HIF_SAMPLE_TIME (0xad0472aaUL) > +#define HIF_SAMPLE_TIME_SAMPLE_TIME (0x56bd0a0bUL) > +#define HIF_STATUS (0x19c1133cUL) > +#define HIF_STATUS_RD_ERR (0x15e9f376UL) > +#define HIF_STATUS_TAGS_IN_USE (0x9789b255UL) > +#define HIF_STATUS_WR_ERR (0xaa8400e7UL) > +#define HIF_STAT_CTRL (0xd9478d74UL) > +#define HIF_STAT_CTRL_STAT_ENA (0xf26c834cUL) > +#define HIF_STAT_CTRL_STAT_REQ (0x1546ff16UL) > +#define HIF_STAT_REFCLK (0x656cf83fUL) > +#define HIF_STAT_REFCLK_REFCLK250 (0xb9dd01fcUL) > +#define HIF_STAT_RX (0x8c483f48UL) > +#define HIF_STAT_RX_COUNTER (0xd99bc360UL) > +#define HIF_STAT_TX (0xda1298ceUL) > +#define HIF_STAT_TX_COUNTER (0xd485b327UL) > +#define HIF_TEST0 (0xdab033c0UL) > +#define HIF_TEST0_DATA (0xb7f3cba2UL) > +#define HIF_TEST1 (0xadb70356UL) > +#define HIF_TEST1_DATA (0x7caf1807UL) > +#define HIF_TEST2 (0x34be52ecUL) > +#define HIF_TEST2_DATA (0xfa3b6aa9UL) > +#define HIF_TEST3 (0x43b9627aUL) > +#define HIF_TEST3_DATA (0x3167b90cUL) > +#define HIF_UUID0 (0xecba7918UL) > +#define HIF_UUID0_UUID0 (0x84b3f35eUL) > +#define HIF_UUID1 (0x9bbd498eUL) > +#define HIF_UUID1_UUID1 (0x55c3c87cUL) > +#define HIF_UUID2 (0x2b41834UL) > +#define HIF_UUID2_UUID2 (0xfd22835bUL) > +#define HIF_UUID3 (0x75b328a2UL) > +#define HIF_UUID3_UUID3 (0x2c52b879UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_HIF_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h > new file mode 100644 > index 0000000000..9066e20dc9 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h > @@ -0,0 +1,49 @@ > +/* > + * nthw_fpga_reg_defs_hsh.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_HSH_ > +#define _NTHW_FPGA_REG_DEFS_HSH_ > + > +/* HSH */ > +#define NTHW_MOD_HSH (0x501484bfUL) > +#define HSH_RCP_CTRL (0xb257f1b9UL) > +#define HSH_RCP_CTRL_ADR (0x5685bfbUL) > +#define HSH_RCP_CTRL_CNT (0x1560c22aUL) > +#define HSH_RCP_DATA (0x1d8673a0UL) > +#define HSH_RCP_DATA_AUTO_IPV4_MASK (0xa0d4de3bUL) > +#define HSH_RCP_DATA_HSH_TYPE (0x14cd0865UL) > +#define HSH_RCP_DATA_HSH_VALID (0xc89b0bd3UL) > +#define HSH_RCP_DATA_K (0xccdb0222UL) > +#define HSH_RCP_DATA_LOAD_DIST_TYPE (0x152a0a87UL) > +#define HSH_RCP_DATA_MAC_PORT_MASK (0x5160b288UL) > +#define HSH_RCP_DATA_P_MASK (0x8a555abbUL) > +#define HSH_RCP_DATA_QW0_OFS (0x276b79cfUL) > +#define HSH_RCP_DATA_QW0_PE (0x32014a20UL) > +#define HSH_RCP_DATA_QW4_OFS (0xd2ebdf0fUL) > +#define HSH_RCP_DATA_QW4_PE (0xbd63dd77UL) > +#define HSH_RCP_DATA_SEED (0xf8fc2c1cUL) > +#define HSH_RCP_DATA_SORT (0xed5f3d38UL) > +#define HSH_RCP_DATA_TNL_P (0x6e56b51eUL) > +#define HSH_RCP_DATA_TOEPLITZ (0xc1864a45UL) > +#define HSH_RCP_DATA_W8_OFS (0x68150d02UL) > +#define HSH_RCP_DATA_W8_PE (0x9387d583UL) > +#define HSH_RCP_DATA_W8_SORT (0x5c67eca8UL) > +#define HSH_RCP_DATA_W9_OFS (0x557524b2UL) > +#define HSH_RCP_DATA_W9_P (0x808204d9UL) > +#define HSH_RCP_DATA_W9_PE (0x2b3bb2e6UL) > +#define HSH_RCP_DATA_W9_SORT (0x973b3f0dUL) > +#define HSH_RCP_DATA_WORD_MASK (0x55c53a1fUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_HSH_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h > new file mode 100644 > index 0000000000..56248d5261 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h > @@ -0,0 +1,38 @@ > +/* > + * nthw_fpga_reg_defs_i2cm.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_I2CM_ > +#define _NTHW_FPGA_REG_DEFS_I2CM_ > + > +/* I2CM */ > +#define NTHW_MOD_I2CM (0x93bc7780UL) > +#define I2CM_CMD_STATUS (0xcb66305bUL) > +#define I2CM_CMD_STATUS_CMD_STATUS (0x9c9460a9UL) > +#define I2CM_CTRL (0x7c06d3b0UL) > +#define I2CM_CTRL_EN (0x57d0a8aaUL) > +#define I2CM_CTRL_IEN (0x9fdc39ebUL) > +#define I2CM_DATA (0xd3d751a9UL) > +#define I2CM_DATA_DATA (0x2ea487faUL) > +#define I2CM_IO_EXP (0xe8dfa320UL) > +#define I2CM_IO_EXP_INT_B (0x85e5ff3fUL) > +#define I2CM_IO_EXP_RST (0x207c9928UL) > +#define I2CM_PRER_HIGH (0xf1139b49UL) > +#define I2CM_PRER_HIGH_PRER_HIGH (0xc6ff6431UL) > +#define I2CM_PRER_LOW (0x84f76481UL) > +#define I2CM_PRER_LOW_PRER_LOW (0x396755aaUL) > +#define I2CM_SELECT (0xecd56d8eUL) > +#define I2CM_SELECT_SELECT (0xb9d992d8UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_I2CM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h > new file mode 100644 > index 0000000000..fcf9193b7d > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h > @@ -0,0 +1,41 @@ > +/* > + * nthw_fpga_reg_defs_ifr.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_IFR_ > +#define _NTHW_FPGA_REG_DEFS_IFR_ > + > +/* IFR */ > +#define NTHW_MOD_IFR (0x9b01f1e6UL) > +#define IFR_COUNTERS_CTRL (0x92ba13e6UL) > +#define IFR_COUNTERS_CTRL_ADR (0xecdeeda8UL) > +#define IFR_COUNTERS_CTRL_CNT (0xfcd67479UL) > +#define IFR_COUNTERS_DATA (0x3d6b91ffUL) > +#define IFR_COUNTERS_DATA_DROP (0x3ee57cc0UL) > +#define IFR_DF_BUF_CTRL (0xf60805e4UL) > +#define IFR_DF_BUF_CTRL_AVAILABLE (0x158f09c3UL) > +#define IFR_DF_BUF_CTRL_MTU_PROFILE (0x7cb4bc5aUL) > +#define IFR_DF_BUF_DATA (0x59d987fdUL) > +#define IFR_DF_BUF_DATA_FIFO_DAT (0xdbfdf650UL) > +#define IFR_RCP_CTRL (0xc6dfc47eUL) > +#define IFR_RCP_CTRL_ADR (0x68600d59UL) > +#define IFR_RCP_CTRL_CNT (0x78689488UL) > +#define IFR_RCP_DATA (0x690e4667UL) > +#define IFR_RCP_DATA_IPV4_DF_DROP (0xbfd1ca18UL) > +#define IFR_RCP_DATA_IPV4_EN (0xb48ee13aUL) > +#define IFR_RCP_DATA_IPV6_DROP (0x4fbf34a2UL) > +#define IFR_RCP_DATA_IPV6_EN (0x1e8729b1UL) > +#define IFR_RCP_DATA_MTU (0xa436ee13UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_IFR_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h > new file mode 100644 > index 0000000000..45c7516a48 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h > @@ -0,0 +1,28 @@ > +/* > + * nthw_fpga_reg_defs_igam.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_IGAM_ > +#define _NTHW_FPGA_REG_DEFS_IGAM_ > + > +/* IGAM */ > +#define NTHW_MOD_IGAM (0xf3b0bfb9UL) > +#define IGAM_BASE (0xcdbfd276UL) > +#define IGAM_BASE_BUSY (0x2a018901UL) > +#define IGAM_BASE_CMD (0x61c2922dUL) > +#define IGAM_BASE_PTR (0x1076934dUL) > +#define IGAM_DATA (0xa0f8df74UL) > +#define IGAM_DATA_DATA (0x6544d6f2UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_IGAM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h > new file mode 100644 > index 0000000000..42a60cff12 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h > @@ -0,0 +1,96 @@ > +/* > + * nthw_fpga_reg_defs_iic.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_IIC_ > +#define _NTHW_FPGA_REG_DEFS_IIC_ > + > +/* IIC */ > +#define NTHW_MOD_IIC (0x7629cddbUL) > +#define IIC_ADR (0x94832a56UL) > +#define IIC_ADR_SLV_ADR (0xe34a95b4UL) > +#define IIC_CR (0x2e99752eUL) > +#define IIC_CR_EN (0x38b0a8b8UL) > +#define IIC_CR_GC_EN (0x6a93c608UL) > +#define IIC_CR_MSMS (0xd3370cefUL) > +#define IIC_CR_RST (0x9d83289fUL) > +#define IIC_CR_RSTA (0xb3f49376UL) > +#define IIC_CR_TX (0x9fbd3ef9UL) > +#define IIC_CR_TXAK (0x4daa2c41UL) > +#define IIC_CR_TXFIFO_RESET (0x9d442d45UL) > +#define IIC_DGIE (0xca86a888UL) > +#define IIC_DGIE_GIE (0xda9f5b68UL) > +#define IIC_GPO (0xdda6ed68UL) > +#define IIC_GPO_GPO_VAL (0x6c51285eUL) > +#define IIC_IER (0x838b4aafUL) > +#define IIC_IER_INT0 (0x27d5f60eUL) > +#define IIC_IER_INT1 (0x50d2c698UL) > +#define IIC_IER_INT2 (0xc9db9722UL) > +#define IIC_IER_INT3 (0xbedca7b4UL) > +#define IIC_IER_INT4 (0x20b83217UL) > +#define IIC_IER_INT5 (0x57bf0281UL) > +#define IIC_IER_INT6 (0xceb6533bUL) > +#define IIC_IER_INT7 (0xb9b163adUL) > +#define IIC_ISR (0x9f13ff78UL) > +#define IIC_ISR_INT0 (0x23db5ffaUL) > +#define IIC_ISR_INT1 (0x54dc6f6cUL) > +#define IIC_ISR_INT2 (0xcdd53ed6UL) > +#define IIC_ISR_INT3 (0xbad20e40UL) > +#define IIC_ISR_INT4 (0x24b69be3UL) > +#define IIC_ISR_INT5 (0x53b1ab75UL) > +#define IIC_ISR_INT6 (0xcab8facfUL) > +#define IIC_ISR_INT7 (0xbdbfca59UL) > +#define IIC_RX_FIFO (0x46f255afUL) > +#define IIC_RX_FIFO_RXDATA (0x90c24f9dUL) > +#define IIC_RX_FIFO_OCY (0xc6457d11UL) > +#define IIC_RX_FIFO_OCY_OCY_VAL (0xee6b4716UL) > +#define IIC_RX_FIFO_PIRQ (0x4201f0b4UL) > +#define IIC_RX_FIFO_PIRQ_CMP_VAL (0xc5121291UL) > +#define IIC_SOFTR (0xfb3f55bfUL) > +#define IIC_SOFTR_RKEY (0x8c9a6beeUL) > +#define IIC_SR (0x645b677fUL) > +#define IIC_SR_AAS (0x66a5d25dUL) > +#define IIC_SR_ABGC (0x4831e30UL) > +#define IIC_SR_BB (0x1ea7e5d6UL) > +#define IIC_SR_RXFIFO_EMPTY (0xe419563UL) > +#define IIC_SR_RXFIFO_FULL (0x60ecb95aUL) > +#define IIC_SR_SRW (0x1f8520c8UL) > +#define IIC_SR_TXFIFO_EMPTY (0xe17c3083UL) > +#define IIC_SR_TXFIFO_FULL (0x88597319UL) > +#define IIC_TBUF (0xe32a311bUL) > +#define IIC_TBUF_TBUF_VAL (0xd48a5ee6UL) > +#define IIC_TEN_ADR (0xb5d88814UL) > +#define IIC_TEN_ADR_MSB_SLV_ADR (0x1bf3647bUL) > +#define IIC_THDDAT (0x9dc42de9UL) > +#define IIC_THDDAT_THDDAT_VAL (0xa4fe6780UL) > +#define IIC_THDSTA (0xdec59ae3UL) > +#define IIC_THDSTA_THDSTA_VAL (0xc3705793UL) > +#define IIC_THIGH (0x43194ec3UL) > +#define IIC_THIGH_THIGH_VAL (0x320d9d1bUL) > +#define IIC_TLOW (0x3329c638UL) > +#define IIC_TLOW_TLOW_VAL (0x167c1ff3UL) > +#define IIC_TSUDAT (0x6251bb80UL) > +#define IIC_TSUDAT_TSUDAT_VAL (0x7b1fdb1dUL) > +#define IIC_TSUSTA (0x21500c8aUL) > +#define IIC_TSUSTA_TSUSTA_VAL (0x1c91eb0eUL) > +#define IIC_TSUSTO (0xc6e8218dUL) > +#define IIC_TSUSTO_TSUSTO_VAL (0x4a908671UL) > +#define IIC_TX_FIFO (0x25226095UL) > +#define IIC_TX_FIFO_START (0xc24fb6c4UL) > +#define IIC_TX_FIFO_STOP (0xe7ae5f6cUL) > +#define IIC_TX_FIFO_TXDATA (0xbe59e736UL) > +#define IIC_TX_FIFO_OCY (0x2ef0b752UL) > +#define IIC_TX_FIFO_OCY_OCY_VAL (0x73b74c05UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_IIC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h > new file mode 100644 > index 0000000000..a4fffb11ab > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h > @@ -0,0 +1,29 @@ > +/* > + * nthw_fpga_reg_defs_ins.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_INS_ > +#define _NTHW_FPGA_REG_DEFS_INS_ > + > +/* INS */ > +#define NTHW_MOD_INS (0x24df4b78UL) > +#define INS_RCP_CTRL (0x93de4e05UL) > +#define INS_RCP_CTRL_ADR (0x3ae620a8UL) > +#define INS_RCP_CTRL_CNT (0x2aeeb979UL) > +#define INS_RCP_DATA (0x3c0fcc1cUL) > +#define INS_RCP_DATA_DYN (0xc6aa4fccUL) > +#define INS_RCP_DATA_LEN (0x2ece4329UL) > +#define INS_RCP_DATA_OFS (0x64a3c26aUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_INS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h > new file mode 100644 > index 0000000000..dec8fccdbb > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h > @@ -0,0 +1,44 @@ > +/* > + * nthw_fpga_reg_defs_ioa.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_IOA_ > +#define _NTHW_FPGA_REG_DEFS_IOA_ > + > +/* IOA */ > +#define NTHW_MOD_IOA (0xce7d0b71UL) > +#define IOA_RECIPE_CTRL (0x3fd57501UL) > +#define IOA_RECIPE_CTRL_ADR (0xa12e8b86UL) > +#define IOA_RECIPE_CTRL_CNT (0xb1261257UL) > +#define IOA_RECIPE_DATA (0x9004f718UL) > +#define IOA_RECIPE_DATA_QUEUE_ID (0x7b82dc9eUL) > +#define IOA_RECIPE_DATA_QUEUE_OVERRIDE_EN (0x65468a0bUL) > +#define IOA_RECIPE_DATA_TUNNEL_POP (0xaa73a3b3UL) > +#define IOA_RECIPE_DATA_VLAN_DEI (0xf27320c4UL) > +#define IOA_RECIPE_DATA_VLAN_PCP (0xdb6d242eUL) > +#define IOA_RECIPE_DATA_VLAN_POP (0x77d86b22UL) > +#define IOA_RECIPE_DATA_VLAN_PUSH (0x458ecac5UL) > +#define IOA_RECIPE_DATA_VLAN_TPID_SEL (0xe1660623UL) > +#define IOA_RECIPE_DATA_VLAN_VID (0x3fd5646bUL) > +#define IOA_ROA_EPP_CTRL (0xab29dcacUL) > +#define IOA_ROA_EPP_CTRL_ADR (0x87edd55dUL) > +#define IOA_ROA_EPP_CTRL_CNT (0x97e54c8cUL) > +#define IOA_ROA_EPP_DATA (0x4f85eb5UL) > +#define IOA_ROA_EPP_DATA_PUSH_TUNNEL (0xc5d915c6UL) > +#define IOA_ROA_EPP_DATA_TX_PORT (0xb127a8d0UL) > +#define IOA_VLAN_TPID_SPECIAL (0x7812827cUL) > +#define IOA_VLAN_TPID_SPECIAL_CUSTTPID0 (0x4333af30UL) > +#define IOA_VLAN_TPID_SPECIAL_CUSTTPID1 (0x34349fa6UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_IOA_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h > new file mode 100644 > index 0000000000..8dc7f26d71 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h > @@ -0,0 +1,84 @@ > +/* > + * nthw_fpga_reg_defs_ipf.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_IPF_ > +#define _NTHW_FPGA_REG_DEFS_IPF_ > + > +/* IPF */ > +#define NTHW_MOD_IPF (0x9d43904cUL) > +#define IPF_CTRL (0x3b50b688UL) > +#define IPF_CTRL_ALL_UNM (0x8b16703UL) > +#define IPF_CTRL_ALL_UNM_INNER (0x16068451UL) > +#define IPF_CTRL_DEL_UNM (0x7d86196cUL) > +#define IPF_CTRL_ENABLE (0xd827d73eUL) > +#define IPF_CTRL_FST_UNM (0x6f063580UL) > +#define IPF_CTRL_PASSIVE (0x441c1633UL) > +#define IPF_CTRL_PERSIST (0xf52aa922UL) > +#define IPF_DEBUG (0x4418698UL) > +#define IPF_DEBUG_FTF_N (0x2cda6a1fUL) > +#define IPF_DEBUG_LIMIT_N (0x8588c40eUL) > +#define IPF_EXPIRE (0xa1d1a3e0UL) > +#define IPF_EXPIRE_PERSIST (0x8d985989UL) > +#define IPF_EXPIRE_T (0x37792e51UL) > +#define IPF_FTF_DEBUG (0x2e34232dUL) > +#define IPF_FTF_DEBUG_N (0x59f772edUL) > +#define IPF_RCP_CTRL (0xaed9eb64UL) > +#define IPF_RCP_CTRL_ADR (0x71e6f593UL) > +#define IPF_RCP_CTRL_CNT (0x61ee6c42UL) > +#define IPF_RCP_DATA (0x108697dUL) > +#define IPF_RCP_DATA_ALL_UNM (0xe9fd243cUL) > +#define IPF_RCP_DATA_COL_INH (0x9da0e920UL) > +#define IPF_RCP_DATA_DEL_UNM (0x9cca5a53UL) > +#define IPF_RCP_DATA_DISC_INH (0x8914e9a0UL) > +#define IPF_RCP_DATA_DUP_INH (0x5f5a8cd0UL) > +#define IPF_RCP_DATA_ENABLE (0x9afcf075UL) > +#define IPF_RCP_DATA_FST_UNM (0x8e4a76bfUL) > +#define IPF_RCP_DATA_GROUP_ID (0xffc993cdUL) > +#define IPF_RCP_DATA_HASH_CENC (0x812cf8c7UL) > +#define IPF_RCP_DATA_HSH_INH (0x1e33d9faUL) > +#define IPF_RCP_DATA_PORT_GROUP_ID (0xd786e10bUL) > +#define IPF_RCP_DATA_QUEUE_INH (0x6cafcc65UL) > +#define IPF_RCP_DATA_UNMQ_HI (0xb6bb8520UL) > +#define IPF_RCP_DATA_UNMQ_LO (0x3bb4e511UL) > +#define IPF_RCP_DATA_UNM_FLAG_CENC (0xbb06fcddUL) > +#define IPF_SIZE_DEBUG (0xa3c27df1UL) > +#define IPF_SIZE_DEBUG_N (0xf8a909fbUL) > +#define IPF_STAT_MAX1 (0xbb09703fUL) > +#define IPF_STAT_MAX1_N (0xd361974dUL) > +#define IPF_STAT_MAX2 (0x22002185UL) > +#define IPF_STAT_MAX2_N (0xd1272914UL) > +#define IPF_STAT_MAX3 (0x55071113UL) > +#define IPF_STAT_MAX3_N (0xd0e54323UL) > +#define IPF_STAT_MAX4 (0xcb6384b0UL) > +#define IPF_STAT_MAX4_N (0xd5aa55a6UL) > +#define IPF_TIMEOUT (0x9b16c106UL) > +#define IPF_TIMEOUT_T (0x9ce14088UL) > +#define IPF_UNMQ_CTRL (0x9c6c2c32UL) > +#define IPF_UNMQ_CTRL_ADR (0x5a052e55UL) > +#define IPF_UNMQ_CTRL_CNT (0x4a0db784UL) > +#define IPF_UNMQ_DATA (0x33bdae2bUL) > +#define IPF_UNMQ_DATA_CENC (0xe444d471UL) > +#define IPF_UNMQ_DATA_EN (0x60b4924bUL) > +#define IPF_UNMQ_DATA_ID (0x2cd43459UL) > +#define IPF_UNM_FEED (0x5be1a729UL) > +#define IPF_UNM_FEED_ADDR (0x109a9424UL) > +#define IPF_UNM_FEED_CNT (0xab58226eUL) > +#define IPF_UNM_FEED_FEED (0x614042baUL) > +#define IPF_UNM_FEED_FEED_VALID (0xba08d9c3UL) > +#define IPF_UNM_FEED_RES1 (0x82ccb216UL) > +#define IPF_UNM_FEED_RES2 (0x1bc5e3acUL) > +#define IPF_UNM_FEED_RES3 (0x6cc2d33aUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_IPF_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h > new file mode 100644 > index 0000000000..ec9a928eda > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h > @@ -0,0 +1,125 @@ > +/* > + * nthw_fpga_reg_defs_km.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_KM_ > +#define _NTHW_FPGA_REG_DEFS_KM_ > + > +/* KM */ > +#define NTHW_MOD_KM (0xcfbd9dbeUL) > +#define KM_CAM_CTRL (0x601dcc08UL) > +#define KM_CAM_CTRL_ADR (0xee5e10b0UL) > +#define KM_CAM_CTRL_CNT (0xfe568961UL) > +#define KM_CAM_DATA (0xcfcc4e11UL) > +#define KM_CAM_DATA_FT0 (0x138589ccUL) > +#define KM_CAM_DATA_FT1 (0x6482b95aUL) > +#define KM_CAM_DATA_FT2 (0xfd8be8e0UL) > +#define KM_CAM_DATA_FT3 (0x8a8cd876UL) > +#define KM_CAM_DATA_FT4 (0x14e84dd5UL) > +#define KM_CAM_DATA_FT5 (0x63ef7d43UL) > +#define KM_CAM_DATA_W0 (0xff7d6c5fUL) > +#define KM_CAM_DATA_W1 (0x887a5cc9UL) > +#define KM_CAM_DATA_W2 (0x11730d73UL) > +#define KM_CAM_DATA_W3 (0x66743de5UL) > +#define KM_CAM_DATA_W4 (0xf810a846UL) > +#define KM_CAM_DATA_W5 (0x8f1798d0UL) > +#define KM_RCP_CTRL (0xf8dbfdd1UL) > +#define KM_RCP_CTRL_ADR (0xf3df02baUL) > +#define KM_RCP_CTRL_CNT (0xe3d79b6bUL) > +#define KM_RCP_DATA (0x570a7fc8UL) > +#define KM_RCP_DATA_BANK_A (0x7fd7bd1UL) > +#define KM_RCP_DATA_BANK_B (0x9ef42a6bUL) > +#define KM_RCP_DATA_DUAL (0x428e6b23UL) > +#define KM_RCP_DATA_DW0_B_DYN (0x342bde5aUL) > +#define KM_RCP_DATA_DW0_B_OFS (0x962253fcUL) > +#define KM_RCP_DATA_DW10_DYN (0x54eccf30UL) > +#define KM_RCP_DATA_DW10_OFS (0xf6e54296UL) > +#define KM_RCP_DATA_DW10_SEL_A (0x6237e887UL) > +#define KM_RCP_DATA_DW10_SEL_B (0xfb3eb93dUL) > +#define KM_RCP_DATA_DW2_B_DYN (0xa3b4cf73UL) > +#define KM_RCP_DATA_DW2_B_OFS (0x1bd42d5UL) > +#define KM_RCP_DATA_DW8_B_DYN (0x7c4903dUL) > +#define KM_RCP_DATA_DW8_B_OFS (0xa5cd1d9bUL) > +#define KM_RCP_DATA_DW8_DYN (0x3f6b49f0UL) > +#define KM_RCP_DATA_DW8_OFS (0x9d62c456UL) > +#define KM_RCP_DATA_DW8_SEL_A (0xad16725bUL) > +#define KM_RCP_DATA_DW8_SEL_B (0x341f23e1UL) > +#define KM_RCP_DATA_EL_A (0x4335d7dbUL) > +#define KM_RCP_DATA_EL_B (0xda3c8661UL) > +#define KM_RCP_DATA_FLOW_SET (0x6b56d647UL) > +#define KM_RCP_DATA_FTM_A (0xdb75ed61UL) > +#define KM_RCP_DATA_FTM_B (0x427cbcdbUL) > +#define KM_RCP_DATA_INFO_A (0x2dd79cf0UL) > +#define KM_RCP_DATA_INFO_B (0xb4decd4aUL) > +#define KM_RCP_DATA_KEYWAY_A (0xd0e5dc89UL) > +#define KM_RCP_DATA_KEYWAY_B (0x49ec8d33UL) > +#define KM_RCP_DATA_KL_A (0xa3eaa0e8UL) > +#define KM_RCP_DATA_KL_B (0x3ae3f152UL) > +#define KM_RCP_DATA_MASK_A (0x54d84646UL) > +#define KM_RCP_DATA_MASK_B (0xcdd117fcUL) > +#define KM_RCP_DATA_PAIRED (0x7847653UL) > +#define KM_RCP_DATA_QW0_B_DYN (0xd27cd964UL) > +#define KM_RCP_DATA_QW0_B_OFS (0x707554c2UL) > +#define KM_RCP_DATA_QW0_DYN (0x3afdb158UL) > +#define KM_RCP_DATA_QW0_OFS (0x98f43cfeUL) > +#define KM_RCP_DATA_QW0_SEL_A (0x78ae3b02UL) > +#define KM_RCP_DATA_QW0_SEL_B (0xe1a76ab8UL) > +#define KM_RCP_DATA_QW4_B_DYN (0x2633fd77UL) > +#define KM_RCP_DATA_QW4_B_OFS (0x843a70d1UL) > +#define KM_RCP_DATA_QW4_DYN (0xcf7d1798UL) > +#define KM_RCP_DATA_QW4_OFS (0x6d749a3eUL) > +#define KM_RCP_DATA_QW4_SEL_A (0x8ce11f11UL) > +#define KM_RCP_DATA_QW4_SEL_B (0x15e84eabUL) > +#define KM_RCP_DATA_SW4_B_DYN (0x8c5d5f1UL) > +#define KM_RCP_DATA_SW4_B_OFS (0xaacc5857UL) > +#define KM_RCP_DATA_SW5_B_DYN (0xaeb2de45UL) > +#define KM_RCP_DATA_SW5_B_OFS (0xcbb53e3UL) > +#define KM_RCP_DATA_SW8_B_DYN (0xcf65bf85UL) > +#define KM_RCP_DATA_SW8_B_OFS (0x6d6c3223UL) > +#define KM_RCP_DATA_SW8_DYN (0x9d12ebb0UL) > +#define KM_RCP_DATA_SW8_OFS (0x3f1b6616UL) > +#define KM_RCP_DATA_SW8_SEL_A (0x65b75de3UL) > +#define KM_RCP_DATA_SW8_SEL_B (0xfcbe0c59UL) > +#define KM_RCP_DATA_SW9_B_DYN (0x6912b431UL) > +#define KM_RCP_DATA_SW9_B_OFS (0xcb1b3997UL) > +#define KM_RCP_DATA_SW9_DYN (0xa072c200UL) > +#define KM_RCP_DATA_SW9_OFS (0x27b4fa6UL) > +#define KM_RCP_DATA_SW9_SEL_A (0xc3c05657UL) > +#define KM_RCP_DATA_SW9_SEL_B (0x5ac907edUL) > +#define KM_RCP_DATA_SWX_CCH (0x5821d596UL) > +#define KM_RCP_DATA_SWX_OVS_SB (0x808773bdUL) > +#define KM_RCP_DATA_SWX_SEL_A (0xee011106UL) > +#define KM_RCP_DATA_SWX_SEL_B (0x770840bcUL) > +#define KM_RCP_DATA_SYNERGY_MODE (0x35a76c4aUL) > +#define KM_STATUS (0x2f1f9d13UL) > +#define KM_STATUS_TCQ_RDY (0x653553c4UL) > +#define KM_TCAM_CTRL (0x18fbc021UL) > +#define KM_TCAM_CTRL_ADR (0x6c84a404UL) > +#define KM_TCAM_CTRL_CNT (0x7c8c3dd5UL) > +#define KM_TCAM_DATA (0xb72a4238UL) > +#define KM_TCAM_DATA_T (0xa995a553UL) > +#define KM_TCI_CTRL (0x1a6da705UL) > +#define KM_TCI_CTRL_ADR (0xc7590d78UL) > +#define KM_TCI_CTRL_CNT (0xd75194a9UL) > +#define KM_TCI_DATA (0xb5bc251cUL) > +#define KM_TCI_DATA_COLOR (0x324017ecUL) > +#define KM_TCI_DATA_FT (0x38afba77UL) > +#define KM_TCQ_CTRL (0xf5e827f3UL) > +#define KM_TCQ_CTRL_ADR (0xf320cc64UL) > +#define KM_TCQ_CTRL_CNT (0xe32855b5UL) > +#define KM_TCQ_DATA (0x5a39a5eaUL) > +#define KM_TCQ_DATA_BANK_MASK (0x97cf4b5aUL) > +#define KM_TCQ_DATA_QUAL (0x4422cc93UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_KM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h > new file mode 100644 > index 0000000000..6c2014e468 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h > @@ -0,0 +1,177 @@ > +/* > + * nthw_fpga_reg_defs_mac.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_ > +#define _NTHW_FPGA_REG_DEFS_MAC_ > + > +/* MAC */ > +#define NTHW_MOD_MAC (0xb9f9ef0fUL) > +#define MAC_CONF_SERDES_BITFRAG (0xb22a0224UL) > +#define MAC_CONF_SERDES_BITFRAG_BITFRAG (0x4980ae1bUL) > +#define MAC_CONF_SERDES_DELAY (0xb106e3baUL) > +#define MAC_CONF_SERDES_DELAY_DELAY (0x3a5a3634UL) > +#define MAC_CONF_SERDES_REORDER (0x7b67c6e7UL) > +#define MAC_CONF_SERDES_REORDER_REORDER (0x1b75028cUL) > +#define MAC_FAULTY_BLK (0x221eb456UL) > +#define MAC_FAULTY_BLK_DATA (0x96b88c4fUL) > +#define MAC_HOST_STAT_BYTE_FILL (0xbb1fc15cUL) > +#define MAC_HOST_STAT_BYTE_FILL_CNT (0x91d6eb19UL) > +#define MAC_INT (0x9100902fUL) > +#define MAC_INT_EN (0x93a8ee79UL) > +#define MAC_INT_MAX_PACE (0x65054b07UL) > +#define MAC_LINK_SUMMARY (0x7f2f60ceUL) > +#define MAC_LINK_SUMMARY_ABS (0x2c3fcbfaUL) > +#define MAC_LINK_SUMMARY_GBOX_INTERR (0x35d304b0UL) > +#define MAC_LINK_SUMMARY_GLB_ALARMN (0x8eac9ca9UL) > +#define MAC_LINK_SUMMARY_LH_ABS (0x24f77279UL) > +#define MAC_LINK_SUMMARY_LH_GLB_ALARMN (0x1646a58eUL) > +#define MAC_LINK_SUMMARY_LH_LOCAL_FAULT (0x36543c21UL) > +#define MAC_LINK_SUMMARY_LH_REMOTE_FAULT (0x97481576UL) > +#define MAC_LINK_SUMMARY_LH_RX_LOS (0x837691acUL) > +#define MAC_LINK_SUMMARY_LINK_DOWN_CNT (0x1879082dUL) > +#define MAC_LINK_SUMMARY_LL_PHY_LINK_STATE (0x64cc82a2UL) > +#define MAC_LINK_SUMMARY_LOCAL_FAULT (0x93c66373UL) > +#define MAC_LINK_SUMMARY_NT_PHY_LINK_STATE (0x25c4b3b4UL) > +#define MAC_LINK_SUMMARY_REMOTE_FAULT (0x1288b7f1UL) > +#define MAC_LINK_SUMMARY_RX_LOS (0xc0bd6b0eUL) > +#define MAC_MAC_STAT_BYTE (0x7c8bb288UL) > +#define MAC_MAC_STAT_BYTE_CNT (0x7e7a0bd3UL) > +#define MAC_MAC_STAT_CRC (0x39d27996UL) > +#define MAC_MAC_STAT_CRC_CNT (0x3e8901dcUL) > +#define MAC_MAC_STAT_CV (0xd9cde09fUL) > +#define MAC_MAC_STAT_CV_CNT (0xdc1321cfUL) > +#define MAC_MAC_STAT_FRAME (0xc71e1060UL) > +#define MAC_MAC_STAT_FRAME_CNT (0xe7c8ff51UL) > +#define MAC_MAC_STAT_MICRO_DROP (0xe4d098cbUL) > +#define MAC_MAC_STAT_MICRO_DROP_CNT (0x659aa0dfUL) > +#define MAC_MAC_STAT_RATE_DROP (0x403c4fbbUL) > +#define MAC_MAC_STAT_RATE_DROP_CNT (0xa513f8e7UL) > +#define MAC_MAC_STAT_TRUNC (0x45f29d8UL) > +#define MAC_MAC_STAT_TRUNC_CNT (0xffbbaa75UL) > +#define MAC_MDS_CEN_VAL (0xa9a494fdUL) > +#define MAC_MDS_CEN_VAL_VAL (0x74e79a1bUL) > +#define MAC_MDS_CONF (0xd4f79721UL) > +#define MAC_MDS_CONF_CENTER_REC_ENA (0x61ec9442UL) > +#define MAC_MDS_CONF_CLR_STAT (0xdc56da95UL) > +#define MAC_MDS_CONF_ENA_TS_MOD (0xf071678dUL) > +#define MAC_MDS_CONF_REC_ENA (0x9c1d77c5UL) > +#define MAC_MDS_CONF_TIME_MODE (0x4f2a4dcaUL) > +#define MAC_MDS_DATA (0x6df7edeaUL) > +#define MAC_MDS_DATA_DATA (0x24589197UL) > +#define MAC_MDS_FRAMES (0x40ca5335UL) > +#define MAC_MDS_FRAMES_CNT (0xff4f25c0UL) > +#define MAC_MDS_MAX (0x230406d6UL) > +#define MAC_MDS_MAX_MAX (0x54809081UL) > +#define MAC_MDS_MIN (0x1f09398fUL) > +#define MAC_MDS_MIN_MIN (0x6b7e4f97UL) > +#define MAC_MDS_STAT (0xe0bce1a8UL) > +#define MAC_MDS_STAT_CLR_BUSY (0x4a5ac60dUL) > +#define MAC_MDS_STAT_HIT_MAX (0xe5a34512UL) > +#define MAC_MDS_STAT_HIT_MIN (0xd9ae7a4bUL) > +#define MAC_MDS_VAL_REC (0x8ec946abUL) > +#define MAC_MDS_VAL_REC_VALUE (0xe4e373beUL) > +#define MAC_MDS_VAL_REC_FRAME (0x8c12c923UL) > +#define MAC_MDS_VAL_REC_FRAME_VALUE (0xd76728beUL) > +#define MAC_NT_PORT_CTRL (0x8cd09e7cUL) > +#define MAC_NT_PORT_CTRL_LED_MODE (0x8486e464UL) > +#define MAC_RAM_MDS_ADDR (0xad17b5f2UL) > +#define MAC_RAM_MDS_ADDR_ADR (0x439fe32bUL) > +#define MAC_RAM_MDS_ADDR_CLR_RAM (0x824a2a22UL) > +#define MAC_RAM_MDS_ADDR_RD_DONE (0x4d858fc4UL) > +#define MAC_RAM_MDS_ADDR_RD_ENA (0xb0e2aae4UL) > +#define MAC_RAW_ADDR (0xfeacc28aUL) > +#define MAC_RAW_ADDR_ADR (0x49f962b0UL) > +#define MAC_RAW_ADDR_RDENA (0x57a8bee0UL) > +#define MAC_RAW_ADDR_RD_DONE (0x1441bde9UL) > +#define MAC_RAW_CTRL (0xae1421c5UL) > +#define MAC_RAW_CTRL_OVERWR_LM (0x4b06da1cUL) > +#define MAC_RAW_CTRL_RESTART (0xc0d2b66fUL) > +#define MAC_RAW_CTRL_TG_ACT (0x40471be4UL) > +#define MAC_RAW_CTRL_TG_ENA (0x9f3d299eUL) > +#define MAC_RAW_CTRL_WRAP (0x11e8b136UL) > +#define MAC_RAW_DATA (0x1c5a3dcUL) > +#define MAC_RAW_DATA_RAW_DATA (0xcb2757bcUL) > +#define MAC_RAW_REPETITION (0xbbec07c6UL) > +#define MAC_RAW_REPETITION_CNT (0xe998b255UL) > +#define MAC_RX_CONFIG (0x69191a34UL) > +#define MAC_RX_CONFIG_DESCRAMB (0xcd5890eUL) > +#define MAC_RX_CONFIG_HOST_CLR_CNT (0xb1ea5438UL) > +#define MAC_RX_CONFIG_MAC_CLR_CNT (0x5181c6edUL) > +#define MAC_RX_CONFIG_MIN_RX_FRAME (0xcf749efeUL) > +#define MAC_RX_CONFIG_NT_DEBOUNCE_LATENCY (0x39a4b7f3UL) > +#define MAC_RX_CONFIG_NT_FORCE_LINK_DOWN (0x361dbc83UL) > +#define MAC_RX_CONFIG_NT_LINKUP_LATENCY (0xe25cf44aUL) > +#define MAC_RX_CONFIG_RST_BLK_ERR (0x476bf210UL) > +#define MAC_RX_CONFIG_RX_MAC_EN (0xbcb6ab91UL) > +#define MAC_RX_CONFIG_TS_EOP (0xc648dd62UL) > +#define MAC_RX_CONFIG_TXRX_LOOP (0x66156fdfUL) > +#define MAC_RX_CONFIG2 (0x3b0853a2UL) > +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_INT (0x15c7f251UL) > +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (0xadc9cd69UL) > +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_RST (0xfad8d2dcUL) > +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_INT (0x76a6fa30UL) > +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_LINK (0x971ffdafUL) > +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_RST (0x99b9dabdUL) > +#define MAC_RX_STATUS (0xc6935054UL) > +#define MAC_RX_STATUS_CORE_MODE (0xb8548429UL) > +#define MAC_RX_STATUS_LOCAL_FAULT (0x4d495f63UL) > +#define MAC_RX_STATUS_REMOTE_FAULT (0xfe128a9UL) > +#define MAC_RX_STATUS_RXTX_OVERFLOW (0xc63536a2UL) > +#define MAC_RX_STATUS_VERSION (0x9bf530b7UL) > +#define MAC_TFG_ADDR (0xfeb2f718UL) > +#define MAC_TFG_ADDR_ADR (0xa851533bUL) > +#define MAC_TFG_ADDR_RDENA (0xde011ef2UL) > +#define MAC_TFG_ADDR_RD_DONE (0xba63e77bUL) > +#define MAC_TFG_CTRL (0xae0a1457UL) > +#define MAC_TFG_CTRL_ID_ENA (0x94e59ae3UL) > +#define MAC_TFG_CTRL_ID_POS (0x64aabb71UL) > +#define MAC_TFG_CTRL_RESTART (0x6ef0ecfdUL) > +#define MAC_TFG_CTRL_TG_ACT (0xb377c30cUL) > +#define MAC_TFG_CTRL_TG_ENA (0x6c0df176UL) > +#define MAC_TFG_CTRL_TIME_MODE (0xc7d30a61UL) > +#define MAC_TFG_CTRL_WRAP (0x6b6343afUL) > +#define MAC_TFG_DATA (0x1db964eUL) > +#define MAC_TFG_DATA_GAP (0x1eb74eaUL) > +#define MAC_TFG_DATA_ID (0xd1864536UL) > +#define MAC_TFG_DATA_LENGTH (0xdb3bb77fUL) > +#define MAC_TFG_FRAME_HDR (0xd36f87edUL) > +#define MAC_TFG_FRAME_HDR_HDR (0x33800156UL) > +#define MAC_TFG_REPETITION (0x3245a7d4UL) > +#define MAC_TFG_REPETITION_CNT (0x21514c05UL) > +#define MAC_TX_CONFIG (0x1a0363beUL) > +#define MAC_TX_CONFIG_CLR_STICKY (0x170875aUL) > +#define MAC_TX_CONFIG_CRC_ERR_INS (0xf0ac9462UL) > +#define MAC_TX_CONFIG_HOST_TX_ENA (0x5593f749UL) > +#define MAC_TX_CONFIG_MAC_LOOP (0x34b86cc7UL) > +#define MAC_TX_CONFIG_PCS_BIP_ERR (0xed089516UL) > +#define MAC_TX_CONFIG_PCS_DIS_BIP_INS (0xce7f1bc7UL) > +#define MAC_TX_CONFIG_PCS_IDLE (0x3a34f374UL) > +#define MAC_TX_CONFIG_PCS_IDLE_DIS (0x3899c1f1UL) > +#define MAC_TX_CONFIG_PCS_LOCAL_FAULT (0xdfeb9ecdUL) > +#define MAC_TX_CONFIG_PCS_LOCAL_FAULT_DIS (0xce2c57b5UL) > +#define MAC_TX_CONFIG_PCS_REMOTE_FAULT (0x3e1d0487UL) > +#define MAC_TX_CONFIG_PCS_REMOTE_FAULT_DIS (0x5fea461fUL) > +#define MAC_TX_CONFIG_PCS_SCRAMB_ENA (0xaa28e162UL) > +#define MAC_TX_CONFIG_PCS_SCRAMB_ERR (0xc8e1fde1UL) > +#define MAC_TX_CONFIG_TIME_OFFSET_TX (0x78fff470UL) > +#define MAC_TX_CONFIG_TS_EOP (0x95d9b486UL) > +#define MAC_TX_STATUS (0xb58929deUL) > +#define MAC_TX_STATUS_PCS_ERR (0x1c890ea7UL) > +#define MAC_TX_STATUS_TX_MAC_ST (0x5ac922d9UL) > +#define MAC_TX_STATUS_UNDER_FLOW (0x49718623UL) > +#define MAC_UPD_RX_COUNTERS (0x82256265UL) > +#define MAC_UPD_RX_COUNTERS_TRIGGER (0x29f90550UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h > new file mode 100644 > index 0000000000..3ad544798c > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h > @@ -0,0 +1,298 @@ > +/* > + * nthw_fpga_reg_defs_mac_pcs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_ > +#define _NTHW_FPGA_REG_DEFS_MAC_PCS_ > + > +/* MAC_PCS */ > +#define NTHW_MOD_MAC_PCS (0x7abe24c7UL) > +#define MAC_PCS_BAD_CODE (0x10d9fce5UL) > +#define MAC_PCS_BAD_CODE_CODE_ERR (0xb08ecc3fUL) > +#define MAC_PCS_BIP_ERR (0x7aead929UL) > +#define MAC_PCS_BIP_ERR_BIP_ERR (0x7e06ff82UL) > +#define MAC_PCS_BLOCK_LOCK (0xa44a8a0bUL) > +#define MAC_PCS_BLOCK_LOCK_LOCK (0x6adfd96bUL) > +#define MAC_PCS_BLOCK_LOCK_CHG (0xf0603b66UL) > +#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (0x9ef4519dUL) > +#define MAC_PCS_CLKRX_FRQ (0x999882b5UL) > +#define MAC_PCS_CLKRX_FRQ_RX_FREQ (0x8b935059UL) > +#define MAC_PCS_CLKTX_FRQ (0x4fc161a8UL) > +#define MAC_PCS_CLKTX_FRQ_TX_FREQ (0x10812ed5UL) > +#define MAC_PCS_DEBOUNCE_CTRL (0x37a3bb69UL) > +#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY > (0xf5845748UL) > +#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN > (0x1a8a9237UL) > +#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (0xaceccbf4UL) > +#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (0x7f66469eUL) > +#define MAC_PCS_DRP_CONFIG (0x1281f4d8UL) > +#define MAC_PCS_DRP_CONFIG_DRP_ADR (0x398caa76UL) > +#define MAC_PCS_DRP_CONFIG_DRP_DI (0x83b54c6fUL) > +#define MAC_PCS_DRP_CONFIG_DRP_EN (0x4cae88dUL) > +#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (0xc24d1deaUL) > +#define MAC_PCS_DRP_CONFIG_DRP_WREN (0x926388aeUL) > +#define MAC_PCS_DRP_CTRL (0x6df0725eUL) > +#define MAC_PCS_DRP_CTRL_ADR (0x5a9962c8UL) > +#define MAC_PCS_DRP_CTRL_DATA (0x2173d834UL) > +#define MAC_PCS_DRP_CTRL_DBG_BUSY (0x26dd3668UL) > +#define MAC_PCS_DRP_CTRL_DONE (0x9cadcbfcUL) > +#define MAC_PCS_DRP_CTRL_MOD_ADR (0x4352354dUL) > +#define MAC_PCS_DRP_CTRL_WREN (0xbed903edUL) > +#define MAC_PCS_DRP_DATA (0xc221f047UL) > +#define MAC_PCS_DRP_DATA_DRP_DO (0xbeb48b96UL) > +#define MAC_PCS_DRP_DATA_DRP_RDY (0x2238822eUL) > +#define MAC_PCS_FEC_CTRL (0x8eea756UL) > +#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (0xd0c0525eUL) > +#define MAC_PCS_FEC_CW_CNT (0x59e0c4deUL) > +#define MAC_PCS_FEC_CW_CNT_CW_CNT (0xd0b8ee0UL) > +#define MAC_PCS_FEC_ERR_CNT_0 (0xee88619cUL) > +#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (0x4fdf126bUL) > +#define MAC_PCS_FEC_ERR_CNT_1 (0x998f510aUL) > +#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (0x58a40628UL) > +#define MAC_PCS_FEC_ERR_CNT_2 (0x8600b0UL) > +#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (0x61293aedUL) > +#define MAC_PCS_FEC_ERR_CNT_3 (0x77813026UL) > +#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (0x76522eaeUL) > +#define MAC_PCS_FEC_LANE_DLY_0 (0xc18f945eUL) > +#define MAC_PCS_FEC_LANE_DLY_0_DLY (0xd9f1d54bUL) > +#define MAC_PCS_FEC_LANE_DLY_1 (0xb688a4c8UL) > +#define MAC_PCS_FEC_LANE_DLY_1_DLY (0xe491fcfbUL) > +#define MAC_PCS_FEC_LANE_DLY_2 (0x2f81f572UL) > +#define MAC_PCS_FEC_LANE_DLY_2_DLY (0xa331862bUL) > +#define MAC_PCS_FEC_LANE_DLY_3 (0x5886c5e4UL) > +#define MAC_PCS_FEC_LANE_DLY_3_DLY (0x9e51af9bUL) > +#define MAC_PCS_FEC_LANE_MAP (0x21d4bd54UL) > +#define MAC_PCS_FEC_LANE_MAP_MAPPING (0x87d12932UL) > +#define MAC_PCS_FEC_STAT (0x2a74290dUL) > +#define MAC_PCS_FEC_STAT_AM_LOCK (0x289b2822UL) > +#define MAC_PCS_FEC_STAT_AM_LOCK_0 (0xc824a589UL) > +#define MAC_PCS_FEC_STAT_AM_LOCK_1 (0xbf23951fUL) > +#define MAC_PCS_FEC_STAT_AM_LOCK_2 (0x262ac4a5UL) > +#define MAC_PCS_FEC_STAT_AM_LOCK_3 (0x512df433UL) > +#define MAC_PCS_FEC_STAT_BLOCK_LOCK (0x6a7d0f5fUL) > +#define MAC_PCS_FEC_STAT_BYPASS (0x2e754185UL) > +#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (0xfd302594UL) > +#define MAC_PCS_FEC_STAT_HI_SER (0xc3501768UL) > +#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (0xa8193db8UL) > +#define MAC_PCS_FEC_STAT_VALID (0x90dd6fe1UL) > +#define MAC_PCS_FEC_UCW_CNT (0xd1354660UL) > +#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (0xf90f900UL) > +#define MAC_PCS_FRAMING_ERR (0x73b6341dUL) > +#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (0xd4bfdbf4UL) > +#define MAC_PCS_GTY_CTL (0x325263edUL) > +#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (0x423e0e64UL) > +#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (0x35393ef2UL) > +#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (0xac306f48UL) > +#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (0xdb375fdeUL) > +#define MAC_PCS_GTY_CTL_RX (0x1f131df2UL) > +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (0x3c2aeb81UL) > +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (0x4b2ddb17UL) > +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (0xd2248aadUL) > +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (0xa523ba3bUL) > +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (0x78b8f7dbUL) > +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (0xfbfc74dUL) > +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (0x96b696f7UL) > +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (0xe1b1a661UL) > +#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (0xce64b22bUL) > +#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (0xb96382bdUL) > +#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (0x206ad307UL) > +#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (0x576de391UL) > +#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (0x80681033UL) > +#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (0xf76f20a5UL) > +#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (0x6e66711fUL) > +#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (0x19614189UL) > +#define MAC_PCS_GTY_CTL_RX_RATE_0 (0x6c6c737dUL) > +#define MAC_PCS_GTY_CTL_RX_RATE_1 (0x1b6b43ebUL) > +#define MAC_PCS_GTY_CTL_RX_RATE_2 (0x82621251UL) > +#define MAC_PCS_GTY_CTL_RX_RATE_3 (0xf56522c7UL) > +#define MAC_PCS_GTY_CTL_TX (0x4949ba74UL) > +#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (0xd2423364UL) > +#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (0xa54503f2UL) > +#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (0x3c4c5248UL) > +#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (0x4b4b62deUL) > +#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (0x208dcfeeUL) > +#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (0x578aff78UL) > +#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (0xce83aec2UL) > +#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (0xb9849e54UL) > +#define MAC_PCS_GTY_DIFF_CTL (0x8756c12fUL) > +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (0xf08ceefdUL) > +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (0x878bde6bUL) > +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (0x1e828fd1UL) > +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (0x6985bf47UL) > +#define MAC_PCS_GTY_LOOP (0x4dd7ddbUL) > +#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (0xd55e5438UL) > +#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (0xa25964aeUL) > +#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (0x3b503514UL) > +#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (0x4c570582UL) > +#define MAC_PCS_GTY_POST_CURSOR (0x4699c607UL) > +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (0x23ff66e9UL) > +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (0x54f8567fUL) > +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (0xcdf107c5UL) > +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (0xbaf63753UL) > +#define MAC_PCS_GTY_PRBS_SEL (0x6610ec4eUL) > +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (0xb535fd56UL) > +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (0xc232cdc0UL) > +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (0x5b3b9c7aUL) > +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (0x2c3cacecUL) > +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (0x15d0228bUL) > +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (0x62d7121dUL) > +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (0xfbde43a7UL) > +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (0x8cd97331UL) > +#define MAC_PCS_GTY_PRE_CURSOR (0x989e0463UL) > +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (0x264242bdUL) > +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (0x5145722bUL) > +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (0xc84c2391UL) > +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (0xbf4b1307UL) > +#define MAC_PCS_GTY_RX_BUF_STAT (0xf37901e8UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (0xab8b9404UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (0xdc8ca492UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (0x4585f528UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (0x3282c5beUL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 > (0x476782c4UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 > (0x3060b252UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 > (0xa969e3e8UL) > +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 > (0xde6ed37eUL) > +#define MAC_PCS_GTY_SCAN_CTL (0x782ddd2aUL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (0xc2791c66UL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (0xb57e2cf0UL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (0x2c777d4aUL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (0x5b704ddcUL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (0xebe5938aUL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (0x9ce2a31cUL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (0x5ebf2a6UL) > +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (0x72ecc230UL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (0x3243ecaeUL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (0x4544dc38UL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (0xdc4d8d82UL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (0xab4abd14UL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (0xf77381daUL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (0x8074b14cUL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (0x197de0f6UL) > +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (0x6e7ad060UL) > +#define MAC_PCS_GTY_SCAN_STAT (0x8070b7b9UL) > +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (0xe5ddd3f9UL) > +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (0x92dae36fUL) > +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (0xbd3b2d5UL) > +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (0x7cd48243UL) > +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (0xb0217badUL) > +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (0xc7264b3bUL) > +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (0x5e2f1a81UL) > +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (0x29282a17UL) > +#define MAC_PCS_GTY_STAT (0x853a9f14UL) > +#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (0x71cda8d6UL) > +#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (0x6ca9840UL) > +#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (0x9fc3c9faUL) > +#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (0xe8c4f96cUL) > +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (0xf766f49eUL) > +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (0x8061c408UL) > +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (0x196895b2UL) > +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (0x6e6fa524UL) > +#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (0xd128770bUL) > +#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (0xa62f479dUL) > +#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (0x3f261627UL) > +#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (0x482126b1UL) > +#define MAC_PCS_LANE_ALIGNER_FILL (0x7f7c92b4UL) > +#define MAC_PCS_LANE_ALIGNER_FILL_FILL (0x5d03a992UL) > +#define MAC_PCS_LINK_SUMMARY (0x7506c2cfUL) > +#define MAC_PCS_LINK_SUMMARY_ABS (0xeaec5364UL) > +#define MAC_PCS_LINK_SUMMARY_LH_ABS (0x75386439UL) > +#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (0xfe0a1d22UL) > +#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (0xe891aedUL) > +#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (0x91098b1fUL) > +#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (0x66c65523UL) > +#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (0x87148e11UL) > +#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (0x3d95c18UL) > +#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (0x27ce6435UL) > +#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (0xb1206568UL) > +#define MAC_PCS_LINK_SUMMARY_RESERVED (0x254bc0e3UL) > +#define MAC_PCS_MAC_PCS_CONFIG (0x1534e5c0UL) > +#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (0xe964d0f5UL) > +#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (0x3301c934UL) > +#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (0xf01103aUL) > +#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (0x65a6baccUL) > +#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (0xf932af1bUL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (0x1d11ab6UL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (0x401bb0beUL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (0x25816398UL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (0x8d13708fUL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (0xbcff1ba5UL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (0xc4dd154eUL) > +#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (0xdbc87be9UL) > +#define MAC_PCS_MAX_PKT_LEN (0x396b0d64UL) > +#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (0x6d95b01fUL) > +#define MAC_PCS_MF_ERR (0xb0be669dUL) > +#define MAC_PCS_MF_ERR_MF_ERR (0x6c7b7561UL) > +#define MAC_PCS_MF_LEN_ERR (0x559f33efUL) > +#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (0x196e21f6UL) > +#define MAC_PCS_MF_REPEAT_ERR (0xc7dedbb3UL) > +#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (0xb5be34c7UL) > +#define MAC_PCS_PHYMAC_MISC (0x4d213de4UL) > +#define MAC_PCS_PHYMAC_MISC_TS_EOP (0xc9232087UL) > +#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (0x761f1c74UL) > +#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (0xb50087a5UL) > +#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (0xbe5ce3b1UL) > +#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (0x106d1efUL) > +#define MAC_PCS_PHY_STAT (0x533a519cUL) > +#define MAC_PCS_PHY_STAT_ALARM (0x57360efaUL) > +#define MAC_PCS_PHY_STAT_MOD_PRS (0x5d9d2135UL) > +#define MAC_PCS_PHY_STAT_RX_LOS (0xf9354fecUL) > +#define MAC_PCS_STAT_PCS_RX (0xb11d1a0cUL) > +#define MAC_PCS_STAT_PCS_RX_ALIGNED (0xc04d3946UL) > +#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (0x82e5aacbUL) > +#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (0xe2ebace5UL) > +#define MAC_PCS_STAT_PCS_RX_HI_BER (0x44ed301UL) > +#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (0xd302122UL) > +#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (0x2fd7a554UL) > +#define MAC_PCS_STAT_PCS_RX_MISALIGNED (0x4f8958c8UL) > +#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (0xce46c6b2UL) > +#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (0xb73e135cUL) > +#define MAC_PCS_STAT_PCS_RX_STATUS (0x6087afc3UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH (0x12a96a4UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (0xffeb7af8UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (0x43af96a9UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (0x9a4f180dUL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (0x170bb0a7UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT > (0x97082914UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (0xee9d9936UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (0x64a891f6UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT > (0x547ece84UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (0x14435914UL) > +#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (0x73c2cc65UL) > +#define MAC_PCS_STAT_PCS_TX (0xe747bd8aUL) > +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (0xd715eee2UL) > +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (0x125aedaaUL) > +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (0x892ad851UL) > +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED > (0xf39f6854UL) > +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (0x6075c4dfUL) > +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED > (0xcd4c168aUL) > +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (0x4483a41fUL) > +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (0xcbd66e98UL) > +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (0xb65e59a1UL) > +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (0x9157fdd8UL) > +#define MAC_PCS_SYNCED (0x76ad78aaUL) > +#define MAC_PCS_SYNCED_SYNC (0xbff0beadUL) > +#define MAC_PCS_SYNCED_ERR (0x136856e9UL) > +#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (0x16c52dc7UL) > +#define MAC_PCS_TEST_ERR (0xbf52be89UL) > +#define MAC_PCS_TEST_ERR_CODE_ERR (0x33a662cUL) > +#define MAC_PCS_TIMESTAMP_COMP (0x3054d1fcUL) > +#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (0xa6496d75UL) > +#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (0x70108e68UL) > +#define MAC_PCS_VL_DEMUXED (0xe1a41659UL) > +#define MAC_PCS_VL_DEMUXED_LOCK (0xf1e85d36UL) > +#define MAC_PCS_VL_DEMUXED_CHG (0xa326d6a6UL) > +#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (0x9327587fUL) > +#define MAC_PCS_VL_NUMBER (0x149d9e3UL) > +#define MAC_PCS_VL_NUMBER_VL_NUMBER (0x3b87c706UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_PCS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > new file mode 100644 > index 0000000000..92878fb01f > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > @@ -0,0 +1,1092 @@ > +/* > + * nthw_fpga_reg_defs_mac_pcs_xxv.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_ > +#define _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_ > + > +/* MAC_PCS_XXV */ > +#define NTHW_MOD_MAC_PCS_XXV (0x3ea7bfeaUL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0 (0xe8535535UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ASMDIR (0xc90a5f78UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_BYPASS (0x66bcb293UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ENABLE (0x7a14fcd5UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_PAUSE (0xb0859554UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_RESTART (0xe270c120UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1 (0x9f5465a3UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ASMDIR (0x5a05fe6UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_BYPASS (0xaa16b20dUL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ENABLE (0xb6befc4bUL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_PAUSE (0x16f29ee0UL) > +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_RESTART (0xf50bd563UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0 (0x577adc44UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0_COMPLETE (0xc61358ebUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ANEG_ABLE (0x61fcc32aUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ASM (0x9aa1191UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_PAUSE (0x61b6e89aUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_RF (0x1f056f1eUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1 (0x207decd2UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1_COMPLETE (0x29d133d5UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ANEG_ABLE (0xfcf3225cUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ASM (0xc500110fUL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_PAUSE (0x8e7483a4UL) > +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_RF (0xb97264aaUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0 (0xd2af0b3bUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR (0xe523e7bcUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR1 (0x41ee33f7UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR_S (0xf8862066UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR (0xb2bec4abUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR1 (0xc26a2b13UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR_S (0x5f62821fUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1 (0xa5a83badUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR (0x291b88c4UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR1 (0x1ffcf296UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR_S (0xc26d6369UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR (0x412a26e0UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR1 (0x239727e9UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR_S (0x2eb6411UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2 (0x3ca16a17UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR (0x5e855a34UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR1 (0xa2369e58UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR_S (0xbe0c46b2UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR (0x36b4f410UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR1 (0x9e5d4b27UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR_S (0x7e8a41caUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3 (0x4ba65a81UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR (0xc520165bUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR1 (0x7fa047ddUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR_S (0x2303a7c4UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR (0xad11b87fUL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR1 (0x43cb92a2UL) > +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR_S (0xe385a0bcUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0 (0x4c943ef2UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_ASMDIR (0x3bbfbb7dUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_BYPASS (0x94095696UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_ENABLE (0x88a118d0UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST (0x76aa937UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST_10G > (0x1a5e1df6UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_ABILITY (0x5d6cbd68UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_REQUEST (0x5334dccbUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_HIDE_FEC74 (0xf0c50196UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_NONCE_SEED (0x8f9feb1eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_PAUSE (0x6761de07UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_PSEUDO (0xfdcd997fUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_REMOTE_FAULT (0xa56faacbUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_RESTART (0x92e8804bUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_RS_FEC_REQUEST > (0x5bcb427dUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_FEC_OVERWRITE > (0x28a23fa1UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_SPEED_OVERWRITE > (0x864c3454UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1 (0x3b930e64UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_ASMDIR (0xf715bbe3UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_BYPASS (0x58a35608UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_ENABLE (0x440b184eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST (0xbe9172dfUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST_10G > (0xcdbc9daeUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_ABILITY (0xe4976680UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_REQUEST (0xeacf0723UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_HIDE_FEC74 (0x6b604df9UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_NONCE_SEED (0x143aa771UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_PAUSE (0xc116d5b3UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_PSEUDO (0x316799e1UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_REMOTE_FAULT (0x38604bbdUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_RESTART (0x85939408UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_RS_FEC_REQUEST > (0xf5a3d3ecUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_FEC_OVERWRITE > (0xc7f08940UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_SPEED_OVERWRITE > (0xe32b0f12UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2 (0xa29a5fdeUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_ASMDIR (0x799abc00UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_BYPASS (0xd62c51ebUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_ENABLE (0xca841fadUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST (0xafec18a6UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST_10G > (0x6eea1b07UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_ABILITY (0xf5ea0cf9UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_REQUEST (0xfbb26d5aUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_HIDE_FEC74 (0x1cfe9f09UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_NONCE_SEED (0x63a47581UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_PAUSE (0xf0fecf2eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_PSEUDO (0xbfe89e02UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_REMOTE_FAULT (0x44016e66UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_RESTART (0xbc1ea8cdUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_RS_FEC_REQUEST > (0xdc6b671eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_FEC_OVERWRITE > (0x2d765422UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_SPEED_OVERWRITE > (0x4c8242d8UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3 (0xd59d6f48UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_ASMDIR (0xb530bc9eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_BYPASS (0x1a865175UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_ENABLE (0x62e1f33UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST > (0x1617c34eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST_10G > (0xb9089b5fUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_ABILITY (0x4c11d711UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_REQUEST > (0x4249b6b2UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_HIDE_FEC74 (0x875bd366UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_NONCE_SEED (0xf80139eeUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_PAUSE (0x5689c49aUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_PSEUDO (0x73429e9cUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_REMOTE_FAULT (0xd90e8f10UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_RESTART (0xab65bc8eUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_RS_FEC_REQUEST > (0x7203f68fUL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_FEC_OVERWRITE > (0xc224e2c3UL) > +#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_SPEED_OVERWRITE > (0x29e5799eUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0 (0x44ac1d35UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_END (0x85d17994UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_STARTED (0xd51a0134UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0_CDR_HOLD (0xdfa847b5UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_END (0xa921af33UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_STARTED (0xaac6e454UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1 (0x33ab2da3UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_END (0x6a1312aaUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_STARTED (0x4815e042UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1_CDR_HOLD (0x306a2c8bUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_END (0x658bafadUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_STARTED (0x3163a83bUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2 (0xaaa27c19UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_END (0x8124a9a9UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_STARTED (0x3474c599UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2_CDR_HOLD (0xdb5d9788UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_END (0xeb04a84eUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_STARTED (0x46fd7acbUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3 (0xdda54c8fUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_END (0x6ee6c297UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_STARTED (0xa97b24efUL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3_CDR_HOLD (0x349ffcb6UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_END (0x27aea8d0UL) > +#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_STARTED (0xdd5836a4UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_0 (0x9cd3a7adUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR (0x833d2c0eUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR1 (0x64e7ff9cUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR_S (0x22c3917aUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_1 (0xebd4973bUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR (0x9446384dUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR1 (0x8b2594a2UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR_S (0xe34d4ebaUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_2 (0x72ddc681UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR (0xadcb0488UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR1 (0x60122fa1UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR_S (0x7aaf28bbUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_3 (0x5daf617UL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR (0xbab010cbUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR1 (0x8fd0449fUL) > +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR_S (0xbb21f77bUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0 (0x679ed455UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR > (0xc77ef9eaUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR_S > (0xee68c58aUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1 (0x1099e4c3UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR > (0x7e852202UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR_S > (0x69ce0ec9UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2 (0x8990b579UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR > (0x6ff8487bUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR_S > (0x3a54554dUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3 (0xfe9785efUL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR > (0xd6039393UL) > +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR_S > (0xbdf29e0eUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0 (0x29fb18a1UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_ABILITY > (0x15810dbeUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_REQUEST > (0x1bd96c1dUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_ABILITY > (0x41df7842UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_REQUEST > (0x4f8719e1UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_25GBASE_CR1 > (0x23d251c1UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_EX_ABILITY_VALID > (0xc632a6a7UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1 (0x5efc2837UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_ABILITY > (0x9227c6fdUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_REQUEST > (0x9c7fa75eUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_ABILITY > (0xc679b301UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_REQUEST > (0xc821d2a2UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_25GBASE_CR1 > (0x8dbac050UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_EX_ABILITY_VALID > (0x59e82539UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2 (0xc7f5798dUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_ABILITY > (0xc1bd9d79UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_REQUEST > (0xcfe5fcdaUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_ABILITY > (0x95e3e885UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_REQUEST > (0x9bbb8926UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_25GBASE_CR1 > (0xa47274a2UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_EX_ABILITY_VALID > (0x22f6a7daUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3 (0xb0f2491bUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_ABILITY > (0x461b563aUL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_REQUEST > (0x48433799UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_ABILITY > (0x124523c6UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_REQUEST > (0x1c1d4265UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_25GBASE_CR1 > (0xa1ae533UL) > +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_EX_ABILITY_VALID > (0xbd2c2444UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0 (0xc256fa45UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ABILITY_VALID (0x414cfb0cUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ANEG_ABLE (0xe0623a0aUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ASM (0xf0872f9dUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_FEC74_REQ (0x3881d9daUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_PAUSE (0xc624310UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RF (0x8be40c82UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RS_FEC_REQ (0x9807cff4UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1 (0xb551cad3UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ABILITY_VALID > (0xae1e4dedUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ANEG_ABLE (0x7d6ddb7cUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ASM (0x3c2d2f03UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_FEC74_REQ (0xa58e38acUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_PAUSE (0xe3a0282eUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RF (0x2d930736UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RS_FEC_REQ (0x21fc141cUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2 (0x2c589b69UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ABILITY_VALID > (0x4498908fUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ANEG_ABLE (0x10cfea7UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ASM (0xb2a228e0UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_FEC74_REQ (0xd9ef1d77UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_PAUSE (0x897932dUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RF (0x1c7b1dabUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RS_FEC_REQ (0x30817e65UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3 (0x5b5fabffUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ABILITY_VALID > (0xabca266eUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ANEG_ABLE (0x9c031fd1UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ASM (0x7e08287eUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_FEC74_REQ (0x44e0fc01UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_PAUSE (0xe755f813UL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RF (0xba0c161fUL) > +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RS_FEC_REQ (0x897aa58dUL) > +#define MAC_PCS_XXV_ANEG_STA_0 (0x3ed7a2b9UL) > +#define MAC_PCS_XXV_ANEG_STA_0_COMPLETE (0x11f713b8UL) > +#define MAC_PCS_XXV_ANEG_STA_0_FEC74_EN (0x974edcf2UL) > +#define MAC_PCS_XXV_ANEG_STA_0_PAR_D_FAULT (0xabe31863UL) > +#define MAC_PCS_XXV_ANEG_STA_0_RS_FEC_EN (0x178283ccUL) > +#define MAC_PCS_XXV_ANEG_STA_0_RX_PAUSE_EN (0xf5adbafaUL) > +#define MAC_PCS_XXV_ANEG_STA_0_TX_PAUSE_EN (0x1d1870b9UL) > +#define MAC_PCS_XXV_ANEG_STA_1 (0x49d0922fUL) > +#define MAC_PCS_XXV_ANEG_STA_1_COMPLETE (0xfe357886UL) > +#define MAC_PCS_XXV_ANEG_STA_1_FEC74_EN (0x788cb7ccUL) > +#define MAC_PCS_XXV_ANEG_STA_1_PAR_D_FAULT (0x7675c1e6UL) > +#define MAC_PCS_XXV_ANEG_STA_1_RS_FEC_EN (0xd60c5c0cUL) > +#define MAC_PCS_XXV_ANEG_STA_1_RX_PAUSE_EN (0x283b637fUL) > +#define MAC_PCS_XXV_ANEG_STA_1_TX_PAUSE_EN (0xc08ea93cUL) > +#define MAC_PCS_XXV_ANEG_STA_2 (0xd0d9c395UL) > +#define MAC_PCS_XXV_ANEG_STA_2_COMPLETE (0x1502c385UL) > +#define MAC_PCS_XXV_ANEG_STA_2_FEC74_EN (0x93bb0ccfUL) > +#define MAC_PCS_XXV_ANEG_STA_2_PAR_D_FAULT (0xcbbfad28UL) > +#define MAC_PCS_XXV_ANEG_STA_2_RS_FEC_EN (0x4fee3a0dUL) > +#define MAC_PCS_XXV_ANEG_STA_2_RX_PAUSE_EN (0x95f10fb1UL) > +#define MAC_PCS_XXV_ANEG_STA_2_TX_PAUSE_EN (0x7d44c5f2UL) > +#define MAC_PCS_XXV_ANEG_STA_3 (0xa7def303UL) > +#define MAC_PCS_XXV_ANEG_STA_3_COMPLETE (0xfac0a8bbUL) > +#define MAC_PCS_XXV_ANEG_STA_3_FEC74_EN (0x7c7967f1UL) > +#define MAC_PCS_XXV_ANEG_STA_3_PAR_D_FAULT (0x162974adUL) > +#define MAC_PCS_XXV_ANEG_STA_3_RS_FEC_EN (0x8e60e5cdUL) > +#define MAC_PCS_XXV_ANEG_STA_3_RX_PAUSE_EN (0x4867d634UL) > +#define MAC_PCS_XXV_ANEG_STA_3_TX_PAUSE_EN (0xa0d21c77UL) > +#define MAC_PCS_XXV_CLK_REF_ACTIVITY (0xad9a1b80UL) > +#define MAC_PCS_XXV_CLK_REF_ACTIVITY_COUNT (0x3216c992UL) > +#define MAC_PCS_XXV_CORE_CONF_0 (0xc665a258UL) > +#define MAC_PCS_XXV_CORE_CONF_0_ENHANCED_TS (0x10792af0UL) > +#define MAC_PCS_XXV_CORE_CONF_0_INLINE_MODE (0xb75bd54aUL) > +#define MAC_PCS_XXV_CORE_CONF_0_LINE_LOOPBACK (0xe27b24f2UL) > +#define MAC_PCS_XXV_CORE_CONF_0_RX_ENABLE (0x58298567UL) > +#define MAC_PCS_XXV_CORE_CONF_0_RX_FORCE_RESYNC > (0x391c7c3bUL) > +#define MAC_PCS_XXV_CORE_CONF_0_TS_AT_EOP (0x34e1ac8fUL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_ENABLE (0x2b33fcedUL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_IGN_FCS (0x65b14385UL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_INS_FCS (0xdace417eUL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_IDLE (0xbb7c23d4UL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_LFI (0x3c99f330UL) > +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_RFI (0x2a217d4aUL) > +#define MAC_PCS_XXV_CORE_CONF_1 (0xb16292ceUL) > +#define MAC_PCS_XXV_CORE_CONF_1_ENHANCED_TS (0xcdeff375UL) > +#define MAC_PCS_XXV_CORE_CONF_1_INLINE_MODE (0x6acd0ccfUL) > +#define MAC_PCS_XXV_CORE_CONF_1_LINE_LOOPBACK (0x5b80ff1aUL) > +#define MAC_PCS_XXV_CORE_CONF_1_RX_ENABLE (0x99a75aa7UL) > +#define MAC_PCS_XXV_CORE_CONF_1_RX_FORCE_RESYNC > (0xbebab778UL) > +#define MAC_PCS_XXV_CORE_CONF_1_TS_AT_EOP (0xf56f734fUL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_ENABLE (0xeabd232dUL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_IGN_FCS (0xfe140feaUL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_INS_FCS (0x416b0d11UL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_IDLE (0x2673c2a2UL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_LFI (0xe10f2ab5UL) > +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_RFI (0xf7b7a4cfUL) > +#define MAC_PCS_XXV_CORE_CONF_2 (0x286bc374UL) > +#define MAC_PCS_XXV_CORE_CONF_2_ENHANCED_TS (0x70259fbbUL) > +#define MAC_PCS_XXV_CORE_CONF_2_INLINE_MODE (0xd7076001UL) > +#define MAC_PCS_XXV_CORE_CONF_2_LINE_LOOPBACK (0x4afd9563UL) > +#define MAC_PCS_XXV_CORE_CONF_2_RX_ENABLE (0x453ca6UL) > +#define MAC_PCS_XXV_CORE_CONF_2_RX_FORCE_RESYNC (0xed20ecfcUL) > +#define MAC_PCS_XXV_CORE_CONF_2_TS_AT_EOP (0x6c8d154eUL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_ENABLE (0x735f452cUL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_IGN_FCS (0x898add1aUL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_INS_FCS (0x36f5dfe1UL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_IDLE (0x5a12e779UL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_LFI (0x5cc5467bUL) > +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_RFI (0x4a7dc801UL) > +#define MAC_PCS_XXV_CORE_CONF_3 (0x5f6cf3e2UL) > +#define MAC_PCS_XXV_CORE_CONF_3_ENHANCED_TS (0xadb3463eUL) > +#define MAC_PCS_XXV_CORE_CONF_3_INLINE_MODE (0xa91b984UL) > +#define MAC_PCS_XXV_CORE_CONF_3_LINE_LOOPBACK (0xf3064e8bUL) > +#define MAC_PCS_XXV_CORE_CONF_3_RX_ENABLE (0xc1cbe366UL) > +#define MAC_PCS_XXV_CORE_CONF_3_RX_FORCE_RESYNC > (0x6a8627bfUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TS_AT_EOP (0xad03ca8eUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_ENABLE (0xb2d19aecUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_IGN_FCS (0x122f9175UL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_INS_FCS (0xad50938eUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_IDLE (0xc71d060fUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_LFI (0x81539ffeUL) > +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_RFI (0x97eb1184UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0 (0xcd1b26beUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_DEBOUNCE_LATENCY > (0x32bcbfc6UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_FORCE_LINK_DOWN > (0xf5caa84cUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_LINKUP_LATENCY > (0x39c69ab7UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_PORT_CTRL > (0xbba352c4UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1 (0xba1c1628UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_DEBOUNCE_LATENCY > (0xad663c58UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_FORCE_LINK_DOWN > (0x90ad930aUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_LINKUP_LATENCY > (0xee241aefUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_PORT_CTRL > (0x26acb3b2UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2 (0x23154792UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_DEBOUNCE_LATENCY > (0xd678bebbUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_FORCE_LINK_DOWN > (0x3f04dec0UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_LINKUP_LATENCY > (0x4d729c46UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_PORT_CTRL > (0x5acd9669UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3 (0x54127704UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_DEBOUNCE_LATENCY > (0x49a23d25UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_FORCE_LINK_DOWN > (0x5a63e586UL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_LINKUP_LATENCY > (0x9a901c1eUL) > +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_PORT_CTRL > (0xc7c2771fUL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_0 (0x98d5cef3UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_0_FEC74_CCW_CNT > (0x98570079UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_1 (0xefd2fe65UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_1_FEC74_CCW_CNT > (0x21acdb91UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_2 (0x76dbafdfUL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_2_FEC74_CCW_CNT > (0x30d1b1e8UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_3 (0x1dc9f49UL) > +#define MAC_PCS_XXV_FEC74_CCW_CNT_3_FEC74_CCW_CNT > (0x892a6a00UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_0 (0xd8988d69UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_0_FEC74_ERRORS_TO_PCS > (0xbad20553UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_0_RX_FEC74_ENABLE > (0x95657559UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_0_TX_FEC74_ENABLE > (0xb79fa1abUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_1 (0xaf9fbdffUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_1_FEC74_ERRORS_TO_PCS > (0x250886cdUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_1_RX_FEC74_ENABLE > (0x12c3be1aUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_1_TX_FEC74_ENABLE > (0x30396ae8UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_2 (0x3696ec45UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_2_FEC74_ERRORS_TO_PCS > (0x5e16042eUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_2_RX_FEC74_ENABLE > (0x4159e59eUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_2_TX_FEC74_ENABLE > (0x63a3316cUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_3 (0x4191dcd3UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_3_FEC74_ERRORS_TO_PCS > (0xc1cc87b0UL) > +#define MAC_PCS_XXV_FEC74_CONFIG_3_RX_FEC74_ENABLE > (0xc6ff2eddUL) > +#define MAC_PCS_XXV_FEC74_CONFIG_3_TX_FEC74_ENABLE > (0xe405fa2fUL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_0 (0x470ff508UL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_0_FEC74_UCW_CNT > (0x70e15dbbUL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_1 (0x3008c59eUL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_1_FEC74_UCW_CNT > (0xc91a8653UL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_2 (0xa9019424UL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_2_FEC74_UCW_CNT > (0xd867ec2aUL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_3 (0xde06a4b2UL) > +#define MAC_PCS_XXV_FEC74_UCW_CNT_3_FEC74_UCW_CNT > (0x619c37c2UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0 (0xb45ac330UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0_CDR_HOLD (0x9494702eUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0_EQUA_RST (0xac159264UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0_LPM_EN (0x8f3f6136UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0_POLARITY (0x589f67ddUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_0_RATE (0x54b5525dUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1 (0xc35df3a6UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1_CDR_HOLD (0x7b561b10UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1_EQUA_RST (0x43d7f95aUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1_LPM_EN (0x439561a8UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1_POLARITY (0xb75d0ce3UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_1_RATE (0x9fe981f8UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2 (0x5a54a21cUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2_CDR_HOLD (0x9061a013UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2_EQUA_RST (0xa8e04259UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2_LPM_EN (0xcd1a664bUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2_POLARITY (0x5c6ab7e0UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_2_RATE (0x197df356UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3 (0x2d53928aUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3_CDR_HOLD (0x7fa3cb2dUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3_EQUA_RST (0x47222967UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3_LPM_EN (0x1b066d5UL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3_POLARITY (0xb3a8dcdeUL) > +#define MAC_PCS_XXV_GTY_CTL_RX_3_RATE (0xd22120f3UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_0 (0x91319cecUL) > +#define MAC_PCS_XXV_GTY_CTL_TX_0_INHIBIT (0x2743e45UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_0_POLARITY (0xf87ab800UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_1 (0xe636ac7aUL) > +#define MAC_PCS_XXV_GTY_CTL_TX_1_INHIBIT (0x150f2a06UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_1_POLARITY (0x17b8d33eUL) > +#define MAC_PCS_XXV_GTY_CTL_TX_2 (0x7f3ffdc0UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_2_INHIBIT (0x2c8216c3UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_2_POLARITY (0xfc8f683dUL) > +#define MAC_PCS_XXV_GTY_CTL_TX_3 (0x838cd56UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_3_INHIBIT (0x3bf90280UL) > +#define MAC_PCS_XXV_GTY_CTL_TX_3_POLARITY (0x134d0303UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_0 (0x7a99aa99UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL (0xcdf499beUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL_ADJUSTED > (0x833ddf3dUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_1 (0xd9e9a0fUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL (0x1062403bUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL_ADJUSTED > (0x9415bbfdUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_2 (0x9497cbb5UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL (0xada82cf5UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL_ADJUSTED > (0xad6d16bdUL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_3 (0xe390fb23UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL (0x703ef570UL) > +#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL_ADJUSTED > (0xba45727dUL) > +#define MAC_PCS_XXV_GTY_LOOP_0 (0xcfacffb3UL) > +#define MAC_PCS_XXV_GTY_LOOP_0_GT_LOOP (0x5c74ecacUL) > +#define MAC_PCS_XXV_GTY_LOOP_1 (0xb8abcf25UL) > +#define MAC_PCS_XXV_GTY_LOOP_1_GT_LOOP (0x4b0ff8efUL) > +#define MAC_PCS_XXV_GTY_LOOP_2 (0x21a29e9fUL) > +#define MAC_PCS_XXV_GTY_LOOP_2_GT_LOOP (0x7282c42aUL) > +#define MAC_PCS_XXV_GTY_LOOP_3 (0x56a5ae09UL) > +#define MAC_PCS_XXV_GTY_LOOP_3_GT_LOOP (0x65f9d069UL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_0 (0xd79b7f80UL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_0_TX_MAIN_CTL (0xded513f4UL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_1 (0xa09c4f16UL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_1_TX_MAIN_CTL (0x343ca71UL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_2 (0x39951eacUL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_2_TX_MAIN_CTL (0xbe89a6bfUL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_3 (0x4e922e3aUL) > +#define MAC_PCS_XXV_GTY_MAIN_CTL_3_TX_MAIN_CTL (0x631f7f3aUL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_0 (0xaa04cb19UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR > (0x7b6f0b43UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR_ADJUSTED > (0xa87d9ad2UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_1 (0xdd03fb8fUL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR > (0xa6f9d2c6UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR_ADJUSTED > (0xbf55fe12UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_2 (0x440aaa35UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR > (0x1b33be08UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR_ADJUSTED > (0x862d5352UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_3 (0x330d9aa3UL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR > (0xc6a5678dUL) > +#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR_ADJUSTED > (0x91053792UL) > +#define MAC_PCS_XXV_GTY_PRBS_0 (0xd3e408e4UL) > +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR (0x4fd820bdUL) > +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR_INS (0x292ed7d3UL) > +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_RST (0xa6c9013cUL) > +#define MAC_PCS_XXV_GTY_PRBS_0_RX_PRBS_SEL (0x9c43c790UL) > +#define MAC_PCS_XXV_GTY_PRBS_0_TX_PRBS_SEL (0x74f60dd3UL) > +#define MAC_PCS_XXV_GTY_PRBS_1 (0xa4e33872UL) > +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR (0xa01a4b83UL) > +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR_INS (0xb42136a5UL) > +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_RST (0x490b6a02UL) > +#define MAC_PCS_XXV_GTY_PRBS_1_RX_PRBS_SEL (0x41d51e15UL) > +#define MAC_PCS_XXV_GTY_PRBS_1_TX_PRBS_SEL (0xa960d456UL) > +#define MAC_PCS_XXV_GTY_PRBS_2 (0x3dea69c8UL) > +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR (0x4b2df080UL) > +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR_INS (0xc840137eUL) > +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_RST (0xa23cd101UL) > +#define MAC_PCS_XXV_GTY_PRBS_2_RX_PRBS_SEL (0xfc1f72dbUL) > +#define MAC_PCS_XXV_GTY_PRBS_2_TX_PRBS_SEL (0x14aab898UL) > +#define MAC_PCS_XXV_GTY_PRBS_3 (0x4aed595eUL) > +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR (0xa4ef9bbeUL) > +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR_INS (0x554ff208UL) > +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_RST (0x4dfeba3fUL) > +#define MAC_PCS_XXV_GTY_PRBS_3_RX_PRBS_SEL (0x2189ab5eUL) > +#define MAC_PCS_XXV_GTY_PRBS_3_TX_PRBS_SEL (0xc93c611dUL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_0 (0xe674af07UL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_0_COUNT (0x9e8b170cUL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_1 (0x91739f91UL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_1_COUNT (0x38fc1cb8UL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_2 (0x87ace2bUL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_2_COUNT (0x9140625UL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_3 (0x7f7dfebdUL) > +#define MAC_PCS_XXV_GTY_PRBS_CNT_3_COUNT (0xaf630d91UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0 (0xa5879edeUL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR (0x2f0d4bd2UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR_ADJUSTED > (0xd738196fUL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1 (0xd280ae48UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR (0xb4a807bdUL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR_ADJUSTED > (0x48e29af1UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2 (0x4b89fff2UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR (0xc336d54dUL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR_ADJUSTED > (0x33fc1812UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3 (0x3c8ecf64UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR (0x58939922UL) > +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR_ADJUSTED > (0xac269b8cUL) > +#define MAC_PCS_XXV_GTY_STATUS_0 (0x922d078cUL) > +#define MAC_PCS_XXV_GTY_STATUS_0_GT_POWERGOOD (0x46fffefcUL) > +#define MAC_PCS_XXV_GTY_STATUS_0_GT_RXBUFSTATUS (0x71961330UL) > +#define MAC_PCS_XXV_GTY_STATUS_0_GT_STARTOFSEQ (0x302abe66UL) > +#define MAC_PCS_XXV_GTY_STATUS_0_GT_TXBUFSTATUS (0x9923d973UL) > +#define MAC_PCS_XXV_GTY_STATUS_1 (0xe52a371aUL) > +#define MAC_PCS_XXV_GTY_STATUS_1_GT_POWERGOOD (0xdbf01f8aUL) > +#define MAC_PCS_XXV_GTY_STATUS_1_GT_RXBUFSTATUS (0xdffe82a1UL) > +#define MAC_PCS_XXV_GTY_STATUS_1_GT_STARTOFSEQ (0x89d1658eUL) > +#define MAC_PCS_XXV_GTY_STATUS_1_GT_TXBUFSTATUS (0x374b48e2UL) > +#define MAC_PCS_XXV_GTY_STATUS_2 (0x7c2366a0UL) > +#define MAC_PCS_XXV_GTY_STATUS_2_GT_POWERGOOD (0xa7913a51UL) > +#define MAC_PCS_XXV_GTY_STATUS_2_GT_RXBUFSTATUS (0xf6363653UL) > +#define MAC_PCS_XXV_GTY_STATUS_2_GT_STARTOFSEQ (0x98ac0ff7UL) > +#define MAC_PCS_XXV_GTY_STATUS_2_GT_TXBUFSTATUS (0x1e83fc10UL) > +#define MAC_PCS_XXV_GTY_STATUS_3 (0xb245636UL) > +#define MAC_PCS_XXV_GTY_STATUS_3_GT_POWERGOOD (0x3a9edb27UL) > +#define MAC_PCS_XXV_GTY_STATUS_3_GT_RXBUFSTATUS (0x585ea7c2UL) > +#define MAC_PCS_XXV_GTY_STATUS_3_GT_STARTOFSEQ (0x2157d41fUL) > +#define MAC_PCS_XXV_GTY_STATUS_3_GT_TXBUFSTATUS (0xb0eb6d81UL) > +#define MAC_PCS_XXV_LATENCY_0 (0x1ebce893UL) > +#define MAC_PCS_XXV_LATENCY_0_RX_LATENCY_MEAS (0x16e7962UL) > +#define MAC_PCS_XXV_LATENCY_1 (0x69bbd805UL) > +#define MAC_PCS_XXV_LATENCY_1_RX_LATENCY_MEAS (0x86c8b221UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0 (0x64b5dd89UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_MAIN > (0x3a6efcd0UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_POST > (0xdfcc5d39UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_PRE > (0xa8605393UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_MAIN > (0xa36cbdfbUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_POST > (0x46ce1c12UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_PRE (0xa370c290UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INIT (0xc3ba915bUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_PRESET (0xb0c65848UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1 (0x13b2ed1fUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_MAIN > (0xd5ac97eeUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_POST > (0x300e3607UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_PRE > (0xbf1b47d0UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_MAIN > (0x4caed6c5UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_POST > (0xa90c772cUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_PRE > (0xb40bd6d3UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INIT (0x8e642feUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_PRESET (0x7c6c58d6UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2 (0x8abbbca5UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_MAIN > (0x3e9b2cedUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_POST > (0xdb398d04UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_PRE > (0x86967b15UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_MAIN > (0xa7996dc6UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_POST > (0x423bcc2fUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_PRE (0x8d86ea16UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INIT (0x8e723050UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_PRESET (0xf2e35f35UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3 (0xfdbc8c33UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_MAIN > (0xd15947d3UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_POST > (0x34fbe63aUL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_PRE (0x91ed6f56UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_MAIN > (0x485b06f8UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_POST > (0xadf9a711UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_PRE (0x9afdfe55UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INIT (0x452ee3f5UL) > +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_PRESET (0x3e495fabUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_0 (0xf103387fUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_MAIN_STA (0x87c6ab44UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_POST_STA (0xb85a5a3dUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_PRE_STA (0x44fa3d7eUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_1 (0x860408e9UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_MAIN_STA (0x6804c07aUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_POST_STA (0x57983103UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_PRE_STA (0x5381293dUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_2 (0x1f0d5953UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_MAIN_STA (0x83337b79UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_POST_STA (0xbcaf8a00UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_PRE_STA (0x6a0c15f8UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_3 (0x680a69c5UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_MAIN_STA (0x6cf11047UL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_POST_STA (0x536de13eUL) > +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_PRE_STA (0x7d7701bbUL) > +#define MAC_PCS_XXV_LINK_SPEED_0 (0xfcf10505UL) > +#define MAC_PCS_XXV_LINK_SPEED_0_10G (0xfb473664UL) > +#define MAC_PCS_XXV_LINK_SPEED_0_SPEED (0xa81deb0bUL) > +#define MAC_PCS_XXV_LINK_SPEED_0_TOGGLE (0xdd2f38f7UL) > +#define MAC_PCS_XXV_LINK_SPEED_1 (0x8bf63593UL) > +#define MAC_PCS_XXV_LINK_SPEED_1_10G (0xc6271fd4UL) > +#define MAC_PCS_XXV_LINK_SPEED_1_SPEED (0xe6ae0bfUL) > +#define MAC_PCS_XXV_LINK_SPEED_1_TOGGLE (0x11853869UL) > +#define MAC_PCS_XXV_LINK_SPEED_2 (0x12ff6429UL) > +#define MAC_PCS_XXV_LINK_SPEED_2_10G (0x81876504UL) > +#define MAC_PCS_XXV_LINK_SPEED_2_SPEED (0x3f82fa22UL) > +#define MAC_PCS_XXV_LINK_SPEED_2_TOGGLE (0x9f0a3f8aUL) > +#define MAC_PCS_XXV_LINK_SPEED_3 (0x65f854bfUL) > +#define MAC_PCS_XXV_LINK_SPEED_3_10G (0xbce74cb4UL) > +#define MAC_PCS_XXV_LINK_SPEED_3_SPEED (0x99f5f196UL) > +#define MAC_PCS_XXV_LINK_SPEED_3_TOGGLE (0x53a03f14UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0 (0xbdeefa9fUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_ABS (0x881db88UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_COMPLETE > (0x5fc67735UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_CONSORTIUM_MISMATCH > (0x61d4136fUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_INTERNAL_LOCAL_FAULT > (0x16fc1a7aUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_ABS (0x159942b9UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_INTERNAL_LOCAL_FAULT > (0x95aab8f5UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_LOCAL_FAULT > (0x4a2e2158UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT > (0x56dc5f65UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_REMOTE_FAULT > (0xbeeda6f3UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_FEC74_LOCK_ERROR > (0xcf25e9b5UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE > (0x8d8fa991UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_PCS_VALID_CTRL_CODE > (0x2846c322UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_RSFEC_HI_SER > (0xbb5aafe6UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_LOCAL_FAULT > (0x8f3e56b4UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_UNDERRUN > (0xb1c337c4UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LINK_DOWN_CNT > (0xbe8bc6e3UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_PHY_LINK_STATE > (0x7050253fUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK > (0x639554a2UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_FEC74_LOCK > (0x73211ce0UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_RSFEC_LANE_ALIGNMENT > (0xd0bd97c6UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_0_LL_TX_RSFEC_LANE_ALIGNMENT > (0x3d77e5bcUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_LT_DONE (0xd2620565UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_NIM_INTERR (0x28ee3c81UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_0_NT_PHY_LINK_STATE > (0x31581429UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1 (0xcae9ca09UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_ABS (0x35e1f238UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_COMPLETE > (0xe63dacddUL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_CONSORTIUM_MISMATCH > (0x86c9b5f8UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_INTERNAL_LOCAL_FAULT > (0x1d47ebaUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_ABS (0xd9334227UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_INTERNAL_LOCAL_FAULT > (0x302128fbUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_LOCAL_FAULT > (0xe446b0c9UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT > (0xf357cf6bUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_REMOTE_FAULT > (0x394b6db0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_FEC74_LOCK_ERROR > (0x4e008c92UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE > (0xe303b2d0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_PCS_VALID_CTRL_CODE > (0x46cad863UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_RSFEC_HI_SER > (0xde3d94a0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_LOCAL_FAULT > (0x58dcd6ecUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_UNDERRUN > (0x1faba655UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LINK_DOWN_CNT > (0x7701d0bUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_PHY_LINK_STATE > (0xa7b2a567UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK > (0x8cc7e243UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_FEC74_LOCK > (0x9c73aa01UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_RSFEC_LANE_ALIGNMENT > (0xd1086adbUL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_1_LL_TX_RSFEC_LANE_ALIGNMENT > (0x3cc218a1UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_LT_DONE (0xc5191126UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_NIM_INTERR (0xb34b70eeUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_1_NT_PHY_LINK_STATE > (0xe6ba9471UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2 (0x53e09bb3UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_ABS (0x724188e8UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_COMPLETE > (0xf740c6a4UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_CONSORTIUM_MISMATCH > (0x749e5800UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_INTERNAL_LOCAL_FAULT > (0x38acd3faUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_ABS (0x57bc45c4UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_INTERNAL_LOCAL_FAULT > (0x5cc9ea8UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_LOCAL_FAULT > (0xcd8e043bUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RECEIVED_LOCAL_FAULT > (0xc6ba7938UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_REMOTE_FAULT > (0x6ad13634UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_FEC74_LOCK_ERROR > (0x161e25baUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_HIGH_BIT_ERROR_RATE > (0x50979f13UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_PCS_VALID_CTRL_CODE > (0xf55ef5a0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_RSFEC_HI_SER > (0x7194d96aUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_LOCAL_FAULT > (0xfb8a5045UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_UNDERRUN > (0x366312a7UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LINK_DOWN_CNT > (0x160d7772UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_PHY_LINK_STATE > (0x4e423ceUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_BLOCK_LOCK > (0x66413f21UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_FEC74_LOCK > (0x76f57763UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_RSFEC_LANE_ALIGNMENT > (0xd3d66dfcUL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_2_LL_TX_RSFEC_LANE_ALIGNMENT > (0x3e1c1f86UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_LT_DONE (0xfc942de3UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_NIM_INTERR (0xc4d5a21eUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_2_NT_PHY_LINK_STATE > (0x45ec12d8UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3 (0x24e7ab25UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_ABS (0x4f21a158UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_COMPLETE > (0x4ebb1d4cUL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_CONSORTIUM_MISMATCH > (0x9383fe97UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_INTERNAL_LOCAL_FAULT > (0x2f84b73aUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_ABS (0x9b16455aUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_INTERNAL_LOCAL_FAULT > (0xa0470ea6UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_LOCAL_FAULT > (0x63e695aaUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RECEIVED_LOCAL_FAULT > (0x6331e936UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_REMOTE_FAULT > (0xed77fd77UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_FEC74_LOCK_ERROR > (0x973b409dUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_HIGH_BIT_ERROR_RATE > (0x3e1b8452UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_PCS_VALID_CTRL_CODE > (0x9bd2eee1UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_RSFEC_HI_SER > (0x14f3e22cUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_LOCAL_FAULT > (0x2c68d01dUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_UNDERRUN > (0x980b8336UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LINK_DOWN_CNT > (0xaff6ac9aUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_PHY_LINK_STATE > (0xd306a396UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_BLOCK_LOCK > (0x891389c0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_FEC74_LOCK > (0x99a7c182UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_RSFEC_LANE_ALIGNMENT > (0xd26390e1UL) > +#define > MAC_PCS_XXV_LINK_SUMMARY_3_LL_TX_RSFEC_LANE_ALIGNMENT > (0x3fa9e29bUL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_LT_DONE (0xebef39a0UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_NIM_INTERR (0x5f70ee71UL) > +#define MAC_PCS_XXV_LINK_SUMMARY_3_NT_PHY_LINK_STATE > (0x920e9280UL) > +#define MAC_PCS_XXV_LT_CONF_0 (0x26c9751bUL) > +#define MAC_PCS_XXV_LT_CONF_0_ENABLE (0xef1e1da6UL) > +#define MAC_PCS_XXV_LT_CONF_0_RESTART (0x2be9eb47UL) > +#define MAC_PCS_XXV_LT_CONF_0_SEED (0xfdf46f00UL) > +#define MAC_PCS_XXV_LT_CONF_1 (0x51ce458dUL) > +#define MAC_PCS_XXV_LT_CONF_1_ENABLE (0x23b41d38UL) > +#define MAC_PCS_XXV_LT_CONF_1_RESTART (0x3c92ff04UL) > +#define MAC_PCS_XXV_LT_CONF_1_SEED (0x36a8bca5UL) > +#define MAC_PCS_XXV_LT_CONF_2 (0xc8c71437UL) > +#define MAC_PCS_XXV_LT_CONF_2_ENABLE (0xad3b1adbUL) > +#define MAC_PCS_XXV_LT_CONF_2_RESTART (0x51fc3c1UL) > +#define MAC_PCS_XXV_LT_CONF_2_SEED (0xb03cce0bUL) > +#define MAC_PCS_XXV_LT_CONF_3 (0xbfc024a1UL) > +#define MAC_PCS_XXV_LT_CONF_3_ENABLE (0x61911a45UL) > +#define MAC_PCS_XXV_LT_CONF_3_RESTART (0x1264d782UL) > +#define MAC_PCS_XXV_LT_CONF_3_SEED (0x7b601daeUL) > +#define MAC_PCS_XXV_LT_STA_0 (0xb58612d6UL) > +#define MAC_PCS_XXV_LT_STA_0_DONE (0x3f809c59UL) > +#define MAC_PCS_XXV_LT_STA_0_FAIL (0xa98a57bbUL) > +#define MAC_PCS_XXV_LT_STA_0_LOCK (0xa822e7fcUL) > +#define MAC_PCS_XXV_LT_STA_0_TRAIN (0x3494fa27UL) > +#define MAC_PCS_XXV_LT_STA_1 (0xc2812240UL) > +#define MAC_PCS_XXV_LT_STA_1_DONE (0xf4dc4ffcUL) > +#define MAC_PCS_XXV_LT_STA_1_FAIL (0x62d6841eUL) > +#define MAC_PCS_XXV_LT_STA_1_LOCK (0x637e3459UL) > +#define MAC_PCS_XXV_LT_STA_1_TRAIN (0x92e3f193UL) > +#define MAC_PCS_XXV_LT_STA_2 (0x5b8873faUL) > +#define MAC_PCS_XXV_LT_STA_2_DONE (0x72483d52UL) > +#define MAC_PCS_XXV_LT_STA_2_FAIL (0xe442f6b0UL) > +#define MAC_PCS_XXV_LT_STA_2_LOCK (0xe5ea46f7UL) > +#define MAC_PCS_XXV_LT_STA_2_TRAIN (0xa30beb0eUL) > +#define MAC_PCS_XXV_LT_STA_3 (0x2c8f436cUL) > +#define MAC_PCS_XXV_LT_STA_3_DONE (0xb914eef7UL) > +#define MAC_PCS_XXV_LT_STA_3_FAIL (0x2f1e2515UL) > +#define MAC_PCS_XXV_LT_STA_3_LOCK (0x2eb69552UL) > +#define MAC_PCS_XXV_LT_STA_3_TRAIN (0x57ce0baUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_0 (0x397037c0UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_ATTRIB (0x38d464dcUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_NEXT (0x75b189c5UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_PREV (0xcd7c11acUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_1 (0x4e770756UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_ATTRIB (0xf47e6442UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_NEXT (0xbeed5a60UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_PREV (0x620c209UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_2 (0xd77e56ecUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_ATTRIB (0x7af163a1UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_NEXT (0x387928ceUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_PREV (0x80b4b0a7UL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_3 (0xa079667aUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_ATTRIB (0xb65b633fUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_NEXT (0xf325fb6bUL) > +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_PREV (0x4be86302UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0 (0xa935a75dUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_ATTRIB (0x86fe53feUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_NEXT (0xe6774ef1UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_PREV (0x5ebad698UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_SEL (0x155c6463UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_TABLE_ADDR > (0xa7ff653fUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_UPDATE > (0xc44806baUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1 (0xde3297cbUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_ATTRIB > (0x4a545360UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_NEXT (0x2d2b9d54UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_PREV (0x95e6053dUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_SEL (0x283c4dd3UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_TABLE_ADDR > (0x3c5a2950UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_UPDATE > (0x8e20624UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2 (0x473bc671UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_ATTRIB > (0xc4db5483UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_NEXT (0xabbfeffaUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_PREV (0x13727793UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_SEL (0x6f9c3703UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_TABLE_ADDR > (0x4bc4fba0UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_UPDATE > (0x866d01c7UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3 (0x303cf6e7UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_ATTRIB (0x871541dUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_NEXT (0x60e33c5fUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_PREV (0xd82ea436UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_SEL (0x52fc1eb3UL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_TABLE_ADDR > (0xd061b7cfUL) > +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_UPDATE > (0x4ac70159UL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0 (0xca36b2f7UL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0_RX_MAX_LENGTH > (0xad9bad5fUL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1 (0xbd318261UL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1_RX_MAX_LENGTH > (0x146076b7UL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2 (0x2438d3dbUL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2_RX_MAX_LENGTH > (0x51d1cceUL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3 (0x533fe34dUL) > +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3_RX_MAX_LENGTH > (0xbce6c726UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0 (0x5a45a21dUL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_MIN_RX_FRAME > (0x781d8621UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_RX_MIN_LENGTH > (0x4fca8931UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1 (0x2d42928bUL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_MIN_RX_FRAME > (0xe5126757UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_RX_MIN_LENGTH > (0xf63152d9UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2 (0xb44bc331UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_MIN_RX_FRAME > (0x9973428cUL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_RX_MIN_LENGTH > (0xe74c38a0UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3 (0xc34cf3a7UL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_MIN_RX_FRAME > (0x47ca3faUL) > +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_RX_MIN_LENGTH > (0x5eb7e348UL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_0 (0x5b190150UL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_0_MAX_LEN (0xeaa0f0bUL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_1 (0x2c1e31c6UL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_1_MAX_LEN (0x19d11b48UL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_2 (0xb517607cUL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_2_MAX_LEN (0x205c278dUL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_3 (0xc21050eaUL) > +#define MAC_PCS_XXV_MAX_PKT_LEN_3_MAX_LEN (0x372733ceUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0 (0xbee01144UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_MAIN (0x553fe7f6UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_POST (0xb09d461fUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_PRE (0x490c9445UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ENABLE (0x1dc34d8aUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_INIT (0xff042d41UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_PRESET (0xc23c618aUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_RX_READY (0x5f37a378UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1 (0xc9e721d2UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_MAIN (0xbafd8cc8UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_POST (0x5f5f2d21UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_PRE (0x5e778006UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ENABLE (0xd1694d14UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_INIT (0x3458fee4UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_PRESET (0xe966114UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_RX_READY (0xb0f5c846UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2 (0x50ee7068UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_MAIN (0x51ca37cbUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_POST (0xb4689622UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_PRE (0x67fabcc3UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ENABLE (0x5fe64af7UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_INIT (0xb2cc8c4aUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_PRESET (0x801966f7UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_RX_READY (0x5bc27345UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3 (0x27e940feUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_MAIN (0xbe085cf5UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_POST (0x5baafd1cUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_PRE (0x7081a880UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ENABLE (0x934c4a69UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_INIT (0x79905fefUL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_PRESET (0x4cb36669UL) > +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_RX_READY (0xb400187bUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0 (0xf12740e1UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_MAIN_STA > (0xc1d6a542UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_POST_STA (0xfe4a543bUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_PRE_STA (0x3d4a42d1UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1 (0x86207077UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_MAIN_STA > (0x2e14ce7cUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_POST_STA (0x11883f05UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_PRE_STA (0x2a315692UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2 (0x1f2921cdUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_MAIN_STA > (0xc523757fUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_POST_STA (0xfabf8406UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_PRE_STA (0x13bc6a57UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3 (0x682e115bUL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_MAIN_STA > (0x2ae11e41UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_POST_STA (0x157def38UL) > +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_PRE_STA (0x4c77e14UL) > +#define MAC_PCS_XXV_RST_0 (0xbc41405eUL) > +#define MAC_PCS_XXV_RST_0_MAC_PCS (0xb425c579UL) > +#define MAC_PCS_XXV_RST_1 (0xcb4670c8UL) > +#define MAC_PCS_XXV_RST_1_MAC_PCS (0xa35ed13aUL) > +#define MAC_PCS_XXV_RST_2 (0x524f2172UL) > +#define MAC_PCS_XXV_RST_2_MAC_PCS (0x9ad3edffUL) > +#define MAC_PCS_XXV_RST_3 (0x254811e4UL) > +#define MAC_PCS_XXV_RST_3_MAC_PCS (0x8da8f9bcUL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0 (0x1fc33ac9UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0_RS_FEC_CCW_CNT > (0x63c40291UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1 (0x68c40a5fUL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1_RS_FEC_CCW_CNT > (0xcdac9300UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2 (0xf1cd5be5UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2_RS_FEC_CCW_CNT > (0xe46427f2UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3 (0x86ca6b73UL) > +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3_RS_FEC_CCW_CNT > (0x4a0cb663UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0 (0x7de9885UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0_CONSORTIUM (0xaf731a5bUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_CORRECTION > (0x574a1223UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_ENABLE (0xc8d960dUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_IEEE_ERROR_INDICATION > (0xe5a25113UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_INDICATION > (0x2487d64cUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1 (0x70d9a813UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1_CONSORTIUM (0x34d65634UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_CORRECTION > (0x80a8927bUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_ENABLE (0xb5764de5UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_IEEE_ERROR_INDICATION > (0xd9c2b21bUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_INDICATION > (0xf3655614UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2 (0xe9d0f9a9UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2_CONSORTIUM (0x434884c4UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_CORRECTION > (0x23fe14d2UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_ENABLE (0xa40b279cUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_IEEE_ERROR_INDICATION > (0x9d639703UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_INDICATION > (0x5033d0bdUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3 (0x9ed7c93fUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3_CONSORTIUM (0xd8edc8abUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_CORRECTION > (0xf41c948aUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_ENABLE (0x1df0fc74UL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_IEEE_ERROR_INDICATION > (0xa103740bUL) > +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_INDICATION > (0x87d150e5UL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0 (0x8ef05d51UL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0_RS_FEC_ERR_CNT > (0x61cba0edUL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1 (0xf9f76dc7UL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1_RS_FEC_ERR_CNT > (0xcfa3317cUL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2 (0x60fe3c7dUL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2_RS_FEC_ERR_CNT > (0xe66b858eUL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3 (0x17f90cebUL) > +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3_RS_FEC_ERR_CNT > (0x4803141fUL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0 (0xc0190132UL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0_RS_FEC_UCW_CNT > (0xa89c8608UL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1 (0xb71e31a4UL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1_RS_FEC_UCW_CNT > (0x6f41799UL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2 (0x2e17601eUL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2_RS_FEC_UCW_CNT > (0x2f3ca36bUL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3 (0x59105088UL) > +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3_RS_FEC_UCW_CNT > (0x815432faUL) > +#define MAC_PCS_XXV_RX_BAD_FCS_0 (0x53d3df14UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_0_COUNT (0xf1329ab1UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_1 (0x24d4ef82UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_1_COUNT (0x57459105UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_2 (0xbdddbe38UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_2_COUNT (0x66ad8b98UL) > +#define MAC_PCS_XXV_RX_BAD_FCS_3 (0xcada8eaeUL) > +#define MAC_PCS_XXV_RX_BAD_FCS_3_COUNT (0xc0da802cUL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_0 (0x88c256ceUL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_0_COUNT (0x97189d30UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_1 (0xffc56658UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_1_COUNT (0x316f9684UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_2 (0x66cc37e2UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_2_COUNT (0x878c19UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_3 (0x11cb0774UL) > +#define MAC_PCS_XXV_RX_FRAMING_ERROR_3_COUNT (0xa6f087adUL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_0 (0xdb9d71adUL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_0_COUNT (0x970d9ccdUL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_1 (0xac9a413bUL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_1_COUNT (0x317a9779UL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_2 (0x35931081UL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_2_COUNT (0x928de4UL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_3 (0x42942017UL) > +#define MAC_PCS_XXV_RX_GOOD_BYTES_3_COUNT (0xa6e58650UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_0 (0xa1a32858UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_0_COUNT (0xaec3dbc9UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_1 (0xd6a418ceUL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_1_COUNT (0x8b4d07dUL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_2 (0x4fad4974UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_2_COUNT (0x395ccae0UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_3 (0x38aa79e2UL) > +#define MAC_PCS_XXV_RX_GOOD_PACKETS_3_COUNT (0x9f2bc154UL) > +#define MAC_PCS_XXV_RX_LATENCY_0 (0x636577a2UL) > +#define MAC_PCS_XXV_RX_LATENCY_0_LATENCY (0x5bc360b1UL) > +#define MAC_PCS_XXV_RX_LATENCY_1 (0x14624734UL) > +#define MAC_PCS_XXV_RX_LATENCY_1_LATENCY (0x4cb874f2UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_0 (0x566d6603UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_0_COUNT (0x95039b5UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_1 (0x216a5695UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_1_COUNT (0xaf273201UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_2 (0xb863072fUL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_2_COUNT (0x9ecf289cUL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_3 (0xcf6437b9UL) > +#define MAC_PCS_XXV_RX_TOTAL_BYTES_3_COUNT (0x38b82328UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0 (0x12f4b108UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0_COUNT (0xef99e10dUL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1 (0x65f3819eUL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1_COUNT (0x49eeeab9UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2 (0xfcfad024UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2_COUNT (0x7806f024UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3 (0x8bfde0b2UL) > +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3_COUNT (0xde71fb90UL) > +#define MAC_PCS_XXV_SUB_RST_0 (0xcea66ca4UL) > +#define MAC_PCS_XXV_SUB_RST_0_AN_LT (0xe868535cUL) > +#define MAC_PCS_XXV_SUB_RST_0_QPLL (0xf8a38742UL) > +#define MAC_PCS_XXV_SUB_RST_0_RX_BUF (0x56ef70f8UL) > +#define MAC_PCS_XXV_SUB_RST_0_RX_GT_DATA (0x233f5adcUL) > +#define MAC_PCS_XXV_SUB_RST_0_RX_MAC_PCS (0x1d82003eUL) > +#define MAC_PCS_XXV_SUB_RST_0_RX_PCS (0x380856daUL) > +#define MAC_PCS_XXV_SUB_RST_0_RX_PMA (0x55320a1cUL) > +#define MAC_PCS_XXV_SUB_RST_0_SPEED_CTRL (0xa1c62fb2UL) > +#define MAC_PCS_XXV_SUB_RST_0_TX_GT_DATA (0x2e212a9bUL) > +#define MAC_PCS_XXV_SUB_RST_0_TX_MAC_PCS (0x109c7079UL) > +#define MAC_PCS_XXV_SUB_RST_0_TX_PCS (0xee51b5c7UL) > +#define MAC_PCS_XXV_SUB_RST_0_TX_PMA (0x836be901UL) > +#define MAC_PCS_XXV_SUB_RST_1 (0xb9a15c32UL) > +#define MAC_PCS_XXV_SUB_RST_1_AN_LT (0x4e1f58e8UL) > +#define MAC_PCS_XXV_SUB_RST_1_QPLL (0x33ff54e7UL) > +#define MAC_PCS_XXV_SUB_RST_1_RX_BUF (0x9a457066UL) > +#define MAC_PCS_XXV_SUB_RST_1_RX_GT_DATA (0xb89a16b3UL) > +#define MAC_PCS_XXV_SUB_RST_1_RX_MAC_PCS (0x86274c51UL) > +#define MAC_PCS_XXV_SUB_RST_1_RX_PCS (0xf4a25644UL) > +#define MAC_PCS_XXV_SUB_RST_1_RX_PMA (0x99980a82UL) > +#define MAC_PCS_XXV_SUB_RST_1_SPEED_CTRL (0x3a6363ddUL) > +#define MAC_PCS_XXV_SUB_RST_1_TX_GT_DATA (0xb58466f4UL) > +#define MAC_PCS_XXV_SUB_RST_1_TX_MAC_PCS (0x8b393c16UL) > +#define MAC_PCS_XXV_SUB_RST_1_TX_PCS (0x22fbb559UL) > +#define MAC_PCS_XXV_SUB_RST_1_TX_PMA (0x4fc1e99fUL) > +#define MAC_PCS_XXV_SUB_RST_2 (0x20a80d88UL) > +#define MAC_PCS_XXV_SUB_RST_2_AN_LT (0x7ff74275UL) > +#define MAC_PCS_XXV_SUB_RST_2_QPLL (0xb56b2649UL) > +#define MAC_PCS_XXV_SUB_RST_2_RX_BUF (0x14ca7785UL) > +#define MAC_PCS_XXV_SUB_RST_2_RX_GT_DATA (0xcf04c443UL) > +#define MAC_PCS_XXV_SUB_RST_2_RX_MAC_PCS (0xf1b99ea1UL) > +#define MAC_PCS_XXV_SUB_RST_2_RX_PCS (0x7a2d51a7UL) > +#define MAC_PCS_XXV_SUB_RST_2_RX_PMA (0x17170d61UL) > +#define MAC_PCS_XXV_SUB_RST_2_SPEED_CTRL (0x4dfdb12dUL) > +#define MAC_PCS_XXV_SUB_RST_2_TX_GT_DATA (0xc21ab404UL) > +#define MAC_PCS_XXV_SUB_RST_2_TX_MAC_PCS (0xfca7eee6UL) > +#define MAC_PCS_XXV_SUB_RST_2_TX_PCS (0xac74b2baUL) > +#define MAC_PCS_XXV_SUB_RST_2_TX_PMA (0xc14eee7cUL) > +#define MAC_PCS_XXV_SUB_RST_3 (0x57af3d1eUL) > +#define MAC_PCS_XXV_SUB_RST_3_AN_LT (0xd98049c1UL) > +#define MAC_PCS_XXV_SUB_RST_3_QPLL (0x7e37f5ecUL) > +#define MAC_PCS_XXV_SUB_RST_3_RX_BUF (0xd860771bUL) > +#define MAC_PCS_XXV_SUB_RST_3_RX_GT_DATA (0x54a1882cUL) > +#define MAC_PCS_XXV_SUB_RST_3_RX_MAC_PCS (0x6a1cd2ceUL) > +#define MAC_PCS_XXV_SUB_RST_3_RX_PCS (0xb6875139UL) > +#define MAC_PCS_XXV_SUB_RST_3_RX_PMA (0xdbbd0dffUL) > +#define MAC_PCS_XXV_SUB_RST_3_SPEED_CTRL (0xd658fd42UL) > +#define MAC_PCS_XXV_SUB_RST_3_TX_GT_DATA (0x59bff86bUL) > +#define MAC_PCS_XXV_SUB_RST_3_TX_MAC_PCS (0x6702a289UL) > +#define MAC_PCS_XXV_SUB_RST_3_TX_PCS (0x60deb224UL) > +#define MAC_PCS_XXV_SUB_RST_3_TX_PMA (0xde4eee2UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_0 (0x31f1d051UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_0_QPLL_LOCK (0x2c39cf3dUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_RX_RST > (0xa1223741UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_TX_RST (0x777bd45cUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_1 (0x46f6e0c7UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_1_QPLL_LOCK (0xedb710fdUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_RX_RST (0x7cb4eec4UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_TX_RST (0xaaed0dd9UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_2 (0xdfffb17dUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_2_QPLL_LOCK (0x745576fcUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_RX_RST (0xc17e820aUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_TX_RST > (0x17276117UL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_3 (0xa8f881ebUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_3_QPLL_LOCK (0xb5dba93cUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_RX_RST (0x1ce85b8fUL) > +#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_TX_RST (0xcab1b892UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_0 (0xa5e7869aUL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_0_RX_DLY (0x825d4fb7UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_0_TX_DLY (0x5404acaaUL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_1 (0xd2e0b60cUL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_1_RX_DLY (0x4ef74f29UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_1_TX_DLY (0x98aeac34UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_2 (0x4be9e7b6UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_2_RX_DLY (0xc07848caUL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_2_TX_DLY (0x1621abd7UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_3 (0x3ceed720UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_3_RX_DLY (0xcd24854UL) > +#define MAC_PCS_XXV_TIMESTAMP_COMP_3_TX_DLY (0xda8bab49UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_0 (0xbcee7af4UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_0_COUNT (0xff4e2634UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_1 (0xcbe94a62UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_1_COUNT (0x59392d80UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_2 (0x52e01bd8UL) > +#define MAC_PCS_XXV_TX_BAD_FCS_2_COUNT (0x68d1371dUL) > +#define MAC_PCS_XXV_TX_BAD_FCS_3 (0x25e72b4eUL) > +#define MAC_PCS_XXV_TX_BAD_FCS_3_COUNT (0xcea63ca9UL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_0 (0x64717f86UL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_0_COUNT (0x17fd90f4UL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_1 (0x13764f10UL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_1_COUNT (0xb18a9b40UL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_2 (0x8a7f1eaaUL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_2_COUNT (0x806281ddUL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_3 (0xfd782e3cUL) > +#define MAC_PCS_XXV_TX_FRAME_ERROR_3_COUNT (0x26158a69UL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_0 (0xf967a55fUL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_0_COUNT (0x6130990bUL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_1 (0x8e6095c9UL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_1_COUNT (0xc74792bfUL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_2 (0x1769c473UL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_2_COUNT (0xf6af8822UL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_3 (0x606ef4e5UL) > +#define MAC_PCS_XXV_TX_GOOD_BYTES_3_COUNT (0x50d88396UL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_0 (0x6979f50UL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_0_COUNT (0x4309a9b3UL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_1 (0x7190afc6UL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_1_COUNT (0xe57ea207UL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_2 (0xe899fe7cUL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_2_COUNT (0xd496b89aUL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_3 (0x9f9eceeaUL) > +#define MAC_PCS_XXV_TX_GOOD_PACKETS_3_COUNT (0x72e1b32eUL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_0 (0x5fc0fe7UL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_0_COUNT (0x7ba16335UL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_1 (0x72fb3f71UL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_1_COUNT (0xddd66881UL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_2 (0xebf26ecbUL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_2_COUNT (0xec3e721cUL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_3 (0x9cf55e5dUL) > +#define MAC_PCS_XXV_TX_TOTAL_BYTES_3_COUNT (0x4a4979a8UL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0 (0x1c880d8dUL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0_COUNT (0x5fa4b35dUL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1 (0x6b8f3d1bUL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1_COUNT (0xf9d3b8e9UL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2 (0xf2866ca1UL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2_COUNT (0xc83ba274UL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3 (0x85815c37UL) > +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3_COUNT (0x6e4ca9c0UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h > new file mode 100644 > index 0000000000..e8dcf06144 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h > @@ -0,0 +1,90 @@ > +/* > + * nthw_fpga_reg_defs_mac_rx.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_RX_ > +#define _NTHW_FPGA_REG_DEFS_MAC_RX_ > + > +/* MAC_RX */ > +#define NTHW_MOD_MAC_RX (0x6347b490UL) > +#define MAC_RX_BAD_FCS (0xca07f618UL) > +#define MAC_RX_BAD_FCS_COUNT (0x11d5ba0eUL) > +#define MAC_RX_BAD_PREAMBLE (0x8a9e1895UL) > +#define MAC_RX_BAD_PREAMBLE_COUNT (0x94cde758UL) > +#define MAC_RX_BAD_SFD (0x2e4ee601UL) > +#define MAC_RX_BAD_SFD_COUNT (0x1d1b1114UL) > +#define MAC_RX_BROADCAST (0xc601a955UL) > +#define MAC_RX_BROADCAST_COUNT (0x34215d1eUL) > +#define MAC_RX_FRAGMENT (0x5363b736UL) > +#define MAC_RX_FRAGMENT_COUNT (0xf664c9aUL) > +#define MAC_RX_INRANGEERR (0x8c827f5aUL) > +#define MAC_RX_INRANGEERR_COUNT (0x412374f1UL) > +#define MAC_RX_JABBER (0x2e057c27UL) > +#define MAC_RX_JABBER_COUNT (0x1b4d17b2UL) > +#define MAC_RX_MULTICAST (0x891e2299UL) > +#define MAC_RX_MULTICAST_COUNT (0xe7818f66UL) > +#define MAC_RX_OVERSIZE (0x7630fc85UL) > +#define MAC_RX_OVERSIZE_COUNT (0x5b25605eUL) > +#define MAC_RX_PACKET_1024_1518_BYTES (0xe525d34dUL) > +#define MAC_RX_PACKET_1024_1518_BYTES_COUNT (0x7d9de556UL) > +#define MAC_RX_PACKET_128_255_BYTES (0xcd8a378bUL) > +#define MAC_RX_PACKET_128_255_BYTES_COUNT (0x442e67ebUL) > +#define MAC_RX_PACKET_1519_1522_BYTES (0x681c88adUL) > +#define MAC_RX_PACKET_1519_1522_BYTES_COUNT (0x40d43ff6UL) > +#define MAC_RX_PACKET_1523_1548_BYTES (0x5dfe5acbUL) > +#define MAC_RX_PACKET_1523_1548_BYTES_COUNT (0x339a5140UL) > +#define MAC_RX_PACKET_1549_2047_BYTES (0x40c4e3d2UL) > +#define MAC_RX_PACKET_1549_2047_BYTES_COUNT (0x81fc4090UL) > +#define MAC_RX_PACKET_2048_4095_BYTES (0x4f3bdf16UL) > +#define MAC_RX_PACKET_2048_4095_BYTES_COUNT (0xba0d0879UL) > +#define MAC_RX_PACKET_256_511_BYTES (0x42cadeecUL) > +#define MAC_RX_PACKET_256_511_BYTES_COUNT (0x566f927UL) > +#define MAC_RX_PACKET_4096_8191_BYTES (0x3ad4685aUL) > +#define MAC_RX_PACKET_4096_8191_BYTES_COUNT (0xbc56edbfUL) > +#define MAC_RX_PACKET_512_1023_BYTES (0xa88bf6b7UL) > +#define MAC_RX_PACKET_512_1023_BYTES_COUNT (0x15430ff8UL) > +#define MAC_RX_PACKET_64_BYTES (0x35e6dcadUL) > +#define MAC_RX_PACKET_64_BYTES_COUNT (0xf81dddUL) > +#define MAC_RX_PACKET_65_127_BYTES (0x262f6a19UL) > +#define MAC_RX_PACKET_65_127_BYTES_COUNT (0xb010dafUL) > +#define MAC_RX_PACKET_8192_9215_BYTES (0x10cd73eaUL) > +#define MAC_RX_PACKET_8192_9215_BYTES_COUNT (0xa967837aUL) > +#define MAC_RX_PACKET_BAD_FCS (0x4cb8b34cUL) > +#define MAC_RX_PACKET_BAD_FCS_COUNT (0xb6701e28UL) > +#define MAC_RX_PACKET_LARGE (0xc11f49c8UL) > +#define MAC_RX_PACKET_LARGE_COUNT (0x884a975UL) > +#define MAC_RX_PACKET_SMALL (0xed318a65UL) > +#define MAC_RX_PACKET_SMALL_COUNT (0x72095ec7UL) > +#define MAC_RX_STOMPED_FCS (0xedbc183eUL) > +#define MAC_RX_STOMPED_FCS_COUNT (0xa0b5bc65UL) > +#define MAC_RX_TOOLONG (0x61da6643UL) > +#define MAC_RX_TOOLONG_COUNT (0xa789b6efUL) > +#define MAC_RX_TOTAL_BYTES (0x831313e2UL) > +#define MAC_RX_TOTAL_BYTES_COUNT (0xe5d8be59UL) > +#define MAC_RX_TOTAL_GOOD_BYTES (0x912c2d1cUL) > +#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (0x63bb5f3eUL) > +#define MAC_RX_TOTAL_GOOD_PACKETS (0xfbb4f497UL) > +#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (0xae9d21b0UL) > +#define MAC_RX_TOTAL_PACKETS (0xb0ea3730UL) > +#define MAC_RX_TOTAL_PACKETS_COUNT (0x532c885dUL) > +#define MAC_RX_TRUNCATED (0x28c83348UL) > +#define MAC_RX_TRUNCATED_COUNT (0xb8e62fccUL) > +#define MAC_RX_UNDERSIZE (0xb6fa4bdbUL) > +#define MAC_RX_UNDERSIZE_COUNT (0x471945ffUL) > +#define MAC_RX_UNICAST (0xaa9e5b6cUL) > +#define MAC_RX_UNICAST_COUNT (0x814ecbf0UL) > +#define MAC_RX_VLAN (0x2f200d8dUL) > +#define MAC_RX_VLAN_COUNT (0xf156d97eUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_RX_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h > new file mode 100644 > index 0000000000..0b36ffbea1 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h > @@ -0,0 +1,42 @@ > +/* > + * nthw_fpga_reg_defs_mac_tfg.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_TFG_ > +#define _NTHW_FPGA_REG_DEFS_MAC_TFG_ > + > +/* MAC_TFG */ > +#define NTHW_MOD_MAC_TFG (0x1a1aac23UL) > +#define MAC_TFG_TFG_ADDR (0x90a59c6bUL) > +#define MAC_TFG_TFG_ADDR_ADR (0x3ad0b041UL) > +#define MAC_TFG_TFG_ADDR_RDENA (0x32d2aecdUL) > +#define MAC_TFG_TFG_ADDR_RD_DONE (0x29dc9218UL) > +#define MAC_TFG_TFG_CTRL (0xc01d7f24UL) > +#define MAC_TFG_TFG_CTRL_ID_ENA (0x226f646eUL) > +#define MAC_TFG_TFG_CTRL_ID_POS (0xd22045fcUL) > +#define MAC_TFG_TFG_CTRL_RESTART (0xfd4f999eUL) > +#define MAC_TFG_TFG_CTRL_TG_ACT (0x5fd3d81UL) > +#define MAC_TFG_TFG_CTRL_TG_ENA (0xda870ffbUL) > +#define MAC_TFG_TFG_CTRL_TIME_MODE (0xa96c2409UL) > +#define MAC_TFG_TFG_CTRL_WRAP (0xdb215a6eUL) > +#define MAC_TFG_TFG_DATA (0x6fccfd3dUL) > +#define MAC_TFG_TFG_DATA_GAP (0x936a9790UL) > +#define MAC_TFG_TFG_DATA_ID (0x82eba4faUL) > +#define MAC_TFG_TFG_DATA_LENGTH (0x6db149f2UL) > +#define MAC_TFG_TFG_FRAME_HDR (0x632d9e2cUL) > +#define MAC_TFG_TFG_FRAME_HDR_HDR (0xe7a88ec1UL) > +#define MAC_TFG_TFG_REPETITION (0xde9617ebUL) > +#define MAC_TFG_TFG_REPETITION_CNT (0x4fee626dUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_TFG_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h > new file mode 100644 > index 0000000000..d05556bce4 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h > @@ -0,0 +1,70 @@ > +/* > + * nthw_fpga_reg_defs_mac_tx.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MAC_TX_ > +#define _NTHW_FPGA_REG_DEFS_MAC_TX_ > + > +/* MAC_TX */ > +#define NTHW_MOD_MAC_TX (0x351d1316UL) > +#define MAC_TX_BAD_FCS (0xc719865fUL) > +#define MAC_TX_BAD_FCS_COUNT (0x4244d3eaUL) > +#define MAC_TX_BROADCAST (0x293c0cb5UL) > +#define MAC_TX_BROADCAST_COUNT (0x3a5de19bUL) > +#define MAC_TX_FRAME_ERRORS (0xaa9219a8UL) > +#define MAC_TX_FRAME_ERRORS_COUNT (0x63d223c3UL) > +#define MAC_TX_MULTICAST (0x66238779UL) > +#define MAC_TX_MULTICAST_COUNT (0xe9fd33e3UL) > +#define MAC_TX_PACKET_1024_1518_BYTES (0x8efebfebUL) > +#define MAC_TX_PACKET_1024_1518_BYTES_COUNT (0x5bcd97b0UL) > +#define MAC_TX_PACKET_128_255_BYTES (0x204045f1UL) > +#define MAC_TX_PACKET_128_255_BYTES_COUNT (0xd54fb772UL) > +#define MAC_TX_PACKET_1519_1522_BYTES (0x3c7e40bUL) > +#define MAC_TX_PACKET_1519_1522_BYTES_COUNT (0x66844d10UL) > +#define MAC_TX_PACKET_1523_1548_BYTES (0x3625366dUL) > +#define MAC_TX_PACKET_1523_1548_BYTES_COUNT (0x15ca23a6UL) > +#define MAC_TX_PACKET_1549_2047_BYTES (0x2b1f8f74UL) > +#define MAC_TX_PACKET_1549_2047_BYTES_COUNT (0xa7ac3276UL) > +#define MAC_TX_PACKET_2048_4095_BYTES (0x24e0b3b0UL) > +#define MAC_TX_PACKET_2048_4095_BYTES_COUNT (0x9c5d7a9fUL) > +#define MAC_TX_PACKET_256_511_BYTES (0xaf00ac96UL) > +#define MAC_TX_PACKET_256_511_BYTES_COUNT (0x940729beUL) > +#define MAC_TX_PACKET_4096_8191_BYTES (0x510f04fcUL) > +#define MAC_TX_PACKET_4096_8191_BYTES_COUNT (0x9a069f59UL) > +#define MAC_TX_PACKET_512_1023_BYTES (0x18b6a4e7UL) > +#define MAC_TX_PACKET_512_1023_BYTES_COUNT (0x9c0145c8UL) > +#define MAC_TX_PACKET_64_BYTES (0x3b9a6028UL) > +#define MAC_TX_PACKET_64_BYTES_COUNT (0xb0c54f8dUL) > +#define MAC_TX_PACKET_65_127_BYTES (0x54de3099UL) > +#define MAC_TX_PACKET_65_127_BYTES_COUNT (0xebd03e1UL) > +#define MAC_TX_PACKET_8192_9215_BYTES (0x7b161f4cUL) > +#define MAC_TX_PACKET_8192_9215_BYTES_COUNT (0x8f37f19cUL) > +#define MAC_TX_PACKET_LARGE (0xe3e59d3aUL) > +#define MAC_TX_PACKET_LARGE_COUNT (0xfeb9acb3UL) > +#define MAC_TX_PACKET_SMALL (0xcfcb5e97UL) > +#define MAC_TX_PACKET_SMALL_COUNT (0x84345b01UL) > +#define MAC_TX_TOTAL_BYTES (0x7bd15854UL) > +#define MAC_TX_TOTAL_BYTES_COUNT (0x61fb238cUL) > +#define MAC_TX_TOTAL_GOOD_BYTES (0xcf0260fUL) > +#define MAC_TX_TOTAL_GOOD_BYTES_COUNT (0x8603398UL) > +#define MAC_TX_TOTAL_GOOD_PACKETS (0xd89f151UL) > +#define MAC_TX_TOTAL_GOOD_PACKETS_COUNT (0x12c47c77UL) > +#define MAC_TX_TOTAL_PACKETS (0xe37b5ed4UL) > +#define MAC_TX_TOTAL_PACKETS_COUNT (0x21ddd2ddUL) > +#define MAC_TX_UNICAST (0xa7802b2bUL) > +#define MAC_TX_UNICAST_COUNT (0xd2dfa214UL) > +#define MAC_TX_VLAN (0x4cf038b7UL) > +#define MAC_TX_VLAN_COUNT (0x51b306a3UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MAC_TX_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h > new file mode 100644 > index 0000000000..fdc74e56bd > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h > @@ -0,0 +1,42 @@ > +/* > + * nthw_fpga_reg_defs_msk.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_MSK_ > +#define _NTHW_FPGA_REG_DEFS_MSK_ > + > +/* MSK */ > +#define NTHW_MOD_MSK (0xcfd617eeUL) > +#define MSK_RCP_CTRL (0xc1c33daaUL) > +#define MSK_RCP_CTRL_ADR (0x350a336UL) > +#define MSK_RCP_CTRL_CNT (0x13583ae7UL) > +#define MSK_RCP_DATA (0x6e12bfb3UL) > +#define MSK_RCP_DATA_MASK_DYN0 (0x9d269a43UL) > +#define MSK_RCP_DATA_MASK_DYN1 (0xea21aad5UL) > +#define MSK_RCP_DATA_MASK_DYN2 (0x7328fb6fUL) > +#define MSK_RCP_DATA_MASK_DYN3 (0x42fcbf9UL) > +#define MSK_RCP_DATA_MASK_EN0 (0x487b2e09UL) > +#define MSK_RCP_DATA_MASK_EN1 (0x3f7c1e9fUL) > +#define MSK_RCP_DATA_MASK_EN2 (0xa6754f25UL) > +#define MSK_RCP_DATA_MASK_EN3 (0xd1727fb3UL) > +#define MSK_RCP_DATA_MASK_LEN0 (0x4daee8b8UL) > +#define MSK_RCP_DATA_MASK_LEN1 (0x3aa9d82eUL) > +#define MSK_RCP_DATA_MASK_LEN2 (0xa3a08994UL) > +#define MSK_RCP_DATA_MASK_LEN3 (0xd4a7b902UL) > +#define MSK_RCP_DATA_MASK_OFS0 (0xa2319513UL) > +#define MSK_RCP_DATA_MASK_OFS1 (0xd536a585UL) > +#define MSK_RCP_DATA_MASK_OFS2 (0x4c3ff43fUL) > +#define MSK_RCP_DATA_MASK_OFS3 (0x3b38c4a9UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_MSK_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h > new file mode 100644 > index 0000000000..c21a1b20c3 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h > @@ -0,0 +1,37 @@ > +/* > + * nthw_fpga_reg_defs_pci_rd_tg.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ > +#define _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ > + > +/* PCI_RD_TG */ > +#define NTHW_MOD_PCI_RD_TG (0x9ad9eed2UL) > +#define PCI_RD_TG_TG_CTRL (0x5a899dc8UL) > +#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (0x66c70bffUL) > +#define PCI_RD_TG_TG_RDADDR (0x39e1af65UL) > +#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (0xf6b0ecd1UL) > +#define PCI_RD_TG_TG_RDDATA0 (0x4bcd36f9UL) > +#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (0xa4479fe8UL) > +#define PCI_RD_TG_TG_RDDATA1 (0x3cca066fUL) > +#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (0x6b3563dfUL) > +#define PCI_RD_TG_TG_RDDATA2 (0xa5c357d5UL) > +#define PCI_RD_TG_TG_RDDATA2_REQ_HID (0x5dab4bc3UL) > +#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (0x85dd8d92UL) > +#define PCI_RD_TG_TG_RDDATA2_WAIT (0x85ba70b2UL) > +#define PCI_RD_TG_TG_RDDATA2_WRAP (0x546e238aUL) > +#define PCI_RD_TG_TG_RD_RUN (0xd6542f54UL) > +#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (0xcdc6e166UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h > new file mode 100644 > index 0000000000..43dacda70a > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h > @@ -0,0 +1,32 @@ > +/* > + * nthw_fpga_reg_defs_pci_ta.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCI_TA_ > +#define _NTHW_FPGA_REG_DEFS_PCI_TA_ > + > +/* PCI_TA */ > +#define NTHW_MOD_PCI_TA (0xfb431997UL) > +#define PCI_TA_CONTROL (0xa707df59UL) > +#define PCI_TA_CONTROL_ENABLE (0x87cdcc9aUL) > +#define PCI_TA_LENGTH_ERROR (0x8648b862UL) > +#define PCI_TA_LENGTH_ERROR_AMOUNT (0x8774bd63UL) > +#define PCI_TA_PACKET_BAD (0xaaa256d4UL) > +#define PCI_TA_PACKET_BAD_AMOUNT (0x601f72f3UL) > +#define PCI_TA_PACKET_GOOD (0xfc13da6cUL) > +#define PCI_TA_PACKET_GOOD_AMOUNT (0xd936d64dUL) > +#define PCI_TA_PAYLOAD_ERROR (0x69d7a09bUL) > +#define PCI_TA_PAYLOAD_ERROR_AMOUNT (0x445da330UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCI_TA_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h > new file mode 100644 > index 0000000000..491152bb97 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h > @@ -0,0 +1,40 @@ > +/* > + * nthw_fpga_reg_defs_pci_wr_tg.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ > +#define _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ > + > +/* PCI_WR_TG */ > +#define NTHW_MOD_PCI_WR_TG (0x274b69e1UL) > +#define PCI_WR_TG_TG_CTRL (0xa48366c7UL) > +#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (0x9983a3e8UL) > +#define PCI_WR_TG_TG_SEQ (0x8b3e0bd6UL) > +#define PCI_WR_TG_TG_SEQ_SEQUENCE (0xebf1c760UL) > +#define PCI_WR_TG_TG_WRADDR (0x2b7b95a5UL) > +#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (0x5fdc2aceUL) > +#define PCI_WR_TG_TG_WRDATA0 (0xd0bb6e73UL) > +#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (0x97cb1c89UL) > +#define PCI_WR_TG_TG_WRDATA1 (0xa7bc5ee5UL) > +#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (0x51b3be92UL) > +#define PCI_WR_TG_TG_WRDATA2 (0x3eb50f5fUL) > +#define PCI_WR_TG_TG_WRDATA2_INC_MODE (0x5be5577UL) > +#define PCI_WR_TG_TG_WRDATA2_REQ_HID (0xf4c78ddcUL) > +#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (0x87ceca1UL) > +#define PCI_WR_TG_TG_WRDATA2_WAIT (0xb29cb8ffUL) > +#define PCI_WR_TG_TG_WRDATA2_WRAP (0x6348ebc7UL) > +#define PCI_WR_TG_TG_WR_RUN (0xc4ce1594UL) > +#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (0xe83c0a22UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h > new file mode 100644 > index 0000000000..4b8bf53cd9 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h > @@ -0,0 +1,281 @@ > +/* > + * nthw_fpga_reg_defs_pcie3.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_ > +#define _NTHW_FPGA_REG_DEFS_PCIE3_ > + > +/* PCIE3 */ > +#define NTHW_MOD_PCIE3 (0xfbc48c18UL) > +#define PCIE3_BUILD_SEED (0x7a6457c5UL) > +#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL) > +#define PCIE3_BUILD_TIME (0x51772c86UL) > +#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL) > +#define PCIE3_CONFIG (0xe7ef0d51UL) > +#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL) > +#define PCIE3_CONFIG_MAX_READ (0x2943f801UL) > +#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL) > +#define PCIE3_CONTROL (0x935935d4UL) > +#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL) > +#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL) > +#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL) > +#define PCIE3_CORESPEED (0x5cbe0925UL) > +#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL) > +#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL) > +#define PCIE3_DRP_COMMON (0xffd331a2UL) > +#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL) > +#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL) > +#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL) > +#define PCIE3_DRP_COMMON_WR (0xbe76449eUL) > +#define PCIE3_DRP_DATE (0xeaae0e97UL) > +#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL) > +#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL) > +#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL) > +#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL) > +#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL) > +#define PCIE3_INT_CLR (0xcde216faUL) > +#define PCIE3_INT_CLR_AVR (0x1982c8eUL) > +#define PCIE3_INT_CLR_FHM (0x5d9e0821UL) > +#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL) > +#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL) > +#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL) > +#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL) > +#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL) > +#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL) > +#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL) > +#define PCIE3_INT_CLR_INT_15 (0xbda934afUL) > +#define PCIE3_INT_CLR_INT_16 (0x24a06515UL) > +#define PCIE3_INT_CLR_INT_17 (0x53a75583UL) > +#define PCIE3_INT_CLR_INT_18 (0xc3184812UL) > +#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL) > +#define PCIE3_INT_CLR_INT_2 (0x82a59259UL) > +#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL) > +#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL) > +#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL) > +#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL) > +#define PCIE3_INT_CLR_INT_24 (0xe18357faUL) > +#define PCIE3_INT_CLR_INT_25 (0x9684676cUL) > +#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL) > +#define PCIE3_INT_CLR_INT_27 (0x788a0640UL) > +#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL) > +#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL) > +#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL) > +#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL) > +#define PCIE3_INT_CLR_INT_31 (0x88f29234UL) > +#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL) > +#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL) > +#define PCIE3_INT_CLR_INT_6 (0x85c85640UL) > +#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL) > +#define PCIE3_INT_CLR_INT_8 (0x62707b47UL) > +#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL) > +#define PCIE3_INT_CLR_PORT (0x4f57e46eUL) > +#define PCIE3_INT_CLR_PPS (0x3d2172d9UL) > +#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL) > +#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL) > +#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL) > +#define PCIE3_INT_CLR_STA (0xa8b278ccUL) > +#define PCIE3_INT_CLR_TIMER (0x696afaafUL) > +#define PCIE3_INT_FORC (0x55ea48d8UL) > +#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL) > +#define PCIE3_INT_FORC_FHM (0x78afd50UL) > +#define PCIE3_INT_FORC_INT_0 (0x9758e745UL) > +#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL) > +#define PCIE3_INT_FORC_INT_10 (0xebe10398UL) > +#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL) > +#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL) > +#define PCIE3_INT_FORC_INT_13 (0x72e85222UL) > +#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL) > +#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL) > +#define PCIE3_INT_FORC_INT_16 (0x282a6adUL) > +#define PCIE3_INT_FORC_INT_17 (0x7585963bUL) > +#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL) > +#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL) > +#define PCIE3_INT_FORC_INT_2 (0x79568669UL) > +#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL) > +#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL) > +#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL) > +#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL) > +#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL) > +#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL) > +#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL) > +#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL) > +#define PCIE3_INT_FORC_INT_28 (0xce17d869UL) > +#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL) > +#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL) > +#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL) > +#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL) > +#define PCIE3_INT_FORC_INT_4 (0x9035235cUL) > +#define PCIE3_INT_FORC_INT_5 (0xe73213caUL) > +#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL) > +#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL) > +#define PCIE3_INT_FORC_INT_8 (0x99836f77UL) > +#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL) > +#define PCIE3_INT_FORC_PORT (0x680fb131UL) > +#define PCIE3_INT_FORC_PPS (0x673587a8UL) > +#define PCIE3_INT_FORC_QSPI (0x94bf821bUL) > +#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL) > +#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL) > +#define PCIE3_INT_FORC_STA (0xf2a68dbdUL) > +#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL) > +#define PCIE3_INT_MASK (0x9fb55ba0UL) > +#define PCIE3_INT_MASK_AVR (0xadf52690UL) > +#define PCIE3_INT_MASK_FHM (0xf1f3023fUL) > +#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL) > +#define PCIE3_INT_MASK_IIC1 (0xf2696667UL) > +#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL) > +#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL) > +#define PCIE3_INT_MASK_IIC4 (0x820392e8UL) > +#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL) > +#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL) > +#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL) > +#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL) > +#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL) > +#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL) > +#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL) > +#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL) > +#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL) > +#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL) > +#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL) > +#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL) > +#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL) > +#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL) > +#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL) > +#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL) > +#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL) > +#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL) > +#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL) > +#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL) > +#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL) > +#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL) > +#define PCIE3_INT_MASK_INT_28 (0x37616068UL) > +#define PCIE3_INT_MASK_INT_29 (0x406650feUL) > +#define PCIE3_INT_MASK_INT_3 (0xc136d863UL) > +#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL) > +#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL) > +#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL) > +#define PCIE3_INT_MASK_INT_5 (0x28557d56UL) > +#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL) > +#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL) > +#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL) > +#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL) > +#define PCIE3_INT_MASK_PORT (0xb5f4b407UL) > +#define PCIE3_INT_MASK_PPS (0x914c78c7UL) > +#define PCIE3_INT_MASK_QSPI (0x4944872dUL) > +#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL) > +#define PCIE3_INT_MASK_SPIS (0x8769a19dUL) > +#define PCIE3_INT_MASK_STA (0x4df72d2UL) > +#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL) > +#define PCIE3_LAT_CTRL (0x5c509767UL) > +#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL) > +#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL) > +#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL) > +#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL) > +#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL) > +#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL) > +#define PCIE3_LAT_MAX (0x316931d1UL) > +#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL) > +#define PCIE3_LAT_RAMADR (0x745612a7UL) > +#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL) > +#define PCIE3_LAT_RAMDATA (0xfc506b8dUL) > +#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL) > +#define PCIE3_LINK_STATUS (0xab303a44UL) > +#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL) > +#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL) > +#define PCIE3_MARKADR_LSB (0xbf66115UL) > +#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL) > +#define PCIE3_MARKADR_MSB (0xa340b22UL) > +#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL) > +#define PCIE3_PB_INTERVAL (0x6d0029bfUL) > +#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL) > +#define PCIE3_PB_MAX_RD (0x14d4cfd0UL) > +#define PCIE3_PB_MAX_RD_PB (0xafae2778UL) > +#define PCIE3_PB_MAX_WR (0x9d778ec4UL) > +#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL) > +#define PCIE3_PCIE_CTRL (0x6a657a79UL) > +#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL) > +#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL) > +#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL) > +#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL) > +#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL) > +#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL) > +#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL) > +#define PCIE3_PCI_TEST0 (0x9035b95dUL) > +#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL) > +#define PCIE3_PCI_TEST1 (0xe73289cbUL) > +#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL) > +#define PCIE3_PCI_TEST2 (0x7e3bd871UL) > +#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL) > +#define PCIE3_PCI_TEST3 (0x93ce8e7UL) > +#define PCIE3_PCI_TEST3_DATA (0x777d7216UL) > +#define PCIE3_PROD_ID_EX (0x8611a98cUL) > +#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL) > +#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL) > +#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL) > +#define PCIE3_PROD_ID_LSB (0x427df3d7UL) > +#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL) > +#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL) > +#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL) > +#define PCIE3_PROD_ID_MSB (0x43bf99e0UL) > +#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL) > +#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL) > +#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL) > +#define PCIE3_RESET_CTRL (0xcc9a6c8bUL) > +#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL) > +#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL) > +#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL) > +#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL) > +#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL) > +#define PCIE3_SAMPLE_TIME (0x6c2ab747UL) > +#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL) > +#define PCIE3_STATUS (0x48654731UL) > +#define PCIE3_STATUS_RD_ERR (0x153789c6UL) > +#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL) > +#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL) > +#define PCIE3_STATUS0 (0xa54dba5cUL) > +#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL) > +#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL) > +#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL) > +#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL) > +#define PCIE3_STATUS0_UR_FMT (0x5724146cUL) > +#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL) > +#define PCIE3_STATUS0_UR_REG (0x6cd416UL) > +#define PCIE3_STAT_CTRL (0xdef3e1d7UL) > +#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL) > +#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL) > +#define PCIE3_STAT_REFCLK (0xa4423dd2UL) > +#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL) > +#define PCIE3_STAT_RQ_RDY (0x3ab72682UL) > +#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL) > +#define PCIE3_STAT_RQ_VLD (0x9661688fUL) > +#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL) > +#define PCIE3_STAT_RX (0xf2a8e7a1UL) > +#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL) > +#define PCIE3_STAT_TX (0xa4f24027UL) > +#define PCIE3_STAT_TX_COUNTER (0x80908563UL) > +#define PCIE3_TEST0 (0xa0e404f1UL) > +#define PCIE3_TEST0_DATA (0xf82b8d9cUL) > +#define PCIE3_TEST1 (0xd7e33467UL) > +#define PCIE3_TEST1_DATA (0x33775e39UL) > +#define PCIE3_TEST2_DATA (0x7151e5e8UL) > +#define PCIE3_TEST3_DATA (0xba0d364dUL) > +#define PCIE3_UUID0 (0x96ee4e29UL) > +#define PCIE3_UUID0_UUID0 (0x459d36b3UL) > +#define PCIE3_UUID1 (0xe1e97ebfUL) > +#define PCIE3_UUID1_UUID1 (0x94ed0d91UL) > +#define PCIE3_UUID2 (0x78e02f05UL) > +#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL) > +#define PCIE3_UUID3 (0xfe71f93UL) > +#define PCIE3_UUID3_UUID3 (0xed7c7d94UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCIE3_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > new file mode 100644 > index 0000000000..34c10c3bea > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > @@ -0,0 +1,19 @@ > +/* > + * nthw_fpga_reg_defs_pcm_nt400dxx.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_ > +#define _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_ > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h > new file mode 100644 > index 0000000000..a3447de224 > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h > @@ -0,0 +1,19 @@ > +/* > + * nthw_fpga_reg_defs_pcm_nt50b01_01.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_ > +#define _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_ > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h > new file mode 100644 > index 0000000000..61efcee4e8 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h > @@ -0,0 +1,92 @@ > +/* > + * nthw_fpga_reg_defs_pcs.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCS_ > +#define _NTHW_FPGA_REG_DEFS_PCS_ > + > +/* PCS */ > +#define NTHW_MOD_PCS (0x8286adcaUL) > +#define PCS_BER_COUNT (0x2e91033bUL) > +#define PCS_BER_COUNT_CNT (0x8069b483UL) > +#define PCS_BIP_COUNT (0xeea1075dUL) > +#define PCS_BIP_COUNT_CNT (0xdd0f40c3UL) > +#define PCS_BLOCK_LOCK (0xcca988f2UL) > +#define PCS_BLOCK_LOCK_LOCK (0x8372ac9aUL) > +#define PCS_BLOCK_LOCK_LATCH (0x4b4db873UL) > +#define PCS_BLOCK_LOCK_LATCH_LATCH_LOCK (0x3e50cbe6UL) > +#define PCS_BLOCK_LOCK_ST (0x8f218598UL) > +#define PCS_BLOCK_LOCK_ST_LATCH_STATE (0xc29c506eUL) > +#define PCS_DDR3_STATUS (0xe0963286UL) > +#define PCS_DDR3_STATUS_CALIB_DONE (0x9a8acba0UL) > +#define PCS_DRP_CONFIG (0x7a62f621UL) > +#define PCS_DRP_CONFIG_DRP_ADR (0x77a5e19eUL) > +#define PCS_DRP_CONFIG_DRP_DI (0xae7df08dUL) > +#define PCS_DRP_CONFIG_DRP_EN (0x2902546fUL) > +#define PCS_DRP_CONFIG_DRP_WREN (0x3cfccbafUL) > +#define PCS_DRP_DATA (0x1d57f9a0UL) > +#define PCS_DRP_DATA_DRP_DO (0x5719fe67UL) > +#define PCS_DRP_DATA_DRP_RDY (0xe86bedd1UL) > +#define PCS_FSM_DONE (0xfb93f7e4UL) > +#define PCS_FSM_DONE_RX_RST_DONE (0x57e501cbUL) > +#define PCS_FSM_DONE_TX_RST_DONE (0xbf50cb88UL) > +#define PCS_GTH_CONFIG (0x4d111e36UL) > +#define PCS_GTH_CONFIG_EYE_SCAN_RST (0xf26521beUL) > +#define PCS_GTH_CONFIG_EYE_SCAN_TRIG (0xcd5499e3UL) > +#define PCS_GTH_CONFIG_GT_LOOP (0x8f0a29e8UL) > +#define PCS_GTH_CONFIG_GT_LPM_EN (0xca43244fUL) > +#define PCS_GTH_CONFIG_GT_MRST (0xc252e7eaUL) > +#define PCS_GTH_CONFIG_GT_RX_RST (0xd0dd4c8fUL) > +#define PCS_GTH_CONFIG_GT_SOFT_RST (0xf4291740UL) > +#define PCS_GTH_CONFIG_GT_TX_RST (0x684af92UL) > +#define PCS_GTH_CONFIG_RX_MONITOR_SEL (0xdb170715UL) > +#define PCS_GTH_CONFIG_RX_PCS_RST (0x63f7aa78UL) > +#define PCS_GTH_CONFIG_RX_USER_RDY (0x25431f5fUL) > +#define PCS_GTH_CONFIG_TX_PCS_RST (0x6ee9da3fUL) > +#define PCS_GTH_CONFIG_TX_USER_RDYU (0xddcfe06cUL) > +#define PCS_GTH_CONTROL (0x40253f3cUL) > +#define PCS_GTH_CONTROL_CPLL_LOCK (0xa7d1c749UL) > +#define PCS_GTH_CONTROL_CPLL_REFCLK_LOST (0x5d089cc9UL) > +#define PCS_GTH_CONTROL_RX_BUF_RST (0x44d16a8eUL) > +#define PCS_GTH_TX_TUNING (0x712f49ceUL) > +#define PCS_GTH_TX_TUNING_DIFF_CTRL (0x28d64209UL) > +#define PCS_GTH_TX_TUNING_POST_CURSOR (0x1baff955UL) > +#define PCS_GTH_TX_TUNING_PRE_CURSOR (0xc6ba5499UL) > +#define PCS_LANE_LOCK (0xfe988167UL) > +#define PCS_LANE_LOCK_LOCK (0x2f4590a6UL) > +#define PCS_LANE_LOCK_LATCH (0x648ef3c8UL) > +#define PCS_LANE_LOCK_LATCH_LATCH_LOCK (0x85bc8101UL) > +#define PCS_LANE_LOCK_ST (0xf4e544c2UL) > +#define PCS_LANE_LOCK_ST_LATCH_STATE (0x7755e260UL) > +#define PCS_LANE_MAPPING (0xabb9e1caUL) > +#define PCS_LANE_MAPPING_LANE (0x3a1fc704UL) > +#define PCS_LANE_OFFSET (0xbebd9e39UL) > +#define PCS_LANE_OFFSET_DIFF (0xac1cb16eUL) > +#define PCS_PCS_CONFIG (0x61138662UL) > +#define PCS_PCS_CONFIG_BER_RST (0x1ed2e4bfUL) > +#define PCS_PCS_CONFIG_BIP_RST (0x13d077a4UL) > +#define PCS_PCS_CONFIG_LANE_ADDR (0xc48ed818UL) > +#define PCS_PCS_CONFIG_LANE_BLOCK_CLR (0x6b249b8UL) > +#define PCS_PCS_CONFIG_TIME_OFFSET_RX (0xc19c631dUL) > +#define PCS_PCS_CONFIG_TXRX_LOOP (0x5c917a55UL) > +#define PCS_PCS_STATUS (0xce99cc02UL) > +#define PCS_PCS_STATUS_ALIGN (0x5376e136UL) > +#define PCS_PCS_STATUS_DELAY_ERR (0x3c8d9a55UL) > +#define PCS_PCS_STATUS_FIFO_DELAY (0x4e88e0e6UL) > +#define PCS_PCS_STATUS_HI_BER (0xe72cf1f6UL) > +#define PCS_POLARITY (0x206611d1UL) > +#define PCS_POLARITY_RX_POL (0xcfec2b60UL) > +#define PCS_POLARITY_TX_POL (0x19b5c87dUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h > new file mode 100644 > index 0000000000..7c5b076eff > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h > @@ -0,0 +1,90 @@ > +/* > + * nthw_fpga_reg_defs_pcs100.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PCS100_ > +#define _NTHW_FPGA_REG_DEFS_PCS100_ > + > +/* PCS100 */ > +#define NTHW_MOD_PCS100 (0xa03da74fUL) > +#define PCS100_BER_COUNT (0x682da9a4UL) > +#define PCS100_BER_COUNT_CNT (0x666a98d6UL) > +#define PCS100_BIP_COUNT (0xa81dadc2UL) > +#define PCS100_BIP_COUNT_CNT (0x3b0c6c96UL) > +#define PCS100_BLOCK_LOCK (0xac5fba8dUL) > +#define PCS100_BLOCK_LOCK_LOCK (0x76668f6bUL) > +#define PCS100_BLOCK_LOCK_LATCH (0x81026edaUL) > +#define PCS100_BLOCK_LOCK_LATCH_LATCH_LOCK (0xc22270cUL) > +#define PCS100_BLOCK_LOCK_ST (0x6922a9cdUL) > +#define PCS100_BLOCK_LOCK_ST_LATCH_STATE (0x48d92300UL) > +#define PCS100_DDR3_STATUS (0x204ca819UL) > +#define PCS100_DDR3_STATUS_CALIB_DONE (0xfd635a82UL) > +#define PCS100_DRP_CONFIG (0x1a94c45eUL) > +#define PCS100_DRP_CONFIG_DRP_ADR (0x67d05b90UL) > +#define PCS100_DRP_CONFIG_DRP_DI (0x1bda417UL) > +#define PCS100_DRP_CONFIG_DRP_EN (0x86c200f5UL) > +#define PCS100_DRP_CONFIG_DRP_WREN (0xdb549312UL) > +#define PCS100_DRP_DATA (0xc8431f0fUL) > +#define PCS100_DRP_DATA_DRP_DO (0xa20ddd96UL) > +#define PCS100_DRP_DATA_DRP_RDY (0x22243b78UL) > +#define PCS100_FSM_DONE (0x2e87114bUL) > +#define PCS100_FSM_DONE_RX_RST_DONE (0xe2d266a2UL) > +#define PCS100_FSM_DONE_TX_RST_DONE (0xa67ace1UL) > +#define PCS100_GTH_CONFIG (0x2de72c49UL) > +#define PCS100_GTH_CONFIG_EYE_SCAN_RST (0x276289cbUL) > +#define PCS100_GTH_CONFIG_EYE_SCAN_TRIG (0xedee1bf8UL) > +#define PCS100_GTH_CONFIG_GT_LOOP (0x9f7f93e6UL) > +#define PCS100_GTH_CONFIG_GT_MRST (0xd2275de4UL) > +#define PCS100_GTH_CONFIG_GT_RX_RST (0x65ea2be6UL) > +#define PCS100_GTH_CONFIG_GT_SOFT_RST (0x93c08662UL) > +#define PCS100_GTH_CONFIG_GT_TX_RST (0xb3b3c8fbUL) > +#define PCS100_GTH_CONFIG_RX_MONITOR_SEL (0x5152747bUL) > +#define PCS100_GTH_CONFIG_RX_PCS_RST (0x572c44e3UL) > +#define PCS100_GTH_CONFIG_RX_USER_RDY (0x42aa8e7dUL) > +#define PCS100_GTH_CONFIG_TX_PCS_RST (0x5a3234a4UL) > +#define PCS100_GTH_CONFIG_TX_USER_RDYU (0x8c84819UL) > +#define PCS100_GTH_CONTROL (0x80ffa5a3UL) > +#define PCS100_GTH_CONTROL_CPLL_LOCK (0x930a29d2UL) > +#define PCS100_GTH_CONTROL_CPLL_REFCLK_LOST (0x1de5e543UL) > +#define PCS100_GTH_CONTROL_QPLL_LOCK (0x113c4325UL) > +#define PCS100_GTH_CONTROL_QPLL_REFCLK_LOST (0x7c62febeUL) > +#define PCS100_GTH_CONTROL_RX_BUF_RST (0x2338fbacUL) > +#define PCS100_GTH_TX_TUNING (0x972c659bUL) > +#define PCS100_GTH_TX_TUNING_DIFF_CTRL (0xfdd1ea7cUL) > +#define PCS100_GTH_TX_TUNING_POST_CURSOR (0x91ea8a3bUL) > +#define PCS100_GTH_TX_TUNING_PRE_CURSOR (0xe600d682UL) > +#define PCS100_LANE_LOCK (0xb8242bf8UL) > +#define PCS100_LANE_LOCK_LOCK (0x34a236f1UL) > +#define PCS100_LANE_LOCK_LATCH (0x919ad039UL) > +#define PCS100_LANE_LOCK_LATCH_LATCH_LOCK (0x2f3c882dUL) > +#define PCS100_LANE_LOCK_ST (0x9495108dUL) > +#define PCS100_LANE_LOCK_ST_LATCH_STATE (0x57ef607bUL) > +#define PCS100_LANE_MAPPING (0xcbc9b585UL) > +#define PCS100_LANE_MAPPING_LANE (0x95df939eUL) > +#define PCS100_LANE_OFFSET (0x7e6704a6UL) > +#define PCS100_LANE_OFFSET_DIFF (0x665367c7UL) > +#define PCS100_PCS_CONFIG (0x1e5b41dUL) > +#define PCS100_PCS_CONFIG_BER_RST (0xea75eb1UL) > +#define PCS100_PCS_CONFIG_BIP_RST (0x3a5cdaaUL) > +#define PCS100_PCS_CONFIG_LANE_ADDR (0x71b9bf71UL) > +#define PCS100_PCS_CONFIG_LANE_BLOCK_CLR (0x8cf73ad6UL) > +#define PCS100_PCS_CONFIG_TIME_OFFSET_RX (0x4bd91073UL) > +#define PCS100_PCS_CONFIG_TXRX_LOOP (0xe9a61d3cUL) > +#define PCS100_PCS_STATUS (0xae6ffe7dUL) > +#define PCS100_PCS_STATUS_ALIGN (0x9939379fUL) > +#define PCS100_PCS_STATUS_DELAY_ERR (0x89bafd3cUL) > +#define PCS100_PCS_STATUS_FIFO_DELAY (0x7a530e7dUL) > +#define PCS100_PCS_STATUS_HI_BER (0x48eca56cUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PCS100_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h > new file mode 100644 > index 0000000000..03d7c89dda > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h > @@ -0,0 +1,47 @@ > +/* > + * nthw_fpga_reg_defs_pdb.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PDB_ > +#define _NTHW_FPGA_REG_DEFS_PDB_ > + > +/* PDB */ > +#define NTHW_MOD_PDB (0xa7771bffUL) > +#define PDB_CONFIG (0xf73771edUL) > +#define PDB_CONFIG_PORT_OFS (0xb5b30335UL) > +#define PDB_CONFIG_TS_FORMAT (0x7013d8aUL) > +#define PDB_RCP_CTRL (0x28ac2b3aUL) > +#define PDB_RCP_CTRL_ADR (0x9d08b0e4UL) > +#define PDB_RCP_CTRL_CNT (0x8d002935UL) > +#define PDB_RCP_DATA (0x877da923UL) > +#define PDB_RCP_DATA_ALIGN (0xe802afb8UL) > +#define PDB_RCP_DATA_CRC_OVERWRITE (0x4847dc0aUL) > +#define PDB_RCP_DATA_DESCRIPTOR (0x46cb76faUL) > +#define PDB_RCP_DATA_DESC_LEN (0xf467e85bUL) > +#define PDB_RCP_DATA_DUPLICATE_BIT (0xaeb59507UL) > +#define PDB_RCP_DATA_DUPLICATE_EN (0xbab03efeUL) > +#define PDB_RCP_DATA_IP_PROT_TNL (0xec892325UL) > +#define PDB_RCP_DATA_OFS0_DYN (0xcef3786aUL) > +#define PDB_RCP_DATA_OFS0_REL (0xde219bd9UL) > +#define PDB_RCP_DATA_OFS1_DYN (0xf39351daUL) > +#define PDB_RCP_DATA_OFS1_REL (0xe341b269UL) > +#define PDB_RCP_DATA_OFS2_DYN (0xb4332b0aUL) > +#define PDB_RCP_DATA_OFS2_REL (0xa4e1c8b9UL) > +#define PDB_RCP_DATA_PCAP_KEEP_FCS (0x90bc735eUL) > +#define PDB_RCP_DATA_PPC_HSH (0xac10e9f8UL) > +#define PDB_RCP_DATA_TX_IGNORE (0x14c556dcUL) > +#define PDB_RCP_DATA_TX_NOW (0x479cb22cUL) > +#define PDB_RCP_DATA_TX_PORT (0x412a5ed8UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PDB_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h > new file mode 100644 > index 0000000000..8c48d5c2e5 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h > @@ -0,0 +1,48 @@ > +/* > + * nthw_fpga_reg_defs_pdi.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PDI_ > +#define _NTHW_FPGA_REG_DEFS_PDI_ > + > +/* PDI */ > +#define NTHW_MOD_PDI (0x30a5c277UL) > +#define PDI_CR (0x9d6d02a8UL) > +#define PDI_CR_EN (0x7a6160dUL) > +#define PDI_CR_PARITY (0xaed85250UL) > +#define PDI_CR_RST (0x26b77922UL) > +#define PDI_CR_RXRST (0xe1aedb39UL) > +#define PDI_CR_STOP (0x78eaf29eUL) > +#define PDI_CR_TXRST (0x6eee2e99UL) > +#define PDI_DRR (0x8ab88f08UL) > +#define PDI_DRR_DRR (0x157e17dfUL) > +#define PDI_DTR (0xdce2288eUL) > +#define PDI_DTR_DTR (0x957d5344UL) > +#define PDI_PRE (0x12440163UL) > +#define PDI_PRE_PRE (0xccd36afbUL) > +#define PDI_SR (0xd7af10f9UL) > +#define PDI_SR_DISABLE_BUSY (0xd8936666UL) > +#define PDI_SR_DONE (0xb64f984dUL) > +#define PDI_SR_ENABLE_BUSY (0xee39b4e3UL) > +#define PDI_SR_FRAME_ERR (0x7c7b177dUL) > +#define PDI_SR_OVERRUN_ERR (0x4093d29dUL) > +#define PDI_SR_PARITY_ERR (0xa12e1293UL) > +#define PDI_SR_RXLVL (0xe5b6087bUL) > +#define PDI_SR_RX_BUSY (0xeb248de4UL) > +#define PDI_SR_TXLVL (0x6af6fddbUL) > +#define PDI_SR_TX_BUSY (0x88f4b8deUL) > +#define PDI_SRR (0x93d13afdUL) > +#define PDI_SRR_RST (0x5fd4fe29UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PDI_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h > new file mode 100644 > index 0000000000..a2fbb01da8 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h > @@ -0,0 +1,196 @@ > +/* > + * nthw_fpga_reg_defs_phy_tile.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PHY_TILE_ > +#define _NTHW_FPGA_REG_DEFS_PHY_TILE_ > + > +/* PHY_TILE */ > +#define NTHW_MOD_PHY_TILE (0x4e0aef6eUL) > +#define PHY_TILE_DR_CFG_STATUS (0x252aff33UL) > +#define PHY_TILE_DR_CFG_STATUS_CURR_PROFILE_ID (0x98db7e13UL) > +#define PHY_TILE_DR_CFG_STATUS_ERROR (0x594c35e7UL) > +#define PHY_TILE_DR_CFG_STATUS_IN_PROGRESS (0x62cdc29fUL) > +#define PHY_TILE_DYN_RECONFIG_BASE (0xda7abd93UL) > +#define PHY_TILE_DYN_RECONFIG_BASE_BUSY (0x3b97f6c6UL) > +#define PHY_TILE_DYN_RECONFIG_BASE_CMD (0xf6b609f6UL) > +#define PHY_TILE_DYN_RECONFIG_BASE_PTR (0x87020896UL) > +#define PHY_TILE_DYN_RECONFIG_DATA (0xb73db091UL) > +#define PHY_TILE_DYN_RECONFIG_DATA_DATA (0x74d2a935UL) > +#define PHY_TILE_LINK_SUMMARY_0 (0x2e6c2bb2UL) > +#define PHY_TILE_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT > (0x658fa4f2UL) > +#define PHY_TILE_LINK_SUMMARY_0_LH_REMOTE_FAULT (0x12c794faUL) > +#define PHY_TILE_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE > (0x99e0ad8bUL) > +#define PHY_TILE_LINK_SUMMARY_0_LINK_DOWN_CNT (0x7c6a63a9UL) > +#define PHY_TILE_LINK_SUMMARY_0_LL_PHY_LINK_STATE (0x694563dcUL) > +#define PHY_TILE_LINK_SUMMARY_0_LL_RX_AM_LOCK (0xc958731bUL) > +#define PHY_TILE_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (0x1ae5c634UL) > +#define PHY_TILE_LINK_SUMMARY_0_NT_PHY_LINK_STATE (0x284d52caUL) > +#define PHY_TILE_LINK_SUMMARY_1 (0x596b1b24UL) > +#define PHY_TILE_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT > (0xc00434fcUL) > +#define PHY_TILE_LINK_SUMMARY_1_LH_REMOTE_FAULT (0x95615fb9UL) > +#define PHY_TILE_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE > (0xf76cb6caUL) > +#define PHY_TILE_LINK_SUMMARY_1_LINK_DOWN_CNT (0xc591b841UL) > +#define PHY_TILE_LINK_SUMMARY_1_LL_PHY_LINK_STATE (0xbea7e384UL) > +#define PHY_TILE_LINK_SUMMARY_1_LL_RX_AM_LOCK (0x70a3a8f3UL) > +#define PHY_TILE_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (0xf5b770d5UL) > +#define PHY_TILE_LINK_SUMMARY_1_NT_PHY_LINK_STATE (0xffafd292UL) > +#define PHY_TILE_PORT_0_ETH_0_BASE (0x337c4712UL) > +#define PHY_TILE_PORT_0_ETH_0_BASE_BUSY (0xd5fbad30UL) > +#define PHY_TILE_PORT_0_ETH_0_BASE_CMD (0x948cd3f4UL) > +#define PHY_TILE_PORT_0_ETH_0_BASE_PTR (0xe538d294UL) > +#define PHY_TILE_PORT_0_ETH_0_DATA (0x5e3b4a10UL) > +#define PHY_TILE_PORT_0_ETH_0_DATA_DATA (0x9abef2c3UL) > +#define PHY_TILE_PORT_0_ETH_1_BASE (0xf82094b7UL) > +#define PHY_TILE_PORT_0_ETH_1_BASE_BUSY (0x147572f0UL) > +#define PHY_TILE_PORT_0_ETH_1_BASE_CMD (0x7b4eb8caUL) > +#define PHY_TILE_PORT_0_ETH_1_BASE_PTR (0xafab9aaUL) > +#define PHY_TILE_PORT_0_ETH_1_DATA (0x956799b5UL) > +#define PHY_TILE_PORT_0_ETH_1_DATA_DATA (0x5b302d03UL) > +#define PHY_TILE_PORT_0_ETH_2_BASE (0x7eb4e619UL) > +#define PHY_TILE_PORT_0_ETH_2_BASE_BUSY (0x8d9714f1UL) > +#define PHY_TILE_PORT_0_ETH_2_BASE_CMD (0x907903c9UL) > +#define PHY_TILE_PORT_0_ETH_2_BASE_PTR (0xe1cd02a9UL) > +#define PHY_TILE_PORT_0_ETH_2_DATA (0x13f3eb1bUL) > +#define PHY_TILE_PORT_0_ETH_2_DATA_DATA (0xc2d24b02UL) > +#define PHY_TILE_PORT_0_ETH_3_BASE (0xb5e835bcUL) > +#define PHY_TILE_PORT_0_ETH_3_BASE_BUSY (0x4c19cb31UL) > +#define PHY_TILE_PORT_0_ETH_3_BASE_CMD (0x7fbb68f7UL) > +#define PHY_TILE_PORT_0_ETH_3_BASE_PTR (0xe0f6997UL) > +#define PHY_TILE_PORT_0_ETH_3_DATA (0xd8af38beUL) > +#define PHY_TILE_PORT_0_ETH_3_DATA_DATA (0x35c94c2UL) > +#define PHY_TILE_PORT_0_XCVR_0_BASE (0x758a7765UL) > +#define PHY_TILE_PORT_0_XCVR_0_BASE_BUSY (0x79488eafUL) > +#define PHY_TILE_PORT_0_XCVR_0_BASE_CMD (0x9b560cdfUL) > +#define PHY_TILE_PORT_0_XCVR_0_BASE_PTR (0xeae20dbfUL) > +#define PHY_TILE_PORT_0_XCVR_0_DATA (0x18cd7a67UL) > +#define PHY_TILE_PORT_0_XCVR_0_DATA_DATA (0x360dd15cUL) > +#define PHY_TILE_PORT_0_XCVR_1_BASE (0xbed6a4c0UL) > +#define PHY_TILE_PORT_0_XCVR_1_BASE_BUSY (0xb8c6516fUL) > +#define PHY_TILE_PORT_0_XCVR_1_BASE_CMD (0x749467e1UL) > +#define PHY_TILE_PORT_0_XCVR_1_BASE_PTR (0x5206681UL) > +#define PHY_TILE_PORT_0_XCVR_1_DATA (0xd391a9c2UL) > +#define PHY_TILE_PORT_0_XCVR_1_DATA_DATA (0xf7830e9cUL) > +#define PHY_TILE_PORT_0_XCVR_2_BASE (0x3842d66eUL) > +#define PHY_TILE_PORT_0_XCVR_2_BASE_BUSY (0x2124376eUL) > +#define PHY_TILE_PORT_0_XCVR_2_BASE_CMD (0x9fa3dce2UL) > +#define PHY_TILE_PORT_0_XCVR_2_BASE_PTR (0xee17dd82UL) > +#define PHY_TILE_PORT_0_XCVR_2_DATA (0x5505db6cUL) > +#define PHY_TILE_PORT_0_XCVR_2_DATA_DATA (0x6e61689dUL) > +#define PHY_TILE_PORT_0_XCVR_3_BASE (0xf31e05cbUL) > +#define PHY_TILE_PORT_0_XCVR_3_BASE_BUSY (0xe0aae8aeUL) > +#define PHY_TILE_PORT_0_XCVR_3_BASE_CMD (0x7061b7dcUL) > +#define PHY_TILE_PORT_0_XCVR_3_BASE_PTR (0x1d5b6bcUL) > +#define PHY_TILE_PORT_0_XCVR_3_DATA (0x9e5908c9UL) > +#define PHY_TILE_PORT_0_XCVR_3_DATA_DATA (0xafefb75dUL) > +#define PHY_TILE_PORT_1_ETH_0_BASE (0xa8d90b7dUL) > +#define PHY_TILE_PORT_1_ETH_0_BASE_BUSY (0x525d6673UL) > +#define PHY_TILE_PORT_1_ETH_0_BASE_CMD (0x3ae44265UL) > +#define PHY_TILE_PORT_1_ETH_0_BASE_PTR (0x4b504305UL) > +#define PHY_TILE_PORT_1_ETH_0_DATA (0xc59e067fUL) > +#define PHY_TILE_PORT_1_ETH_0_DATA_DATA (0x1d183980UL) > +#define PHY_TILE_PORT_1_ETH_1_BASE (0x6385d8d8UL) > +#define PHY_TILE_PORT_1_ETH_1_BASE_BUSY (0x93d3b9b3UL) > +#define PHY_TILE_PORT_1_ETH_1_BASE_CMD (0xd526295bUL) > +#define PHY_TILE_PORT_1_ETH_1_BASE_PTR (0xa492283bUL) > +#define PHY_TILE_PORT_1_ETH_1_DATA (0xec2d5daUL) > +#define PHY_TILE_PORT_1_ETH_1_DATA_DATA (0xdc96e640UL) > +#define PHY_TILE_PORT_1_ETH_2_BASE (0xe511aa76UL) > +#define PHY_TILE_PORT_1_ETH_2_BASE_BUSY (0xa31dfb2UL) > +#define PHY_TILE_PORT_1_ETH_2_BASE_CMD (0x3e119258UL) > +#define PHY_TILE_PORT_1_ETH_2_BASE_PTR (0x4fa59338UL) > +#define PHY_TILE_PORT_1_ETH_2_DATA (0x8856a774UL) > +#define PHY_TILE_PORT_1_ETH_2_DATA_DATA (0x45748041UL) > +#define PHY_TILE_PORT_1_ETH_3_BASE (0x2e4d79d3UL) > +#define PHY_TILE_PORT_1_ETH_3_BASE_BUSY (0xcbbf0072UL) > +#define PHY_TILE_PORT_1_ETH_3_BASE_CMD (0xd1d3f966UL) > +#define PHY_TILE_PORT_1_ETH_3_BASE_PTR (0xa067f806UL) > +#define PHY_TILE_PORT_1_ETH_3_DATA (0x430a74d1UL) > +#define PHY_TILE_PORT_1_ETH_3_DATA_DATA (0x84fa5f81UL) > +#define PHY_TILE_PORT_1_XCVR_0_BASE (0xa81caee0UL) > +#define PHY_TILE_PORT_1_XCVR_0_BASE_BUSY (0x961a384eUL) > +#define PHY_TILE_PORT_1_XCVR_0_BASE_CMD (0x1cf0c79cUL) > +#define PHY_TILE_PORT_1_XCVR_0_BASE_PTR (0x6d44c6fcUL) > +#define PHY_TILE_PORT_1_XCVR_0_DATA (0xc55ba3e2UL) > +#define PHY_TILE_PORT_1_XCVR_0_DATA_DATA (0xd95f67bdUL) > +#define PHY_TILE_PORT_1_XCVR_1_BASE (0x63407d45UL) > +#define PHY_TILE_PORT_1_XCVR_1_BASE_BUSY (0x5794e78eUL) > +#define PHY_TILE_PORT_1_XCVR_1_BASE_CMD (0xf332aca2UL) > +#define PHY_TILE_PORT_1_XCVR_1_BASE_PTR (0x8286adc2UL) > +#define PHY_TILE_PORT_1_XCVR_1_DATA (0xe077047UL) > +#define PHY_TILE_PORT_1_XCVR_1_DATA_DATA (0x18d1b87dUL) > +#define PHY_TILE_PORT_1_XCVR_2_BASE (0xe5d40febUL) > +#define PHY_TILE_PORT_1_XCVR_2_BASE_BUSY (0xce76818fUL) > +#define PHY_TILE_PORT_1_XCVR_2_BASE_CMD (0x180517a1UL) > +#define PHY_TILE_PORT_1_XCVR_2_BASE_PTR (0x69b116c1UL) > +#define PHY_TILE_PORT_1_XCVR_2_DATA (0x889302e9UL) > +#define PHY_TILE_PORT_1_XCVR_2_DATA_DATA (0x8133de7cUL) > +#define PHY_TILE_PORT_1_XCVR_3_BASE (0x2e88dc4eUL) > +#define PHY_TILE_PORT_1_XCVR_3_BASE_BUSY (0xff85e4fUL) > +#define PHY_TILE_PORT_1_XCVR_3_BASE_CMD (0xf7c77c9fUL) > +#define PHY_TILE_PORT_1_XCVR_3_BASE_PTR (0x86737dffUL) > +#define PHY_TILE_PORT_1_XCVR_3_DATA (0x43cfd14cUL) > +#define PHY_TILE_PORT_1_XCVR_3_DATA_DATA (0x40bd01bcUL) > +#define PHY_TILE_PORT_COMP_0 (0xfc048a04UL) > +#define PHY_TILE_PORT_COMP_0_RX_COMPENSATION (0xffba9733UL) > +#define PHY_TILE_PORT_COMP_0_TX_COMPENSATION (0xdd4043c1UL) > +#define PHY_TILE_PORT_COMP_1 (0x8b03ba92UL) > +#define PHY_TILE_PORT_COMP_1_RX_COMPENSATION (0x781c5c70UL) > +#define PHY_TILE_PORT_COMP_1_TX_COMPENSATION (0x5ae68882UL) > +#define PHY_TILE_PORT_CONFIG (0x24e3ab60UL) > +#define PHY_TILE_PORT_CONFIG_DYN_RESET (0x72b5f859UL) > +#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_0 > (0x7e66781UL) > +#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_1 > (0x70e15717UL) > +#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_0 (0x33fd94c2UL) > +#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_1 (0x44faa454UL) > +#define PHY_TILE_PORT_CONFIG_RESET_0 (0xf0e1e1c4UL) > +#define PHY_TILE_PORT_CONFIG_RESET_1 (0x87e6d152UL) > +#define PHY_TILE_PORT_CONFIG_RX_RESET_0 (0x70027edeUL) > +#define PHY_TILE_PORT_CONFIG_RX_RESET_1 (0x7054e48UL) > +#define PHY_TILE_PORT_CONFIG_TX_RESET_0 (0x7d1c0e99UL) > +#define PHY_TILE_PORT_CONFIG_TX_RESET_1 (0xa1b3e0fUL) > +#define PHY_TILE_PORT_STATUS (0x8b69e100UL) > +#define PHY_TILE_PORT_STATUS_RESET_ACK_N_0 (0x812f344UL) > +#define PHY_TILE_PORT_STATUS_RESET_ACK_N_1 (0x7f15c3d2UL) > +#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_0 (0x18c38950UL) > +#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_1 (0x6fc4b9c6UL) > +#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_0 (0x72b847a5UL) > +#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_1 (0x5bf7733UL) > +#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_0 (0x8557733cUL) > +#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_1 (0xf25043aaUL) > +#define PHY_TILE_PORT_STATUS_RX_HI_BER_0 (0xae6e5427UL) > +#define PHY_TILE_PORT_STATUS_RX_HI_BER_1 (0xd96964b1UL) > +#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_0 (0xb7de3d5eUL) > +#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_1 (0xc0d90dc8UL) > +#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_0 > (0x690e7dbcUL) > +#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_1 > (0x1e094d2aUL) > +#define PHY_TILE_PORT_STATUS_RX_PCS_READY_0 (0x4bb3d53cUL) > +#define PHY_TILE_PORT_STATUS_RX_PCS_READY_1 (0x3cb4e5aaUL) > +#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_0 > (0x4a8305e7UL) > +#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_1 > (0x3d843571UL) > +#define PHY_TILE_PORT_STATUS_RX_PTP_READY_0 (0xb74c7368UL) > +#define PHY_TILE_PORT_STATUS_RX_PTP_READY_1 (0xc04b43feUL) > +#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_0 (0x7160c5c7UL) > +#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_1 (0x667f551UL) > +#define PHY_TILE_PORT_STATUS_SYSTEMPLL_LOCK (0x3d44b5b8UL) > +#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_0 (0x9a284858UL) > +#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_1 (0xed2f78ceUL) > +#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_0 (0x9d0d322aUL) > +#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_1 (0xea0a02bcUL) > +#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_0 (0x56587371UL) > +#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_1 (0x215f43e7UL) > +#define PHY_TILE_SCRATCH (0xcd637527UL) > +#define PHY_TILE_SCRATCH_DATA (0x1934d873UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_PHY_TILE_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > new file mode 100644 > index 0000000000..87f255bfea > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > @@ -0,0 +1,19 @@ > +/* > + * nthw_fpga_reg_defs_prm_nt400dxx.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_ > +#define _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_ > + > +#endif /* _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h > new file mode 100644 > index 0000000000..193598092d > --- /dev/null > +++ > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h > @@ -0,0 +1,19 @@ > +/* > + * nthw_fpga_reg_defs_prm_nt50b01_01.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_ > +#define _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_ > + > +#endif /* _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h > new file mode 100644 > index 0000000000..c768109866 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h > @@ -0,0 +1,65 @@ > +/* > + * nthw_fpga_reg_defs_qsl.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_QSL_ > +#define _NTHW_FPGA_REG_DEFS_QSL_ > + > +/* QSL */ > +#define NTHW_MOD_QSL (0x448ed859UL) > +#define QSL_LTX_CTRL (0xd16859aUL) > +#define QSL_LTX_CTRL_ADR (0x56ab4bfeUL) > +#define QSL_LTX_CTRL_CNT (0x46a3d22fUL) > +#define QSL_LTX_DATA (0xa2c70783UL) > +#define QSL_LTX_DATA_LR (0xbd09e686UL) > +#define QSL_LTX_DATA_TSA (0xdc9172f1UL) > +#define QSL_LTX_DATA_TX_PORT (0x4e838100UL) > +#define QSL_QEN_CTRL (0xfe8ed79cUL) > +#define QSL_QEN_CTRL_ADR (0x81d44d48UL) > +#define QSL_QEN_CTRL_CNT (0x91dcd499UL) > +#define QSL_QEN_DATA (0x515f5585UL) > +#define QSL_QEN_DATA_EN (0xa1e5961UL) > +#define QSL_QST_CTRL (0x58cd5f95UL) > +#define QSL_QST_CTRL_ADR (0xf71b52e1UL) > +#define QSL_QST_CTRL_CNT (0xe713cb30UL) > +#define QSL_QST_DATA (0xf71cdd8cUL) > +#define QSL_QST_DATA_EN (0x19406021UL) > +#define QSL_QST_DATA_LRE (0x71626c7eUL) > +#define QSL_QST_DATA_QEN (0xf7cd0143UL) > +#define QSL_QST_DATA_QUEUE (0x70bc6d12UL) > +#define QSL_QST_DATA_TCI (0x3938f18dUL) > +#define QSL_QST_DATA_TX_PORT (0x101a63f0UL) > +#define QSL_QST_DATA_VEN (0xf28217c6UL) > +#define QSL_RCP_CTRL (0x2a0d86aeUL) > +#define QSL_RCP_CTRL_ADR (0x2798e4a0UL) > +#define QSL_RCP_CTRL_CNT (0x37907d71UL) > +#define QSL_RCP_DATA (0x85dc04b7UL) > +#define QSL_RCP_DATA_CAO (0x2b87358eUL) > +#define QSL_RCP_DATA_DISCARD (0x5b3da2b8UL) > +#define QSL_RCP_DATA_DROP (0x30f5b2fbUL) > +#define QSL_RCP_DATA_LR (0x3f2331c2UL) > +#define QSL_RCP_DATA_TBL_HI (0xde81892fUL) > +#define QSL_RCP_DATA_TBL_IDX (0xa8d19ee1UL) > +#define QSL_RCP_DATA_TBL_LO (0x538ee91eUL) > +#define QSL_RCP_DATA_TBL_MSK (0x2ee5f375UL) > +#define QSL_RCP_DATA_TSA (0xada2ddafUL) > +#define QSL_RCP_DATA_VLI (0x6da78f6dUL) > +#define QSL_UNMQ_CTRL (0xe759d3f1UL) > +#define QSL_UNMQ_CTRL_ADR (0xe5833152UL) > +#define QSL_UNMQ_CTRL_CNT (0xf58ba883UL) > +#define QSL_UNMQ_DATA (0x488851e8UL) > +#define QSL_UNMQ_DATA_DEST_QUEUE (0xef8ce959UL) > +#define QSL_UNMQ_DATA_EN (0x36ca8378UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_QSL_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h > new file mode 100644 > index 0000000000..a34df75c14 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h > @@ -0,0 +1,89 @@ > +/* > + * nthw_fpga_reg_defs_qspi.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_QSPI_ > +#define _NTHW_FPGA_REG_DEFS_QSPI_ > + > +/* QSPI */ > +#define NTHW_MOD_QSPI (0x29862c6cUL) > +#define QSPI_CR (0xef84e130UL) > +#define QSPI_CR_CPHA (0x948dc9b4UL) > +#define QSPI_CR_CPOL (0xa57d23ceUL) > +#define QSPI_CR_LOOP (0xfe658b9aUL) > +#define QSPI_CR_LSBF (0xaa231a92UL) > +#define QSPI_CR_MSSAE (0xa5dafdd0UL) > +#define QSPI_CR_MST (0xd32a6268UL) > +#define QSPI_CR_MTI (0xff6d9876UL) > +#define QSPI_CR_RXFIFO_RST (0x66004882UL) > +#define QSPI_CR_SPE (0x840f9f23UL) > +#define QSPI_CR_TXFIFO_RST (0x6b1e38c5UL) > +#define QSPI_DGIE (0xe9a50117UL) > +#define QSPI_DGIE_GIE (0xf5dbca66UL) > +#define QSPI_DRR (0x741e7d9dUL) > +#define QSPI_DRR_DATA_VAL (0xd7977338UL) > +#define QSPI_DTR (0x2244da1bUL) > +#define QSPI_DTR_DATA_VAL (0x3f22b97bUL) > +#define QSPI_IER (0x79456a58UL) > +#define QSPI_IER_CMD_ERR (0x80d9abaUL) > +#define QSPI_IER_CPOL_CPHA_ERR (0x607c3883UL) > +#define QSPI_IER_DRR_FULL (0xbb33732UL) > +#define QSPI_IER_DRR_NEMPTY (0xf947b1acUL) > +#define QSPI_IER_DRR_OR (0x1fe5371bUL) > +#define QSPI_IER_DTR_EMPTY (0x8b2c2a00UL) > +#define QSPI_IER_DTR_UR (0x20883860UL) > +#define QSPI_IER_LOOP_ERR (0xfc3eeec4UL) > +#define QSPI_IER_MODF (0x75955c38UL) > +#define QSPI_IER_MSB_ERR (0xeeae77acUL) > +#define QSPI_IER_SLV_ERR (0xbeaf1133UL) > +#define QSPI_IER_SLV_MODF (0x3f016834UL) > +#define QSPI_IER_SLV_MS (0x14b5e998UL) > +#define QSPI_IER_TXFIFO_HEMPTY (0x4711acf3UL) > +#define QSPI_ISR (0x65dddf8fUL) > +#define QSPI_ISR_CMD_ERR (0x22bd6b15UL) > +#define QSPI_ISR_CPOL_CPHA_ERR (0xd5ca6ff9UL) > +#define QSPI_ISR_DRR_FULL (0x4df039baUL) > +#define QSPI_ISR_DRR_NEMPTY (0xeda5c8abUL) > +#define QSPI_ISR_DRR_OR (0xc03f0ce0UL) > +#define QSPI_ISR_DTR_EMPTY (0x6809621cUL) > +#define QSPI_ISR_DTR_UR (0xff52039bUL) > +#define QSPI_ISR_LOOP_ERR (0xba7de04cUL) > +#define QSPI_ISR_MODF (0x719bf5ccUL) > +#define QSPI_ISR_MSB_ERR (0xc41e8603UL) > +#define QSPI_ISR_SLV_ERR (0x941fe09cUL) > +#define QSPI_ISR_SLV_MODF (0x794266bcUL) > +#define QSPI_ISR_SLV_MS (0xcb6fd263UL) > +#define QSPI_ISR_TXFIFO_HEMPTY (0xf2a7fb89UL) > +#define QSPI_RX_FIFO_OCY (0xd5306ee6UL) > +#define QSPI_RX_FIFO_OCY_OCY_VAL (0x315cad36UL) > +#define QSPI_SR (0xa546f361UL) > +#define QSPI_SR_CMD_ERR (0x224e01f5UL) > +#define QSPI_SR_CPOL_CPHA_ERR (0x84dfa2deUL) > +#define QSPI_SR_LOOP_ERR (0x1a77f15eUL) > +#define QSPI_SR_MODF (0x36271cabUL) > +#define QSPI_SR_MSB_ERR (0xc4edece3UL) > +#define QSPI_SR_RXEMPTY (0xace9ac96UL) > +#define QSPI_SR_RXFULL (0xafa43e79UL) > +#define QSPI_SR_SLVMS (0x50619a67UL) > +#define QSPI_SR_SLV_ERR (0x94ec8a7cUL) > +#define QSPI_SR_TXEMPTY (0xcf3999acUL) > +#define QSPI_SR_TXFULL (0x79fddd64UL) > +#define QSPI_SRR (0x6d77c868UL) > +#define QSPI_SRR_RST (0xc1528c75UL) > +#define QSPI_SSR (0x746cf929UL) > +#define QSPI_SSR_SEL_SLV (0x1e9e863cUL) > +#define QSPI_TX_FIFO_OCY (0x3d85a4a5UL) > +#define QSPI_TX_FIFO_OCY_OCY_VAL (0xac80a625UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_QSPI_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h > new file mode 100644 > index 0000000000..ffff2552fe > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h > @@ -0,0 +1,29 @@ > +/* > + * nthw_fpga_reg_defs_r2drp.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_R2DRP_ > +#define _NTHW_FPGA_REG_DEFS_R2DRP_ > + > +/* R2DRP */ > +#define NTHW_MOD_R2DRP (0x8b673fa6UL) > +#define R2DRP_CTRL (0x6fe03b4eUL) > +#define R2DRP_CTRL_ADR (0xd107f065UL) > +#define R2DRP_CTRL_DATA (0x899f99f3UL) > +#define R2DRP_CTRL_DBG_BUSY (0x96d9901aUL) > +#define R2DRP_CTRL_DONE (0x34418a3bUL) > +#define R2DRP_CTRL_RES (0xa17bec9bUL) > +#define R2DRP_CTRL_WREN (0x1635422aUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_R2DRP_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h > new file mode 100644 > index 0000000000..b4af411b47 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h > @@ -0,0 +1,72 @@ > +/* > + * nthw_fpga_reg_defs_rac.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RAC_ > +#define _NTHW_FPGA_REG_DEFS_RAC_ > + > +/* RAC */ > +#define NTHW_MOD_RAC (0xae830b42UL) > +#define RAC_DBG_CTRL (0x587273e2UL) > +#define RAC_DBG_CTRL_C (0x4fe263UL) > +#define RAC_DBG_DATA (0xf7a3f1fbUL) > +#define RAC_DBG_DATA_D (0x69d9305UL) > +#define RAC_DUMMY0 (0xd8e9ed5bUL) > +#define RAC_DUMMY1 (0xafeeddcdUL) > +#define RAC_DUMMY2 (0x36e78c77UL) > +#define RAC_NDM_REGISTER (0x36b9e7d0UL) > +#define RAC_NDM_REGISTER_NDM (0xf791ef23UL) > +#define RAC_NMB_DATA (0xc0e60c69UL) > +#define RAC_NMB_DATA_NMB_DATA (0x21f71466UL) > +#define RAC_NMB_RD_ADR (0x274e1df2UL) > +#define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL) > +#define RAC_NMB_RD_ADR_RES (0x829c7f2eUL) > +#define RAC_NMB_STATUS (0x2070b64UL) > +#define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL) > +#define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL) > +#define RAC_NMB_WR_ADR (0x9823ee63UL) > +#define RAC_NMB_WR_ADR_ADR (0xcb13936fUL) > +#define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL) > +#define RAC_RAB_BUF_FREE (0x60f7f2d8UL) > +#define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL) > +#define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL) > +#define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL) > +#define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL) > +#define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL) > +#define RAC_RAB_BUF_USED (0x549e5008UL) > +#define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL) > +#define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL) > +#define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL) > +#define RAC_RAB_DMA_IB_HI (0x3adf4e92UL) > +#define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL) > +#define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL) > +#define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL) > +#define RAC_RAB_DMA_IB_RD (0xf443c8f4UL) > +#define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL) > +#define RAC_RAB_DMA_IB_WR (0x7de089e0UL) > +#define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL) > +#define RAC_RAB_DMA_OB_HI (0xb59fbb32UL) > +#define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL) > +#define RAC_RAB_DMA_OB_LO (0x3890db03UL) > +#define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL) > +#define RAC_RAB_DMA_OB_WR (0xf2a07c40UL) > +#define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL) > +#define RAC_RAB_IB_DATA (0xea524b52UL) > +#define RAC_RAB_IB_DATA_D (0x52ecd3c6UL) > +#define RAC_RAB_INIT (0x47d5556eUL) > +#define RAC_RAB_INIT_RAB (0xda582a35UL) > +#define RAC_RAB_OB_DATA (0x89827e68UL) > +#define RAC_RAB_OB_DATA_D (0x21f6aa4cUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RAC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h > new file mode 100644 > index 0000000000..5e5a7e96d1 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h > @@ -0,0 +1,37 @@ > +/* > + * nthw_fpga_reg_defs_rfd.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RFD_ > +#define _NTHW_FPGA_REG_DEFS_RFD_ > + > +/* RFD */ > +#define NTHW_MOD_RFD (0x7fa60826UL) > +#define RFD_CTRL (0x5347930aUL) > +#define RFD_CTRL_CFP (0x38fb2beUL) > +#define RFD_CTRL_ISL (0x2dac8d33UL) > +#define RFD_CTRL_PWMCW (0xebb075fcUL) > +#define RFD_MAX_FRAME_SIZE (0x8369a9a2UL) > +#define RFD_MAX_FRAME_SIZE_MAX (0x647c0b15UL) > +#define RFD_TNL_VLAN (0xb85aa35fUL) > +#define RFD_TNL_VLAN_TPID0 (0xe2dfb0a4UL) > +#define RFD_TNL_VLAN_TPID1 (0x95d88032UL) > +#define RFD_VLAN (0xa954e6d1UL) > +#define RFD_VLAN_TPID0 (0xab4dac41UL) > +#define RFD_VLAN_TPID1 (0xdc4a9cd7UL) > +#define RFD_VXLAN (0xe2207aeaUL) > +#define RFD_VXLAN_DP0 (0xb17ca4d9UL) > +#define RFD_VXLAN_DP1 (0xc67b944fUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RFD_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h > new file mode 100644 > index 0000000000..7857314251 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h > @@ -0,0 +1,35 @@ > +/* > + * nthw_fpga_reg_defs_rmc.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RMC_ > +#define _NTHW_FPGA_REG_DEFS_RMC_ > + > +/* RMC */ > +#define NTHW_MOD_RMC (0x236444eUL) > +#define RMC_CTRL (0x4c45f748UL) > +#define RMC_CTRL_BLOCK_KEEPA (0x5e036c8UL) > +#define RMC_CTRL_BLOCK_MAC_PORT (0x582a6486UL) > +#define RMC_CTRL_BLOCK_RPP_SLICE (0x58c719cUL) > +#define RMC_CTRL_BLOCK_STATT (0xb36d5342UL) > +#define RMC_CTRL_LAG_PHY_ODD_EVEN (0xf4613c9UL) > +#define RMC_DBG (0x578721f2UL) > +#define RMC_DBG_MERGE (0xebfd6f00UL) > +#define RMC_MAC_IF (0x806bb8b0UL) > +#define RMC_MAC_IF_ERR (0xa79e974aUL) > +#define RMC_STATUS (0x3c415d75UL) > +#define RMC_STATUS_DESCR_FIFO_OF (0x7be968baUL) > +#define RMC_STATUS_SF_RAM_OF (0x1832173dUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RMC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h > new file mode 100644 > index 0000000000..a776ac1dfb > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h > @@ -0,0 +1,67 @@ > +/* > + * nthw_fpga_reg_defs_roa.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_ROA_ > +#define _NTHW_FPGA_REG_DEFS_ROA_ > + > +/* ROA */ > +#define NTHW_MOD_ROA (0xde0e47e0UL) > +#define ROA_CONFIG (0xff1838eeUL) > +#define ROA_CONFIG_FWD_CELLBUILDER_PCKS (0xd6e1416dUL) > +#define ROA_CONFIG_FWD_NON_NORMAL_PCKS (0xc5d32d2eUL) > +#define ROA_CONFIG_FWD_NORMAL_PCKS (0x1127f510UL) > +#define ROA_CONFIG_FWD_RECIRCULATE (0x500dc0bcUL) > +#define ROA_CONFIG_FWD_TXPORT0 (0xf5b61631UL) > +#define ROA_CONFIG_FWD_TXPORT1 (0x82b126a7UL) > +#define ROA_IGS (0xffa60f2UL) > +#define ROA_IGS_BYTE (0x4dbd049UL) > +#define ROA_IGS_BYTE_DROP (0x8da204f9UL) > +#define ROA_IGS_PKT (0x68ca2b28UL) > +#define ROA_IGS_PKT_DROP (0xac3b264eUL) > +#define ROA_LAGCFG_CTRL (0xd5c2463cUL) > +#define ROA_LAGCFG_CTRL_ADR (0xc01e7fc3UL) > +#define ROA_LAGCFG_CTRL_CNT (0xd016e612UL) > +#define ROA_LAGCFG_DATA (0x7a13c425UL) > +#define ROA_LAGCFG_DATA_TXPHY_PORT (0xf1a085aUL) > +#define ROA_RCC (0x6652f903UL) > +#define ROA_RCC_BYTE (0xd293dbbcUL) > +#define ROA_RCC_BYTE_DROP (0x739ce234UL) > +#define ROA_RCC_PKT (0xf6623688UL) > +#define ROA_RCC_PKT_DROP (0x46c69dd6UL) > +#define ROA_TUNCFG_CTRL (0x4311f47bUL) > +#define ROA_TUNCFG_CTRL_ADR (0xb37e9594UL) > +#define ROA_TUNCFG_CTRL_CNT (0xa3760c45UL) > +#define ROA_TUNCFG_DATA (0xecc07662UL) > +#define ROA_TUNCFG_DATA_PUSH_TUNNEL (0x2b684608UL) > +#define ROA_TUNCFG_DATA_RECIRCULATE (0xc0947b2fUL) > +#define ROA_TUNCFG_DATA_RECIRC_BYPASS (0xb167919dUL) > +#define ROA_TUNCFG_DATA_RECIRC_PORT (0xa69f21d7UL) > +#define ROA_TUNCFG_DATA_TUN_IPCS_PRECALC (0xf78f25e0UL) > +#define ROA_TUNCFG_DATA_TUN_IPCS_UPD (0xa524f432UL) > +#define ROA_TUNCFG_DATA_TUN_IPTL_PRECALC (0x418432d1UL) > +#define ROA_TUNCFG_DATA_TUN_IPTL_UPD (0x5947c642UL) > +#define ROA_TUNCFG_DATA_TUN_IP_TYPE (0xdcb0763UL) > +#define ROA_TUNCFG_DATA_TUN_LEN (0xf2fad7ffUL) > +#define ROA_TUNCFG_DATA_TUN_TYPE (0xad945573UL) > +#define ROA_TUNCFG_DATA_TUN_VLAN (0xd97b06fbUL) > +#define ROA_TUNCFG_DATA_TUN_VXLAN_UDP_LEN_UPD (0x9b13a7cbUL) > +#define ROA_TUNCFG_DATA_TX_LAG_IX (0x1ed24069UL) > +#define ROA_TUNHDR_CTRL (0xdaff6a2cUL) > +#define ROA_TUNHDR_CTRL_ADR (0x5b07c2f7UL) > +#define ROA_TUNHDR_CTRL_CNT (0x4b0f5b26UL) > +#define ROA_TUNHDR_DATA (0x752ee835UL) > +#define ROA_TUNHDR_DATA_TUNNEL_HDR (0xf2fed211UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_ROA_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h > new file mode 100644 > index 0000000000..90afca44c7 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h > @@ -0,0 +1,30 @@ > +/* > + * nthw_fpga_reg_defs_rpf.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RPF_ > +#define _NTHW_FPGA_REG_DEFS_RPF_ > + > +/* RPF */ > +#define NTHW_MOD_RPF (0x8d30dcddUL) > +#define RPF_CONTROL (0x7a5bdb50UL) > +#define RPF_CONTROL_KEEP_ALIVE_EN (0x80be3ffcUL) > +#define RPF_CONTROL_PEN (0xb23137b8UL) > +#define RPF_CONTROL_RPP_EN (0xdb51f109UL) > +#define RPF_CONTROL_ST_TGL_EN (0x45a6ecfaUL) > +#define RPF_TS_SORT_PRG (0xff1d137eUL) > +#define RPF_TS_SORT_PRG_MATURING_DELAY (0x2a38e127UL) > +#define RPF_TS_SORT_PRG_TS_AT_EOF (0x9f27d433UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RPF_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h > new file mode 100644 > index 0000000000..5346bc673d > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h > @@ -0,0 +1,42 @@ > +/* > + * nthw_fpga_reg_defs_rpl.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RPL_ > +#define _NTHW_FPGA_REG_DEFS_RPL_ > + > +/* RPL */ > +#define NTHW_MOD_RPL (0x6de535c3UL) > +#define RPL_EXT_CTRL (0x4c47804fUL) > +#define RPL_EXT_CTRL_ADR (0xe391ddadUL) > +#define RPL_EXT_CTRL_CNT (0xf399447cUL) > +#define RPL_EXT_DATA (0xe3960256UL) > +#define RPL_EXT_DATA_RPL_PTR (0xa8e4d0d9UL) > +#define RPL_RCP_CTRL (0xc471325fUL) > +#define RPL_RCP_CTRL_ADR (0x1f2d3a2bUL) > +#define RPL_RCP_CTRL_CNT (0xf25a3faUL) > +#define RPL_RCP_DATA (0x6ba0b046UL) > +#define RPL_RCP_DATA_DYN (0xe361554fUL) > +#define RPL_RCP_DATA_ETH_TYPE_WR (0xfc7f05c1UL) > +#define RPL_RCP_DATA_EXT_PRIO (0xcd2ae9d1UL) > +#define RPL_RCP_DATA_LEN (0xb0559aaUL) > +#define RPL_RCP_DATA_OFS (0x4168d8e9UL) > +#define RPL_RCP_DATA_RPL_PTR (0x3000a098UL) > +#define RPL_RPL_CTRL (0xe65376ecUL) > +#define RPL_RPL_CTRL_ADR (0x15abf987UL) > +#define RPL_RPL_CTRL_CNT (0x5a36056UL) > +#define RPL_RPL_DATA (0x4982f4f5UL) > +#define RPL_RPL_DATA_VALUE (0x60951eb4UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RPL_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h > new file mode 100644 > index 0000000000..c8a6efb2b6 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h > @@ -0,0 +1,36 @@ > +/* > + * nthw_fpga_reg_defs_rpp_lr.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RPP_LR_ > +#define _NTHW_FPGA_REG_DEFS_RPP_LR_ > + > +/* RPP_LR */ > +#define NTHW_MOD_RPP_LR (0xba7f945cUL) > +#define RPP_LR_IFR_RCP_CTRL (0xce88594UL) > +#define RPP_LR_IFR_RCP_CTRL_ADR (0x4b4cc068UL) > +#define RPP_LR_IFR_RCP_CTRL_CNT (0x5b4459b9UL) > +#define RPP_LR_IFR_RCP_DATA (0xa339078dUL) > +#define RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP (0xee1d681fUL) > +#define RPP_LR_IFR_RCP_DATA_IPV4_EN (0xfe386131UL) > +#define RPP_LR_IFR_RCP_DATA_IPV6_DROP (0x41f324ffUL) > +#define RPP_LR_IFR_RCP_DATA_IPV6_EN (0x5431a9baUL) > +#define RPP_LR_IFR_RCP_DATA_MTU (0x871a2322UL) > +#define RPP_LR_RCP_CTRL (0xf3395d47UL) > +#define RPP_LR_RCP_CTRL_ADR (0x4916a944UL) > +#define RPP_LR_RCP_CTRL_CNT (0x591e3095UL) > +#define RPP_LR_RCP_DATA (0x5ce8df5eUL) > +#define RPP_LR_RCP_DATA_EXP (0x578ca035UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RPP_LR_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h > new file mode 100644 > index 0000000000..0a1fecd649 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h > @@ -0,0 +1,59 @@ > +/* > + * nthw_fpga_reg_defs_rst9563.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_RST9563_ > +#define _NTHW_FPGA_REG_DEFS_RST9563_ > + > +/* RST9563 */ > +#define NTHW_MOD_RST9563 (0x385d6d1dUL) > +#define RST9563_CTRL (0x8fe7585fUL) > +#define RST9563_CTRL_PTP_MMCM_CLKSEL (0xf441b405UL) > +#define RST9563_CTRL_TS_CLKSEL (0x210e9a78UL) > +#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (0x304bbf3UL) > +#define RST9563_POWER (0xdb6d3006UL) > +#define RST9563_POWER_PU_NSEB (0x68a55de6UL) > +#define RST9563_POWER_PU_PHY (0xdc0b7719UL) > +#define RST9563_RST (0x366a2a03UL) > +#define RST9563_RST_CORE_MMCM (0x4055af70UL) > +#define RST9563_RST_DDR4 (0x367cad64UL) > +#define RST9563_RST_MAC_RX (0x46da79e6UL) > +#define RST9563_RST_PERIPH (0xd39d53bdUL) > +#define RST9563_RST_PHY (0x50c57f90UL) > +#define RST9563_RST_PTP (0xcf6e9a69UL) > +#define RST9563_RST_PTP_MMCM (0xf69029c8UL) > +#define RST9563_RST_RPP (0xa8868b03UL) > +#define RST9563_RST_SDC (0x35477bfUL) > +#define RST9563_RST_SYS (0xe18f0bc7UL) > +#define RST9563_RST_SYS_MMCM (0x9f5c3d45UL) > +#define RST9563_RST_TMC (0xd7d9da73UL) > +#define RST9563_RST_TS (0x216dd0e7UL) > +#define RST9563_RST_TSM_REF_MMCM (0x664f1a24UL) > +#define RST9563_RST_TS_MMCM (0xce54ff59UL) > +#define RST9563_STAT (0xad7dd604UL) > +#define RST9563_STAT_CORE_MMCM_LOCKED (0xfd6d0a5aUL) > +#define RST9563_STAT_DDR4_MMCM_LOCKED (0xb902f1d0UL) > +#define RST9563_STAT_DDR4_PLL_LOCKED (0xe8a6d1b9UL) > +#define RST9563_STAT_PTP_MMCM_LOCKED (0x4e4fd2a9UL) > +#define RST9563_STAT_SYS_MMCM_LOCKED (0x5502a445UL) > +#define RST9563_STAT_TS_MMCM_LOCKED (0xe6405b02UL) > +#define RST9563_STICKY (0x97e2efe3UL) > +#define RST9563_STICKY_CORE_MMCM_UNLOCKED (0xac340bb6UL) > +#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (0x4737148cUL) > +#define RST9563_STICKY_DDR4_PLL_UNLOCKED (0xf9857d1bUL) > +#define RST9563_STICKY_PTP_MMCM_UNLOCKED (0x2a4e9819UL) > +#define RST9563_STICKY_SYS_MMCM_UNLOCKED (0x61e3ebbdUL) > +#define RST9563_STICKY_TS_MMCM_UNLOCKED (0x7e9f941eUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_RST9563_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h > new file mode 100644 > index 0000000000..ed3a25ebfa > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h > @@ -0,0 +1,44 @@ > +/* > + * nthw_fpga_reg_defs_sdc.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_SDC_ > +#define _NTHW_FPGA_REG_DEFS_SDC_ > + > +/* SDC */ > +#define NTHW_MOD_SDC (0xd2369530UL) > +#define SDC_CELL_CNT (0xc6d82110UL) > +#define SDC_CELL_CNT_CELL_CNT (0xdd4de629UL) > +#define SDC_CELL_CNT_PERIOD (0x8dfef1d4UL) > +#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (0x2b5819c1UL) > +#define SDC_CTRL (0x1577b205UL) > +#define SDC_CTRL_INIT (0x70e62104UL) > +#define SDC_CTRL_RESET_POINTERS (0xec1c0f9cUL) > +#define SDC_CTRL_RUN_TEST (0x2efbe98eUL) > +#define SDC_CTRL_STOP_CLIENT (0xb11ebe2dUL) > +#define SDC_CTRL_TEST_EN (0xaa1fa4UL) > +#define SDC_FILL_LVL (0xd3b30232UL) > +#define SDC_FILL_LVL_FILL_LVL (0xc97281acUL) > +#define SDC_MAX_FILL_LVL (0x326de743UL) > +#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (0x915fbf73UL) > +#define SDC_STAT (0x37ed3c5eUL) > +#define SDC_STAT_CALIB (0x27122e80UL) > +#define SDC_STAT_CELL_CNT_STOPPED (0x517d5cafUL) > +#define SDC_STAT_ERR_FOUND (0x3bb6bd0UL) > +#define SDC_STAT_INIT_DONE (0x1dc2e095UL) > +#define SDC_STAT_MMCM_LOCK (0xd9aac1c2UL) > +#define SDC_STAT_PLL_LOCK (0x3bcab6ebUL) > +#define SDC_STAT_RESETTING (0xa85349c1UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_SDC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h > new file mode 100644 > index 0000000000..da257a9425 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h > @@ -0,0 +1,33 @@ > +/* > + * nthw_fpga_reg_defs_slc.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_SLC_ > +#define _NTHW_FPGA_REG_DEFS_SLC_ > + > +/* SLC */ > +#define NTHW_MOD_SLC (0x1aef1f38UL) > +#define SLC_RCP_CTRL (0xa3373b1UL) > +#define SLC_RCP_CTRL_ADR (0xe64629e7UL) > +#define SLC_RCP_CTRL_CNT (0xf64eb036UL) > +#define SLC_RCP_DATA (0xa5e2f1a8UL) > +#define SLC_RCP_DATA_HEAD_DYN (0x86b55a78UL) > +#define SLC_RCP_DATA_HEAD_OFS (0x24bcd7deUL) > +#define SLC_RCP_DATA_HEAD_SLC_EN (0x61cf5ef7UL) > +#define SLC_RCP_DATA_PCAP (0x84909c04UL) > +#define SLC_RCP_DATA_TAIL_DYN (0x85cd93a3UL) > +#define SLC_RCP_DATA_TAIL_OFS (0x27c41e05UL) > +#define SLC_RCP_DATA_TAIL_SLC_EN (0xa4f5112cUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_SLC_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h > new file mode 100644 > index 0000000000..6d1cf03bd8 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_slc_lr.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_SLC_LR_ > +#define _NTHW_FPGA_REG_DEFS_SLC_LR_ > + > +/* SLC_LR */ > +#define NTHW_MOD_SLC_LR (0x969fc50bUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_SLC_LR_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h > new file mode 100644 > index 0000000000..1e9eebd59a > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h > @@ -0,0 +1,75 @@ > +/* > + * nthw_fpga_reg_defs_spim.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_SPIM_ > +#define _NTHW_FPGA_REG_DEFS_SPIM_ > + > +/* SPIM */ > +#define NTHW_MOD_SPIM (0x1da437bfUL) > +#define SPIM_CFG (0x90b6b0d5UL) > +#define SPIM_CFG_PRE (0x156a8ea9UL) > +#define SPIM_CFG_CLK (0xeb7046a1UL) > +#define SPIM_CFG_CLK_MODE (0x228be0cbUL) > +#define SPIM_CMD (0xea4b38a4UL) > +#define SPIM_CMD_ADDR (0x95fe56baUL) > +#define SPIM_CMD_CMD (0x9c30279bUL) > +#define SPIM_CMD_DATA (0x6a9737ecUL) > +#define SPIM_CONF0 (0x84d4acb5UL) > +#define SPIM_CONF0_BYTE_PACE (0xc9a95016UL) > +#define SPIM_CONF0_MIRROR_EN (0xa710688UL) > +#define SPIM_CONF0_MSB_FIRST (0x5f60c96aUL) > +#define SPIM_CONF0_PRESCAL_CLK (0xadb38a7UL) > +#define SPIM_CONF0_RESTART (0x1fda85dcUL) > +#define SPIM_CONF0_RST (0x64e3b3bUL) > +#define SPIM_CONF0_SYNC_MON_EN (0x591a639eUL) > +#define SPIM_CONF1 (0xf3d39c23UL) > +#define SPIM_CONF1_MIRROR_PACE (0x370f3f34UL) > +#define SPIM_CONF1_MIRROR_SCAN (0x83daffbeUL) > +#define SPIM_CONF1_SYNCTIMEOUT (0x1b5d30cdUL) > +#define SPIM_CONF2 (0x6adacd99UL) > +#define SPIM_CONF2_MIRROR_PRESC (0x3a8c10e2UL) > +#define SPIM_CONF2_OPCODE_RD (0x3eb6084fUL) > +#define SPIM_CONF2_OPCODE_WR (0xb715495bUL) > +#define SPIM_CONF3 (0x1dddfd0fUL) > +#define SPIM_CONF3_MIRROR_RDADR (0xc00ba60fUL) > +#define SPIM_CONF3_MIRROR_WRADR (0x7d99213cUL) > +#define SPIM_CR (0x1c1de013UL) > +#define SPIM_CR_EN (0xf2e0e72fUL) > +#define SPIM_CR_LOOP (0xdeb882aUL) > +#define SPIM_CR_RXRST (0x487f7d1bUL) > +#define SPIM_CR_TXRST (0xc73f88bbUL) > +#define SPIM_DRR (0xd68a95eeUL) > +#define SPIM_DRR_DRR (0x78766633UL) > +#define SPIM_DTR (0x80d03268UL) > +#define SPIM_DTR_DTR (0xf87522a8UL) > +#define SPIM_REPLY (0x6ed04defUL) > +#define SPIM_REPLY_RDDATA (0x40db3b24UL) > +#define SPIM_SR (0x56dff242UL) > +#define SPIM_SR_DONE (0xdb47e9a1UL) > +#define SPIM_SR_RXEMPTY (0x489aaf91UL) > +#define SPIM_SR_RXFULL (0xd26832f5UL) > +#define SPIM_SR_RXLVL (0x4c67ae59UL) > +#define SPIM_SR_TXEMPTY (0x2b4a9aabUL) > +#define SPIM_SR_TXFULL (0x431d1e8UL) > +#define SPIM_SR_TXLVL (0xc3275bf9UL) > +#define SPIM_SRR (0xcfe3201bUL) > +#define SPIM_SRR_RST (0x32dc8fc5UL) > +#define SPIM_STATUS (0xd04220ceUL) > +#define SPIM_STATUS_CMDPENDING (0x74ed833fUL) > +#define SPIM_STATUS_RESERVED (0xa50278bUL) > +#define SPIM_STATUS_RESYNCDETECT (0x5b268881UL) > +#define SPIM_STATUS_RESYNCING (0x5ec3f11UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_SPIM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h > new file mode 100644 > index 0000000000..30ff3a624e > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h > @@ -0,0 +1,50 @@ > +/* > + * nthw_fpga_reg_defs_spis.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_SPIS_ > +#define _NTHW_FPGA_REG_DEFS_SPIS_ > + > +/* SPIS */ > +#define NTHW_MOD_SPIS (0xe7ab0adcUL) > +#define SPIS_CR (0xacdbc0bfUL) > +#define SPIS_CR_DEBUG (0xf2096408UL) > +#define SPIS_CR_EN (0xc50100bcUL) > +#define SPIS_CR_LOOP (0x69e911c9UL) > +#define SPIS_CR_RXRST (0x7118cc40UL) > +#define SPIS_CR_TXRST (0xfe5839e0UL) > +#define SPIS_DRR (0x95abc0dUL) > +#define SPIS_DRR_DRR (0x1c74ffd0UL) > +#define SPIS_DTR (0x5f001b8bUL) > +#define SPIS_DTR_DTR (0x9c77bb4bUL) > +#define SPIS_RAM_CTRL (0x682dc7d8UL) > +#define SPIS_RAM_CTRL_ADR (0x15c2f809UL) > +#define SPIS_RAM_CTRL_CNT (0x5ca61d8UL) > +#define SPIS_RAM_DATA (0xc7fc45c1UL) > +#define SPIS_RAM_DATA_DATA (0x422b05eaUL) > +#define SPIS_SR (0xe619d2eeUL) > +#define SPIS_SR_DONE (0xbf457042UL) > +#define SPIS_SR_FRAME_ERR (0x31b5d7e4UL) > +#define SPIS_SR_READ_ERR (0xa83d91f1UL) > +#define SPIS_SR_RXEMPTY (0xadb39173UL) > +#define SPIS_SR_RXFULL (0x2ee8dd38UL) > +#define SPIS_SR_RXLVL (0x75001f02UL) > +#define SPIS_SR_TXEMPTY (0xce63a449UL) > +#define SPIS_SR_TXFULL (0xf8b13e25UL) > +#define SPIS_SR_TXLVL (0xfa40eaa2UL) > +#define SPIS_SR_WRITE_ERR (0x9d389ce2UL) > +#define SPIS_SRR (0x103309f8UL) > +#define SPIS_SRR_RST (0x56de1626UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_SPIS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h > new file mode 100644 > index 0000000000..a028ece8d8 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h > @@ -0,0 +1,59 @@ > +/* > + * nthw_fpga_reg_defs_sta.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_STA_ > +#define _NTHW_FPGA_REG_DEFS_STA_ > + > +/* STA */ > +#define NTHW_MOD_STA (0x76fae64dUL) > +#define STA_BYTE (0xa08364d4UL) > +#define STA_BYTE_CNT (0x3119e6bcUL) > +#define STA_CFG (0xcecaf9f4UL) > +#define STA_CFG_CNT_CLEAR (0xc325e12eUL) > +#define STA_CFG_CNT_FRZ (0x8c27a596UL) > +#define STA_CFG_DMA_ENA (0x940dbacUL) > +#define STA_CFG_TX_DISABLE (0x30f43250UL) > +#define STA_CV_ERR (0x7db7db5dUL) > +#define STA_CV_ERR_CNT (0x2c02fbbeUL) > +#define STA_FCS_ERR (0xa0de1647UL) > +#define STA_FCS_ERR_CNT (0xc68c37d1UL) > +#define STA_HOST_ADR_LSB (0xde569336UL) > +#define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL) > +#define STA_HOST_ADR_MSB (0xdf94f901UL) > +#define STA_HOST_ADR_MSB_MSB (0x114798c8UL) > +#define STA_LOAD_BIN (0x2e842591UL) > +#define STA_LOAD_BIN_BIN (0x1a2b942eUL) > +#define STA_LOAD_BPS_RX_0 (0xbf8f4595UL) > +#define STA_LOAD_BPS_RX_0_BPS (0x41647781UL) > +#define STA_LOAD_BPS_RX_1 (0xc8887503UL) > +#define STA_LOAD_BPS_RX_1_BPS (0x7c045e31UL) > +#define STA_LOAD_BPS_TX_0 (0x9ae41a49UL) > +#define STA_LOAD_BPS_TX_0_BPS (0x870b7e06UL) > +#define STA_LOAD_BPS_TX_1 (0xede32adfUL) > +#define STA_LOAD_BPS_TX_1_BPS (0xba6b57b6UL) > +#define STA_LOAD_PPS_RX_0 (0x811173c3UL) > +#define STA_LOAD_PPS_RX_0_PPS (0xbee573fcUL) > +#define STA_LOAD_PPS_RX_1 (0xf6164355UL) > +#define STA_LOAD_PPS_RX_1_PPS (0x83855a4cUL) > +#define STA_LOAD_PPS_TX_0 (0xa47a2c1fUL) > +#define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL) > +#define STA_LOAD_PPS_TX_1 (0xd37d1c89UL) > +#define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL) > +#define STA_PCKT (0xecc8f30aUL) > +#define STA_PCKT_CNT (0x63291d16UL) > +#define STA_STATUS (0x91c5c51cUL) > +#define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_STA_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git > a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h > new file mode 100644 > index 0000000000..5c5190bb4f > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h > @@ -0,0 +1,29 @@ > +/* > + * nthw_fpga_reg_defs_tempmon.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TEMPMON_ > +#define _NTHW_FPGA_REG_DEFS_TEMPMON_ > + > +/* TEMPMON */ > +#define NTHW_MOD_TEMPMON (0x2f77020dUL) > +#define TEMPMON_ALARMS (0x3f7046c2UL) > +#define TEMPMON_ALARMS_OT (0xb278af71UL) > +#define TEMPMON_ALARMS_OT_OVERWR (0x6e4d38d3UL) > +#define TEMPMON_ALARMS_OT_OVERWRVAL (0x9145f23eUL) > +#define TEMPMON_ALARMS_TEMP (0x85d42f2cUL) > +#define TEMPMON_STAT (0x9e81e173UL) > +#define TEMPMON_STAT_TEMP (0x7bd5bb7bUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TEMPMON_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h > new file mode 100644 > index 0000000000..9ffcec3bf6 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h > @@ -0,0 +1,27 @@ > +/* > + * nthw_fpga_reg_defs_tint.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TINT_ > +#define _NTHW_FPGA_REG_DEFS_TINT_ > + > +/* TINT */ > +#define NTHW_MOD_TINT (0xb8aea9feUL) > +#define TINT_CTRL (0x95bdc9c3UL) > +#define TINT_CTRL_INTERVAL (0xfe472b70UL) > +#define TINT_STATUS (0x2557d8a6UL) > +#define TINT_STATUS_DELAYED (0xabd2ff4cUL) > +#define TINT_STATUS_SKIPPED (0x1c35b879UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TINT_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h > new file mode 100644 > index 0000000000..1eb7939d3a > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h > @@ -0,0 +1,294 @@ > +/* > + * nthw_fpga_reg_defs_tsm.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TSM_ > +#define _NTHW_FPGA_REG_DEFS_TSM_ > + > +/* TSM */ > +#define NTHW_MOD_TSM (0x35422a24UL) > +#define TSM_ADJ_FINE_N (0x5ee7eb67UL) > +#define TSM_ADJ_FINE_N_2DY (0x5e4ebc9dUL) > +#define TSM_ADJ_FINE_N_2DY2DX (0x5d41df5UL) > +#define TSM_ADJ_FINE_P (0xa4e8d604UL) > +#define TSM_ADJ_FINE_P_2DY (0x819e957eUL) > +#define TSM_ADJ_FINE_P_2DY2DX (0x6ce53eecUL) > +#define TSM_ADJ_LIMIT_HI (0x735c7b90UL) > +#define TSM_ADJ_LIMIT_HI_LIMIT (0x868cb9a6UL) > +#define TSM_ADJ_LIMIT_LO (0xfe531ba1UL) > +#define TSM_ADJ_LIMIT_LO_LIMIT (0x61168266UL) > +#define TSM_BASIC_2DY (0x70dd9159UL) > +#define TSM_BASIC_2DY_2DY (0xeea30d3fUL) > +#define TSM_BASIC_2DY2DX (0xda5ebb56UL) > +#define TSM_BASIC_2DY2DX_2DY2DX (0x78a2f0edUL) > +#define TSM_CON0_CONFIG (0xf893d371UL) > +#define TSM_CON0_CONFIG_BLIND (0x59ccfcbUL) > +#define TSM_CON0_CONFIG_DC_SRC (0x1879812bUL) > +#define TSM_CON0_CONFIG_PORT (0x3ff0bb08UL) > +#define TSM_CON0_CONFIG_PPSIN_2_5V (0xb8e78227UL) > +#define TSM_CON0_CONFIG_SAMPLE_EDGE (0x4a4022ebUL) > +#define TSM_CON0_INTERFACE (0x76e93b59UL) > +#define TSM_CON0_INTERFACE_EX_TERM (0xd079b416UL) > +#define TSM_CON0_INTERFACE_IN_REF_PWM (0x16f73c33UL) > +#define TSM_CON0_INTERFACE_PWM_ENA (0x3629e73fUL) > +#define TSM_CON0_INTERFACE_RESERVED (0xf9c5066UL) > +#define TSM_CON0_INTERFACE_VTERM_PWM (0x6d2b1e23UL) > +#define TSM_CON0_SAMPLE_HI (0x6e536b8UL) > +#define TSM_CON0_SAMPLE_HI_SEC (0x5fc26159UL) > +#define TSM_CON0_SAMPLE_LO (0x8bea5689UL) > +#define TSM_CON0_SAMPLE_LO_NS (0x13d0010dUL) > +#define TSM_CON1_CONFIG (0x3439d3efUL) > +#define TSM_CON1_CONFIG_BLIND (0x98932ebdUL) > +#define TSM_CON1_CONFIG_DC_SRC (0xa1825ac3UL) > +#define TSM_CON1_CONFIG_PORT (0xe266628dUL) > +#define TSM_CON1_CONFIG_PPSIN_2_5V (0x6f05027fUL) > +#define TSM_CON1_CONFIG_SAMPLE_EDGE (0x2f2719adUL) > +#define TSM_CON1_SAMPLE_HI (0xc76be978UL) > +#define TSM_CON1_SAMPLE_HI_SEC (0xe639bab1UL) > +#define TSM_CON1_SAMPLE_LO (0x4a648949UL) > +#define TSM_CON1_SAMPLE_LO_NS (0x8edfe07bUL) > +#define TSM_CON2_CONFIG (0xbab6d40cUL) > +#define TSM_CON2_CONFIG_BLIND (0xe4f20b66UL) > +#define TSM_CON2_CONFIG_DC_SRC (0xb0ff30baUL) > +#define TSM_CON2_CONFIG_PORT (0x5fac0e43UL) > +#define TSM_CON2_CONFIG_PPSIN_2_5V (0xcc5384d6UL) > +#define TSM_CON2_CONFIG_SAMPLE_EDGE (0x808e5467UL) > +#define TSM_CON2_SAMPLE_HI (0x5e898f79UL) > +#define TSM_CON2_SAMPLE_HI_SEC (0xf744d0c8UL) > +#define TSM_CON2_SAMPLE_LO (0xd386ef48UL) > +#define TSM_CON2_SAMPLE_LO_NS (0xf2bec5a0UL) > +#define TSM_CON3_CONFIG (0x761cd492UL) > +#define TSM_CON3_CONFIG_BLIND (0x79fdea10UL) > +#define TSM_CON3_CONFIG_PORT (0x823ad7c6UL) > +#define TSM_CON3_CONFIG_SAMPLE_EDGE (0xe5e96f21UL) > +#define TSM_CON3_SAMPLE_HI (0x9f0750b9UL) > +#define TSM_CON3_SAMPLE_HI_SEC (0x4ebf0b20UL) > +#define TSM_CON3_SAMPLE_LO (0x12083088UL) > +#define TSM_CON3_SAMPLE_LO_NS (0x6fb124d6UL) > +#define TSM_CON4_CONFIG (0x7cd9dd8bUL) > +#define TSM_CON4_CONFIG_BLIND (0x1c3040d0UL) > +#define TSM_CON4_CONFIG_PORT (0xff49d19eUL) > +#define TSM_CON4_CONFIG_SAMPLE_EDGE (0x4adc9b2UL) > +#define TSM_CON4_SAMPLE_HI (0xb63c453aUL) > +#define TSM_CON4_SAMPLE_HI_SEC (0xd5be043aUL) > +#define TSM_CON4_SAMPLE_LO (0x3b33250bUL) > +#define TSM_CON4_SAMPLE_LO_NS (0xa7c8e16UL) > +#define TSM_CON5_CONFIG (0xb073dd15UL) > +#define TSM_CON5_CONFIG_BLIND (0x813fa1a6UL) > +#define TSM_CON5_CONFIG_PORT (0x22df081bUL) > +#define TSM_CON5_CONFIG_SAMPLE_EDGE (0x61caf2f4UL) > +#define TSM_CON5_SAMPLE_HI (0x77b29afaUL) > +#define TSM_CON5_SAMPLE_HI_SEC (0x6c45dfd2UL) > +#define TSM_CON5_SAMPLE_LO (0xfabdfacbUL) > +#define TSM_CON5_SAMPLE_LO_TIME (0x945d87e8UL) > +#define TSM_CON6_CONFIG (0x3efcdaf6UL) > +#define TSM_CON6_CONFIG_BLIND (0xfd5e847dUL) > +#define TSM_CON6_CONFIG_PORT (0x9f1564d5UL) > +#define TSM_CON6_CONFIG_SAMPLE_EDGE (0xce63bf3eUL) > +#define TSM_CON6_SAMPLE_HI (0xee50fcfbUL) > +#define TSM_CON6_SAMPLE_HI_SEC (0x7d38b5abUL) > +#define TSM_CON6_SAMPLE_LO (0x635f9ccaUL) > +#define TSM_CON6_SAMPLE_LO_NS (0xeb124abbUL) > +#define TSM_CON7_HOST_SAMPLE_HI (0xdcd90e52UL) > +#define TSM_CON7_HOST_SAMPLE_HI_SEC (0xd98d3618UL) > +#define TSM_CON7_HOST_SAMPLE_LO (0x51d66e63UL) > +#define TSM_CON7_HOST_SAMPLE_LO_NS (0x8f5594ddUL) > +#define TSM_CONFIG (0xef5dec83UL) > +#define TSM_CONFIG_NTTS_SRC (0x1b60227bUL) > +#define TSM_CONFIG_NTTS_SYNC (0x43e0a69dUL) > +#define TSM_CONFIG_TIMESET_EDGE (0x8c381127UL) > +#define TSM_CONFIG_TIMESET_SRC (0xe7590a31UL) > +#define TSM_CONFIG_TIMESET_UP (0x561980c1UL) > +#define TSM_CONFIG_TS_FORMAT (0xe6efc2faUL) > +#define TSM_CTRL (0x87c1782cUL) > +#define TSM_CTRL_DCEN_CON0 (0x50b3db87UL) > +#define TSM_CTRL_DCEN_CON1 (0x27b4eb11UL) > +#define TSM_CTRL_DCEN_CON2 (0xbebdbaabUL) > +#define TSM_CTRL_FORMAT (0xd6f91ae8UL) > +#define TSM_CTRL_HIGH_SAMPLE (0x6d4509b1UL) > +#define TSM_CTRL_LED_CON0 (0x225af447UL) > +#define TSM_CTRL_LED_CON1 (0x555dc4d1UL) > +#define TSM_CTRL_LED_CON2 (0xcc54956bUL) > +#define TSM_CTRL_MASTER_STAT (0x6a0e3d17UL) > +#define TSM_CTRL_OEN_CON0 (0xd4ed0c2UL) > +#define TSM_CTRL_OEN_CON1 (0x7a49e054UL) > +#define TSM_CTRL_OEN_CON2 (0xe340b1eeUL) > +#define TSM_CTRL_PPSEN (0x9eada897UL) > +#define TSM_CTRL_PPS_NEGEDGE (0x8390d486UL) > +#define TSM_CTRL_PPS_TIME_UP (0x78161775UL) > +#define TSM_CTRL_PTP_TIME_UP (0x48708bcaUL) > +#define TSM_CTRL_RESERVED (0x3026aeb5UL) > +#define TSM_CTRL_SEL_EXTSRC (0x57855b43UL) > +#define TSM_CTRL_SYNEN (0xb0fbadeeUL) > +#define TSM_CTRL_TS_CON0 (0x7c756725UL) > +#define TSM_CTRL_TS_CON1 (0xb7257b3UL) > +#define TSM_CTRL_TS_CON2 (0x927b0609UL) > +#define TSM_EXT_STAT (0xf7c0a6cbUL) > +#define TSM_EXT_STAT_STAT (0xb32dd5d8UL) > +#define TSM_EXT_TIME_HI (0x678de1fUL) > +#define TSM_EXT_TIME_HI_TIME (0xe8159c02UL) > +#define TSM_EXT_TIME_LO (0x8b77be2eUL) > +#define TSM_EXT_TIME_LO_TIME (0xca035b0cUL) > +#define TSM_INTERFACE (0xe4ab597bUL) > +#define TSM_INTERFACE_EX_TERM (0x9e5553e6UL) > +#define TSM_INTERFACE_IN_REF_PWM (0x80d44665UL) > +#define TSM_INTERFACE_PWM_ENA (0x780500cfUL) > +#define TSM_INTERFACE_RESERVED (0xb26f8e9dUL) > +#define TSM_INTERFACE_VTERM_PWM (0x47f9c669UL) > +#define TSM_INT_CONFIG (0x9a0d52dUL) > +#define TSM_INT_CONFIG_AUTO_DISABLE (0x9581470UL) > +#define TSM_INT_CONFIG_MASK (0xf00cd3d7UL) > +#define TSM_INT_STAT (0xa4611a70UL) > +#define TSM_INT_STAT_CAUSE (0x315168cfUL) > +#define TSM_INT_STAT_ENABLE (0x980a12d1UL) > +#define TSM_INT_TIME_HI (0x26d2bd77UL) > +#define TSM_INT_TIME_HI_TIME (0x29af0477UL) > +#define TSM_INT_TIME_LO (0xabdddd46UL) > +#define TSM_INT_TIME_LO_TIME (0xbb9c379UL) > +#define TSM_LED (0x6ae05f87UL) > +#define TSM_LED_LED0_BG_COLOR (0x897cf9eeUL) > +#define TSM_LED_LED0_COLOR (0x6d7ada39UL) > +#define TSM_LED_LED0_MODE (0x6087b644UL) > +#define TSM_LED_LED0_SRC (0x4fe29639UL) > +#define TSM_LED_LED1_BG_COLOR (0x66be92d0UL) > +#define TSM_LED_LED1_COLOR (0xcb0dd18dUL) > +#define TSM_LED_LED1_MODE (0xabdb65e1UL) > +#define TSM_LED_LED1_SRC (0x7282bf89UL) > +#define TSM_LED_LED2_BG_COLOR (0x8d8929d3UL) > +#define TSM_LED_LED2_COLOR (0xfae5cb10UL) > +#define TSM_LED_LED2_MODE (0x2d4f174fUL) > +#define TSM_LED_LED2_SRC (0x3522c559UL) > +#define TSM_NTTS_CONFIG (0x8bc38bdeUL) > +#define TSM_NTTS_CONFIG_AUTO_HARDSET (0xd75be25dUL) > +#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (0x700425b6UL) > +#define TSM_NTTS_CONFIG_HIGH_SAMPLE (0x37135b7eUL) > +#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (0x6e6e707UL) > +#define TSM_NTTS_CTRL (0x4798367bUL) > +#define TSM_NTTS_CTRL_NTTS_CMD (0x85e132cfUL) > +#define TSM_NTTS_DATA_HI (0x6bfb0188UL) > +#define TSM_NTTS_DATA_HI_DATA (0x44315d8UL) > +#define TSM_NTTS_DATA_LO (0xe6f461b9UL) > +#define TSM_NTTS_DATA_LO_DATA (0x2655d2d6UL) > +#define TSM_NTTS_EXT_STAT (0x2b0315b7UL) > +#define TSM_NTTS_EXT_STAT_MASTER_ID (0xf263315eUL) > +#define TSM_NTTS_EXT_STAT_MASTER_REV (0xd543795eUL) > +#define TSM_NTTS_EXT_STAT_MASTER_STAT (0x92d96f5eUL) > +#define TSM_NTTS_LIMIT_HI (0x1ddaa85fUL) > +#define TSM_NTTS_LIMIT_HI_SEC (0x315c6ef2UL) > +#define TSM_NTTS_LIMIT_LO (0x90d5c86eUL) > +#define TSM_NTTS_LIMIT_LO_NS (0xe6d94d9aUL) > +#define TSM_NTTS_OFFSET (0x6436e72UL) > +#define TSM_NTTS_OFFSET_NS (0x12d43a06UL) > +#define TSM_NTTS_SAMPLE_HI (0xcdc8aa3eUL) > +#define TSM_NTTS_SAMPLE_HI_SEC (0x4f6588fdUL) > +#define TSM_NTTS_SAMPLE_LO (0x40c7ca0fUL) > +#define TSM_NTTS_SAMPLE_LO_NS (0x6e43ff97UL) > +#define TSM_NTTS_STAT (0x6502b820UL) > +#define TSM_NTTS_STAT_NTTS_VALID (0x3e184471UL) > +#define TSM_NTTS_STAT_SIGNAL_LOST (0x178bedfdUL) > +#define TSM_NTTS_STAT_SYNC_LOST (0xe4cd53dfUL) > +#define TSM_NTTS_TS_T0_HI (0x1300d1b6UL) > +#define TSM_NTTS_TS_T0_HI_TIME (0xa016ae4fUL) > +#define TSM_NTTS_TS_T0_LO (0x9e0fb187UL) > +#define TSM_NTTS_TS_T0_LO_TIME (0x82006941UL) > +#define TSM_NTTS_TS_T0_OFFSET (0xbf70ce4fUL) > +#define TSM_NTTS_TS_T0_OFFSET_COUNT (0x35dd4398UL) > +#define TSM_OFFSET_HI (0xb5b09839UL) > +#define TSM_OFFSET_HI_OFFSET (0xec7bf359UL) > +#define TSM_OFFSET_LO (0x38bff808UL) > +#define TSM_OFFSET_LO_OFFSET (0x77f8abd2UL) > +#define TSM_PB_CTRL (0x7a8b60faUL) > +#define TSM_PB_CTRL_INSTMEM_WR (0xf96e2cbcUL) > +#define TSM_PB_CTRL_RESET (0xa38ade8bUL) > +#define TSM_PB_CTRL_RST (0x3aaa82f4UL) > +#define TSM_PB_INSTMEM (0xb54aeecUL) > +#define TSM_PB_INSTMEM_ADDR (0x3549ddaaUL) > +#define TSM_PB_INSTMEM_DATA (0xca20bcfcUL) > +#define TSM_PB_INSTMEM_MEM_ADDR (0x9ac79b6eUL) > +#define TSM_PB_INSTMEM_MEM_DATA (0x65aefa38UL) > +#define TSM_PI_CTRL_I (0x8d71a4e2UL) > +#define TSM_PI_CTRL_I_VAL (0x98baedc9UL) > +#define TSM_PI_CTRL_KI (0xa1bd86cbUL) > +#define TSM_PI_CTRL_KI_GAIN (0x53faa916UL) > +#define TSM_PI_CTRL_KP (0xc5d62e0bUL) > +#define TSM_PI_CTRL_KP_GAIN (0x7723fa45UL) > +#define TSM_PI_CTRL_SHL (0xaa518701UL) > +#define TSM_PI_CTRL_SHL_VAL (0x56f56a6fUL) > +#define TSM_RSYNC_COUNT (0xa7bb7108UL) > +#define TSM_RSYNC_COUNT_COUNT (0x66e7d46UL) > +#define TSM_STAT (0xa55bf677UL) > +#define TSM_STAT_EXT_SRC_OK (0x62036046UL) > +#define TSM_STAT_HARD_SYNC (0x7fff20fdUL) > +#define TSM_STAT_INSYNC (0x29f2e4adUL) > +#define TSM_STAT_LINK_ACTIVE (0x575513d4UL) > +#define TSM_STAT_LINK_CON0 (0x216086f0UL) > +#define TSM_STAT_LINK_CON1 (0x5667b666UL) > +#define TSM_STAT_LINK_CON2 (0xcf6ee7dcUL) > +#define TSM_STAT_LINK_CON3 (0xb869d74aUL) > +#define TSM_STAT_LINK_CON4 (0x260d42e9UL) > +#define TSM_STAT_LINK_CON5 (0x510a727fUL) > +#define TSM_STAT_NTTS_INSYNC (0xb593a245UL) > +#define TSM_STAT_PTP_MI_PRESENT (0x43131eb0UL) > +#define TSM_TIMER_CTRL (0x648da051UL) > +#define TSM_TIMER_CTRL_TIMER_EN_T0 (0x17cee154UL) > +#define TSM_TIMER_CTRL_TIMER_EN_T1 (0x60c9d1c2UL) > +#define TSM_TIMER_CTRL_TRIGGER_SEL (0x79f7c3a5UL) > +#define TSM_TIMER_D_T0 (0xfae6ed98UL) > +#define TSM_TIMER_D_T0_MAX_COUNT (0xbd0df6dbUL) > +#define TSM_TIMER_T0 (0x417217a5UL) > +#define TSM_TIMER_T0_MAX_COUNT (0xaa601706UL) > +#define TSM_TIMER_T1 (0x36752733UL) > +#define TSM_TIMER_T1_MAX_COUNT (0x6beec8c6UL) > +#define TSM_TIMESTAMP_HI (0x59f35088UL) > +#define TSM_TIMESTAMP_HI_TIME (0x56f613f0UL) > +#define TSM_TIMESTAMP_LO (0xd4fc30b9UL) > +#define TSM_TIMESTAMP_LO_TIME (0x74e0d4feUL) > +#define TSM_TIME_HARDSET_HI (0xf28bdb46UL) > +#define TSM_TIME_HARDSET_HI_TIME (0x2d9a28baUL) > +#define TSM_TIME_HARDSET_LO (0x7f84bb77UL) > +#define TSM_TIME_HARDSET_LO_TIME (0xf8cefb4UL) > +#define TSM_TIME_HI (0x175acea1UL) > +#define TSM_TIME_HI_SEC (0xc0e9c9a1UL) > +#define TSM_TIME_HI_TIME (0x7febcc76UL) > +#define TSM_TIME_LO (0x9a55ae90UL) > +#define TSM_TIME_LO_NS (0x879c5c4bUL) > +#define TSM_TIME_RATE_ADJ (0xb1cc4bb1UL) > +#define TSM_TIME_RATE_ADJ_FRACTION (0xb7ab96UL) > +#define TSM_TS_HI (0xccfe9e5eUL) > +#define TSM_TS_HI_TIME (0xc23fed30UL) > +#define TSM_TS_LO (0x41f1fe6fUL) > +#define TSM_TS_LO_TIME (0xe0292a3eUL) > +#define TSM_TS_OFFSET (0x4b2e6e13UL) > +#define TSM_TS_OFFSET_NS (0x68c286b9UL) > +#define TSM_TS_STAT (0x64d41b8cUL) > +#define TSM_TS_STAT_OVERRUN (0xad9db92aUL) > +#define TSM_TS_STAT_SAMPLES (0xb6350e0bUL) > +#define TSM_TS_STAT_HI_OFFSET (0x1aa2ddf2UL) > +#define TSM_TS_STAT_HI_OFFSET_NS (0xeb040e0fUL) > +#define TSM_TS_STAT_LO_OFFSET (0x81218579UL) > +#define TSM_TS_STAT_LO_OFFSET_NS (0xb7ff33UL) > +#define TSM_TS_STAT_TAR_HI (0x65af24b6UL) > +#define TSM_TS_STAT_TAR_HI_SEC (0x7e92f619UL) > +#define TSM_TS_STAT_TAR_LO (0xe8a04487UL) > +#define TSM_TS_STAT_TAR_LO_NS (0xf7b3f439UL) > +#define TSM_TS_STAT_X (0x419f0ddUL) > +#define TSM_TS_STAT_X_NS (0xa48c3f27UL) > +#define TSM_TS_STAT_X2_HI (0xd6b1c517UL) > +#define TSM_TS_STAT_X2_HI_NS (0x4288c50fUL) > +#define TSM_TS_STAT_X2_LO (0x5bbea526UL) > +#define TSM_TS_STAT_X2_LO_NS (0x92633c13UL) > +#define TSM_UTC_OFFSET (0xf622a13aUL) > +#define TSM_UTC_OFFSET_SEC (0xd9c80209UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TSM_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h > new file mode 100644 > index 0000000000..2b156f9de9 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_tx_cpy.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TX_CPY_ > +#define _NTHW_FPGA_REG_DEFS_TX_CPY_ > + > +/* TX_CPY */ > +#define NTHW_MOD_TX_CPY (0x60acf217UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TX_CPY_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h > new file mode 100644 > index 0000000000..98d9bbc452 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_tx_csi.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TX_CSI_ > +#define _NTHW_FPGA_REG_DEFS_TX_CSI_ > + > +/* TX_CSI */ > +#define NTHW_MOD_TX_CSI (0x5636b1b0UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TX_CSI_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h > new file mode 100644 > index 0000000000..8b2d77878b > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_tx_cso.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TX_CSO_ > +#define _NTHW_FPGA_REG_DEFS_TX_CSO_ > + > +/* TX_CSO */ > +#define NTHW_MOD_TX_CSO (0xbf551485UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TX_CSO_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h > new file mode 100644 > index 0000000000..48add8d788 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_tx_ins.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TX_INS_ > +#define _NTHW_FPGA_REG_DEFS_TX_INS_ > + > +/* TX_INS */ > +#define NTHW_MOD_TX_INS (0x59afa100UL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TX_INS_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h > new file mode 100644 > index 0000000000..2ddeadaf53 > --- /dev/null > +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h > @@ -0,0 +1,22 @@ > +/* > + * nthw_fpga_reg_defs_tx_rpl.h > + * > + * Auto-generated file - do *NOT* edit > + * > + */ > + > +#ifndef _NTHW_FPGA_REG_DEFS_TX_RPL_ > +#define _NTHW_FPGA_REG_DEFS_TX_RPL_ > + > +/* TX_RPL */ > +#define NTHW_MOD_TX_RPL (0x1095dfbbUL) > + > +#endif /* _NTHW_FPGA_REG_DEFS_TX_RPL_ */ > + > +/* > + * Auto-generated file - do *NOT* edit > + */ > + > +/* > + * EOF > + */ > -- > 2.45.0 --_000_VE1P190MB08300D0553879E2525AC6FE380FB2VE1P190MB0830EURP_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Hi Ferruh,

We have sent a patch set which includes base PMD driver for NapaTech smartN= iC for DPDK v24.07.

This time, driver has limited basic functionality(Link up only) and we have= made refactoring to split it into smaller patches.
Extended functionality is planned for upstream to the next release DPDK 24.= 11.

Patches have passed the CI but there are several code style warnings which = we assumed as false-positive. 
Could you please take a look at these patches and suggest us how = we can procced with it?


Best regards,
Serhii

From: Mykola= Kostenok <mko-plv@napatech.com>
Sent: 04 June 2024 13:29
To: Serhii Iliushyk <sil-plv@napatech.com>; dev@dpdk.org = <dev@dpdk.org>
Cc: Christian Koue Muf <ckm@napatech.com>; andrew.rybchen= ko@oktetlabs.ru <andrew.rybchenko@oktetlabs.ru>; ferruh.yigit@amd.com= <ferruh.yigit@amd.com>
Subject: RE: [PATCH v3 01/17] net/ntnic: Add registers for Napa= Tech SmartNiC
 
Recheck-request: iol-unit-amd64-testing, io= l-compile-amd64-testing, iol-unit-arm64-testing, iol-compile-arm64-testing<= br>
> -----Original Message-----
> From: Serhii Iliushyk <sil-plv@napatech.com>
> Sent: Monday, June 3, 2024 7:18 PM
> To: dev@dpdk.org
> Cc: Mykola Kostenok <mko-plv@napatech.com>; Christian Koue Muf > <ckm@napatech.com>; andrew.rybchenko@oktetlabs.ru;
> ferruh.yigit@amd.com
> Subject: [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartN= iC
>
> The NTNIC PMD does not rely on a kernel space Napatech driver,
> thus all defines related to the register layout is part of the PMD
> code, which will be added in later commits.
>
> Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
> ---
>  .../supported/nthw_fpga_9563_055_039_0000.c   | 3488 > +++++++++++++++++
>  .../nthw/supported/nthw_fpga_instances.c    =   |    6 +
>  .../nthw/supported/nthw_fpga_instances.h    =   |    7 +
>  .../ntnic/nthw/supported/nthw_fpga_mod_defs.h |   93 +=
>  .../nthw/supported/nthw_fpga_mod_str_map.c    |&n= bsp;  78 +
>  .../nthw/supported/nthw_fpga_mod_str_map.h    |&n= bsp;  11 +
>  .../nthw/supported/nthw_fpga_param_defs.h    = ; |  232 ++
>  .../ntnic/nthw/supported/nthw_fpga_reg_defs.h |   94 +=
>  .../nthw/supported/nthw_fpga_reg_defs_cat.h   |  = 237 ++
>  .../nthw/supported/nthw_fpga_reg_defs_cb.h    |&n= bsp;  73 +
>  .../nthw/supported/nthw_fpga_reg_defs_cor.h   | &= nbsp; 81 +
>  .../nthw/supported/nthw_fpga_reg_defs_cpy.h   |  = 112 +
>  .../nthw/supported/nthw_fpga_reg_defs_csu.h   | &= nbsp; 30 +
>  .../nthw/supported/nthw_fpga_reg_defs_dbs.h   |  = 144 +
>  .../nthw/supported/nthw_fpga_reg_defs_ddp.h   | &= nbsp; 34 +
>  .../nthw/supported/nthw_fpga_reg_defs_epp.h   | &= nbsp; 64 +
>  .../nthw/supported/nthw_fpga_reg_defs_eqm.h   | &= nbsp; 45 +
>  .../nthw/supported/nthw_fpga_reg_defs_fhm.h   | &= nbsp; 48 +
>  .../nthw/supported/nthw_fpga_reg_defs_flm.h   |  = 237 ++
>  .../nthw/supported/nthw_fpga_reg_defs_gfg.h   |  = 126 +
>  .../nthw/supported/nthw_fpga_reg_defs_gmf.h   | &= nbsp; 68 +
>  .../supported/nthw_fpga_reg_defs_gpio_phy.h   | &= nbsp; 48 +
>  .../nthw_fpga_reg_defs_gpio_phy_ports.h    &= nbsp;  |   72 +
>  .../supported/nthw_fpga_reg_defs_gpio_sfpp.h  |  = 34 +
>  .../nthw/supported/nthw_fpga_reg_defs_hfu.h   | &= nbsp; 48 +
>  .../nthw/supported/nthw_fpga_reg_defs_hif.h   | &= nbsp; 79 +
>  .../nthw/supported/nthw_fpga_reg_defs_hsh.h   | &= nbsp; 49 +
>  .../nthw/supported/nthw_fpga_reg_defs_i2cm.h  |  = 38 +
>  .../nthw/supported/nthw_fpga_reg_defs_ifr.h   | &= nbsp; 41 +
>  .../nthw/supported/nthw_fpga_reg_defs_igam.h  |  = 28 +
>  .../nthw/supported/nthw_fpga_reg_defs_iic.h   | &= nbsp; 96 +
>  .../nthw/supported/nthw_fpga_reg_defs_ins.h   | &= nbsp; 29 +
>  .../nthw/supported/nthw_fpga_reg_defs_ioa.h   | &= nbsp; 44 +
>  .../nthw/supported/nthw_fpga_reg_defs_ipf.h   | &= nbsp; 84 +
>  .../nthw/supported/nthw_fpga_reg_defs_km.h    |&n= bsp; 125 +
>  .../nthw/supported/nthw_fpga_reg_defs_mac.h   |  = 177 +
>  .../supported/nthw_fpga_reg_defs_mac_pcs.h    |&n= bsp; 298 ++
>  .../nthw_fpga_reg_defs_mac_pcs_xxv.h    &nbs= p;     | 1092 ++++++
>  .../supported/nthw_fpga_reg_defs_mac_rx.h    = ; |   90 +
>  .../supported/nthw_fpga_reg_defs_mac_tfg.h    |&n= bsp;  42 +
>  .../supported/nthw_fpga_reg_defs_mac_tx.h    = ; |   70 +
>  .../nthw/supported/nthw_fpga_reg_defs_msk.h   | &= nbsp; 42 +
>  .../supported/nthw_fpga_reg_defs_pci_rd_tg.h  |  = 37 +
>  .../supported/nthw_fpga_reg_defs_pci_ta.h    = ; |   32 +
>  .../supported/nthw_fpga_reg_defs_pci_wr_tg.h  |  = 40 +
>  .../nthw/supported/nthw_fpga_reg_defs_pcie3.h |  281 ++
>  .../nthw_fpga_reg_defs_pcm_nt400dxx.h    &nb= sp;    |   19 +
>  .../nthw_fpga_reg_defs_pcm_nt50b01_01.h    &= nbsp;  |   19 +
>  .../nthw/supported/nthw_fpga_reg_defs_pcs.h   | &= nbsp; 92 +
>  .../supported/nthw_fpga_reg_defs_pcs100.h    = ; |   90 +
>  .../nthw/supported/nthw_fpga_reg_defs_pdb.h   | &= nbsp; 47 +
>  .../nthw/supported/nthw_fpga_reg_defs_pdi.h   | &= nbsp; 48 +
>  .../supported/nthw_fpga_reg_defs_phy_tile.h   |  = 196 +
>  .../nthw_fpga_reg_defs_prm_nt400dxx.h    &nb= sp;    |   19 +
>  .../nthw_fpga_reg_defs_prm_nt50b01_01.h    &= nbsp;  |   19 +
>  .../nthw/supported/nthw_fpga_reg_defs_qsl.h   | &= nbsp; 65 +
>  .../nthw/supported/nthw_fpga_reg_defs_qspi.h  |  = 89 +
>  .../nthw/supported/nthw_fpga_reg_defs_r2drp.h |   29 +=
>  .../nthw/supported/nthw_fpga_reg_defs_rac.h   | &= nbsp; 72 +
>  .../nthw/supported/nthw_fpga_reg_defs_rfd.h   | &= nbsp; 37 +
>  .../nthw/supported/nthw_fpga_reg_defs_rmc.h   | &= nbsp; 35 +
>  .../nthw/supported/nthw_fpga_reg_defs_roa.h   | &= nbsp; 67 +
>  .../nthw/supported/nthw_fpga_reg_defs_rpf.h   | &= nbsp; 30 +
>  .../nthw/supported/nthw_fpga_reg_defs_rpl.h   | &= nbsp; 42 +
>  .../supported/nthw_fpga_reg_defs_rpp_lr.h    = ; |   36 +
>  .../supported/nthw_fpga_reg_defs_rst9563.h    |&n= bsp;  59 +
>  .../nthw/supported/nthw_fpga_reg_defs_sdc.h   | &= nbsp; 44 +
>  .../nthw/supported/nthw_fpga_reg_defs_slc.h   | &= nbsp; 33 +
>  .../supported/nthw_fpga_reg_defs_slc_lr.h    = ; |   22 +
>  .../nthw/supported/nthw_fpga_reg_defs_spim.h  |  = 75 +
>  .../nthw/supported/nthw_fpga_reg_defs_spis.h  |  = 50 +
>  .../nthw/supported/nthw_fpga_reg_defs_sta.h   | &= nbsp; 59 +
>  .../supported/nthw_fpga_reg_defs_tempmon.h    |&n= bsp;  29 +
>  .../nthw/supported/nthw_fpga_reg_defs_tint.h  |  = 27 +
>  .../nthw/supported/nthw_fpga_reg_defs_tsm.h   |  = 294 ++
>  .../supported/nthw_fpga_reg_defs_tx_cpy.h    = ; |   22 +
>  .../supported/nthw_fpga_reg_defs_tx_csi.h    = ; |   22 +
>  .../supported/nthw_fpga_reg_defs_tx_cso.h    = ; |   22 +
>  .../supported/nthw_fpga_reg_defs_tx_ins.h    = ; |   22 +
>  .../supported/nthw_fpga_reg_defs_tx_rpl.h    = ; |   22 +
>  80 files changed, 10177 insertions(+)
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h >  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h >  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h >  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
>  create mode 100644
> drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
>
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
> new file mode 100644
> index 0000000000..a7ee892007
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
> @@ -0,0 +1,3488 @@
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +#include "nthw_register.h"
> +
> +static nthw_fpga_field_init_s cat_cct_ctrl_fields[] =3D {
> +     { CAT_CCT_CTRL_ADR, 8, 0, 0x0000 },
> +     { CAT_CCT_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cct_data_fields[] =3D {
> +     { CAT_CCT_DATA_COLOR, 32, 0, 0x0000 },
> +     { CAT_CCT_DATA_KM, 4, 32, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cfn_ctrl_fields[] =3D {
> +     { CAT_CFN_CTRL_ADR, 6, 0, 0x0000 },
> +     { CAT_CFN_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cfn_data_fields[] =3D {
> +     { CAT_CFN_DATA_ENABLE, 1, 0, 0x0000 },
> +     { CAT_CFN_DATA_ERR_CV, 2, 99, 0x0000 },
> +     { CAT_CFN_DATA_ERR_FCS, 2, 101, 0x0000 }, > +     { CAT_CFN_DATA_ERR_INV, 1, 98, 0x0000 },
> +     { CAT_CFN_DATA_ERR_L3_CS, 2, 105, 0x0000 },<= br> > +     { CAT_CFN_DATA_ERR_L4_CS, 2, 107, 0x0000 },<= br> > +     { CAT_CFN_DATA_ERR_TNL_L3_CS, 2, 109, 0x0000= },
> +     { CAT_CFN_DATA_ERR_TNL_L4_CS, 2, 111, 0x0000= },
> +     { CAT_CFN_DATA_ERR_TNL_TTL_EXP, 2, 115, 0x00= 00 },
> +     { CAT_CFN_DATA_ERR_TRUNC, 2, 103, 0x0000 },<= br> > +     { CAT_CFN_DATA_ERR_TTL_EXP, 2, 113, 0x0000 }= ,
> +     { CAT_CFN_DATA_INV, 1, 1, 0x0000 },
> +     { CAT_CFN_DATA_KM0_OR, 3, 173, 0x0000 },
> +     { CAT_CFN_DATA_KM1_OR, 3, 176, 0x0000 },
> +     { CAT_CFN_DATA_LC, 8, 164, 0x0000 },
> +     { CAT_CFN_DATA_LC_INV, 1, 172, 0x0000 },
> +     { CAT_CFN_DATA_MAC_PORT, 2, 117, 0x0000 }, > +     { CAT_CFN_DATA_PM_AND_INV, 1, 161, 0x0000 },=
> +     { CAT_CFN_DATA_PM_CMB, 4, 157, 0x0000 },
> +     { CAT_CFN_DATA_PM_CMP, 32, 119, 0x0000 }, > +     { CAT_CFN_DATA_PM_DCT, 2, 151, 0x0000 },
> +     { CAT_CFN_DATA_PM_EXT_INV, 4, 153, 0x0000 },=
> +     { CAT_CFN_DATA_PM_INV, 1, 163, 0x0000 },
> +     { CAT_CFN_DATA_PM_OR_INV, 1, 162, 0x0000 },<= br> > +     { CAT_CFN_DATA_PTC_CFP, 2, 5, 0x0000 },
> +     { CAT_CFN_DATA_PTC_FRAG, 4, 36, 0x0000 }, > +     { CAT_CFN_DATA_PTC_INV, 1, 2, 0x0000 },
> +     { CAT_CFN_DATA_PTC_IP_PROT, 8, 40, 0x0000 },=
> +     { CAT_CFN_DATA_PTC_ISL, 2, 3, 0x0000 },
> +     { CAT_CFN_DATA_PTC_L2, 7, 12, 0x0000 },
> +     { CAT_CFN_DATA_PTC_L3, 3, 33, 0x0000 },
> +     { CAT_CFN_DATA_PTC_L4, 5, 48, 0x0000 },
> +     { CAT_CFN_DATA_PTC_MAC, 5, 7, 0x0000 },
> +     { CAT_CFN_DATA_PTC_MPLS, 8, 25, 0x0000 }, > +     { CAT_CFN_DATA_PTC_TNL_FRAG, 4, 81, 0x0000 }= ,
> +     { CAT_CFN_DATA_PTC_TNL_IP_PROT, 8, 85, 0x000= 0 },
> +     { CAT_CFN_DATA_PTC_TNL_L2, 2, 64, 0x0000 },<= br> > +     { CAT_CFN_DATA_PTC_TNL_L3, 3, 78, 0x0000 },<= br> > +     { CAT_CFN_DATA_PTC_TNL_L4, 5, 93, 0x0000 },<= br> > +     { CAT_CFN_DATA_PTC_TNL_MPLS, 8, 70, 0x0000 }= ,
> +     { CAT_CFN_DATA_PTC_TNL_VLAN, 4, 66, 0x0000 }= ,
> +     { CAT_CFN_DATA_PTC_TUNNEL, 11, 53, 0x0000 },=
> +     { CAT_CFN_DATA_PTC_VLAN, 4, 21, 0x0000 }, > +     { CAT_CFN_DATA_PTC_VNTAG, 2, 19, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cat_cot_ctrl_fields[] =3D {
> +     { CAT_COT_CTRL_ADR, 6, 0, 0x0000 },
> +     { CAT_COT_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cot_data_fields[] =3D {
> +     { CAT_COT_DATA_COLOR, 32, 0, 0x0000 },
> +     { CAT_COT_DATA_KM, 4, 32, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cte_ctrl_fields[] =3D {
> +     { CAT_CTE_CTRL_ADR, 6, 0, 0x0000 },
> +     { CAT_CTE_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cte_data_fields[] =3D {
> +     { CAT_CTE_DATA_COL_ENABLE, 1, 0, 0x0000 }, {=
> CAT_CTE_DATA_COR_ENABLE, 1, 1, 0x0000 },
> +     { CAT_CTE_DATA_EPP_ENABLE, 1, 9, 0x0000 }, {=
> CAT_CTE_DATA_HSH_ENABLE, 1, 2, 0x0000 },
> +     { CAT_CTE_DATA_HST_ENABLE, 1, 8, 0x0000 }, {=
> CAT_CTE_DATA_IPF_ENABLE, 1, 4, 0x0000 },
> +     { CAT_CTE_DATA_MSK_ENABLE, 1, 7, 0x0000 }, {=
> CAT_CTE_DATA_PDB_ENABLE, 1, 6, 0x0000 },
> +     { CAT_CTE_DATA_QSL_ENABLE, 1, 3, 0x0000 }, {=
> CAT_CTE_DATA_SLC_ENABLE, 1, 5, 0x0000 },
> +     { CAT_CTE_DATA_TPE_ENABLE, 1, 10, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s cat_cts_ctrl_fields[] =3D {
> +     { CAT_CTS_CTRL_ADR, 9, 0, 0x0000 },
> +     { CAT_CTS_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_cts_data_fields[] =3D {
> +     { CAT_CTS_DATA_CAT_A, 6, 0, 0x0000 },
> +     { CAT_CTS_DATA_CAT_B, 6, 6, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_dct_ctrl_fields[] =3D {
> +     { CAT_DCT_CTRL_ADR, 13, 0, 0x0000 },
> +     { CAT_DCT_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_dct_data_fields[] =3D {
> +     { CAT_DCT_DATA_RES, 16, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_dct_sel_fields[] =3D {
> +     { CAT_DCT_SEL_LU, 2, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_exo_ctrl_fields[] =3D {
> +     { CAT_EXO_CTRL_ADR, 2, 0, 0x0000 },
> +     { CAT_EXO_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_exo_data_fields[] =3D {
> +     { CAT_EXO_DATA_DYN, 5, 0, 0x0000 },
> +     { CAT_EXO_DATA_OFS, 11, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_fte0_ctrl_fields[] =3D {
> +     { CAT_FTE0_CTRL_ADR, 9, 0, 0x0000 },
> +     { CAT_FTE0_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_fte0_data_fields[] =3D {
> +     { CAT_FTE0_DATA_ENABLE, 8, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_fte1_ctrl_fields[] =3D {
> +     { CAT_FTE1_CTRL_ADR, 9, 0, 0x0000 },
> +     { CAT_FTE1_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_fte1_data_fields[] =3D {
> +     { CAT_FTE1_DATA_ENABLE, 8, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_join_fields[] =3D {
> +     { CAT_JOIN_J1, 2, 0, 0x0000 },
> +     { CAT_JOIN_J2, 1, 8, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kcc_ctrl_fields[] =3D {
> +     { CAT_KCC_CTRL_ADR, 11, 0, 0x0000 },
> +     { CAT_KCC_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kcc_data_fields[] =3D {
> +     { CAT_KCC_DATA_CATEGORY, 8, 64, 0x0000 }, > +     { CAT_KCC_DATA_ID, 12, 72, 0x0000 },
> +     { CAT_KCC_DATA_KEY, 64, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kce0_ctrl_fields[] =3D {
> +     { CAT_KCE0_CTRL_ADR, 3, 0, 0x0000 },
> +     { CAT_KCE0_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kce0_data_fields[] =3D {
> +     { CAT_KCE0_DATA_ENABLE, 8, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kce1_ctrl_fields[] =3D {
> +     { CAT_KCE1_CTRL_ADR, 3, 0, 0x0000 },
> +     { CAT_KCE1_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kce1_data_fields[] =3D {
> +     { CAT_KCE1_DATA_ENABLE, 8, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kcs0_ctrl_fields[] =3D {
> +     { CAT_KCS0_CTRL_ADR, 6, 0, 0x0000 },
> +     { CAT_KCS0_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kcs0_data_fields[] =3D {
> +     { CAT_KCS0_DATA_CATEGORY, 6, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cat_kcs1_ctrl_fields[] =3D {
> +     { CAT_KCS1_CTRL_ADR, 6, 0, 0x0000 },
> +     { CAT_KCS1_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_kcs1_data_fields[] =3D {
> +     { CAT_KCS1_DATA_CATEGORY, 6, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cat_len_ctrl_fields[] =3D {
> +     { CAT_LEN_CTRL_ADR, 3, 0, 0x0000 },
> +     { CAT_LEN_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_len_data_fields[] =3D {
> +     { CAT_LEN_DATA_DYN1, 5, 28, 0x0000 }, { CAT_= LEN_DATA_DYN2, 5,
> 33, 0x0000 },
> +     { CAT_LEN_DATA_INV, 1, 38, 0x0000 }, { CAT_L= EN_DATA_LOWER, 14,
> 0, 0x0000 },
> +     { CAT_LEN_DATA_UPPER, 14, 14, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_rck_ctrl_fields[] =3D {
> +     { CAT_RCK_CTRL_ADR, 8, 0, 0x0000 },
> +     { CAT_RCK_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s cat_rck_data_fields[] =3D {
> +     { CAT_RCK_DATA_CM0U, 1, 1, 0x0000 }, { CAT_R= CK_DATA_CM1U, 1,
> 5, 0x0000 },
> +     { CAT_RCK_DATA_CM2U, 1, 9, 0x0000 }, { CAT_R= CK_DATA_CM3U, 1,
> 13, 0x0000 },
> +     { CAT_RCK_DATA_CM4U, 1, 17, 0x0000 }, { CAT_= RCK_DATA_CM5U, 1,
> 21, 0x0000 },
> +     { CAT_RCK_DATA_CM6U, 1, 25, 0x0000 }, { CAT_= RCK_DATA_CM7U, 1,
> 29, 0x0000 },
> +     { CAT_RCK_DATA_CML0, 1, 0, 0x0000 }, { CAT_R= CK_DATA_CML1, 1, 4,
> 0x0000 },
> +     { CAT_RCK_DATA_CML2, 1, 8, 0x0000 }, { CAT_R= CK_DATA_CML3, 1,
> 12, 0x0000 },
> +     { CAT_RCK_DATA_CML4, 1, 16, 0x0000 }, { CAT_= RCK_DATA_CML5, 1,
> 20, 0x0000 },
> +     { CAT_RCK_DATA_CML6, 1, 24, 0x0000 }, { CAT_= RCK_DATA_CML7, 1,
> 28, 0x0000 },
> +     { CAT_RCK_DATA_SEL0, 1, 2, 0x0000 }, { CAT_R= CK_DATA_SEL1, 1, 6,
> 0x0000 },
> +     { CAT_RCK_DATA_SEL2, 1, 10, 0x0000 }, { CAT_= RCK_DATA_SEL3, 1, 14,
> 0x0000 },
> +     { CAT_RCK_DATA_SEL4, 1, 18, 0x0000 }, { CAT_= RCK_DATA_SEL5, 1, 22,
> 0x0000 },
> +     { CAT_RCK_DATA_SEL6, 1, 26, 0x0000 }, { CAT_= RCK_DATA_SEL7, 1, 30,
> 0x0000 },
> +     { CAT_RCK_DATA_SEU0, 1, 3, 0x0000 }, { CAT_R= CK_DATA_SEU1, 1, 7,
> 0x0000 },
> +     { CAT_RCK_DATA_SEU2, 1, 11, 0x0000 }, { CAT_= RCK_DATA_SEU3, 1,
> 15, 0x0000 },
> +     { CAT_RCK_DATA_SEU4, 1, 19, 0x0000 }, { CAT_= RCK_DATA_SEU5, 1,
> 23, 0x0000 },
> +     { CAT_RCK_DATA_SEU6, 1, 27, 0x0000 }, { CAT_= RCK_DATA_SEU7, 1,
> 31, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s cat_registers[] =3D {
> +     { CAT_CCT_CTRL, 30, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cct_ctrl_fields },
> +     { CAT_CCT_DATA, 31, 36, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cct_data_fields },
> +     { CAT_CFN_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cfn_ctrl_fields },
> +     { CAT_CFN_DATA, 11, 179, NTHW_FPGA_REG_TYPE_= WO, 0, 44,
> cat_cfn_data_fields },
> +     { CAT_COT_CTRL, 28, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cot_ctrl_fields },
> +     { CAT_COT_DATA, 29, 36, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cot_data_fields },
> +     { CAT_CTE_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cte_ctrl_fields },
> +     { CAT_CTE_DATA, 25, 11, NTHW_FPGA_REG_TYPE_W= O, 0, 11,
> cat_cte_data_fields },
> +     { CAT_CTS_CTRL, 26, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cts_ctrl_fields },
> +     { CAT_CTS_DATA, 27, 12, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_cts_data_fields },
> +     { CAT_DCT_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> cat_dct_ctrl_fields },
> +     { CAT_DCT_DATA, 7, 16, NTHW_FPGA_REG_TYPE_WO= , 0, 1,
> cat_dct_data_fields },
> +     { CAT_DCT_SEL, 4, 2, NTHW_FPGA_REG_TYPE_WO, = 0, 1,
> cat_dct_sel_fields },
> +     { CAT_EXO_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> cat_exo_ctrl_fields },
> +     { CAT_EXO_DATA, 1, 27, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> cat_exo_data_fields },
> +     { CAT_FTE0_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_fte0_ctrl_fields },
> +     { CAT_FTE0_DATA, 17, 8, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_fte0_data_fields },
> +     { CAT_FTE1_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_fte1_ctrl_fields },
> +     { CAT_FTE1_DATA, 23, 8, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_fte1_data_fields },
> +     { CAT_JOIN, 5, 9, NTHW_FPGA_REG_TYPE_WO, 0, = 2, cat_join_fields },
> +     { CAT_KCC_CTRL, 32, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> cat_kcc_ctrl_fields },
> +     { CAT_KCC_DATA, 33, 84, NTHW_FPGA_REG_TYPE_W= O, 0, 3,
> cat_kcc_data_fields },
> +     { CAT_KCE0_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_kce0_ctrl_fields },
> +     { CAT_KCE0_DATA, 13, 8, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_kce0_data_fields },
> +     { CAT_KCE1_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_kce1_ctrl_fields },
> +     { CAT_KCE1_DATA, 19, 8, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_kce1_data_fields },
> +     { CAT_KCS0_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_kcs0_ctrl_fields },
> +     { CAT_KCS0_DATA, 15, 6, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_kcs0_data_fields },
> +     { CAT_KCS1_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 2,
> cat_kcs1_ctrl_fields },
> +     { CAT_KCS1_DATA, 21, 6, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> cat_kcs1_data_fields },
> +     { CAT_LEN_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> cat_len_ctrl_fields },
> +     { CAT_LEN_DATA, 9, 39, NTHW_FPGA_REG_TYPE_WO= , 0, 5,
> cat_len_data_fields },
> +     { CAT_RCK_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> cat_rck_ctrl_fields },
> +     { CAT_RCK_DATA, 3, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 32,
> cat_rck_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s cpy_packet_reader0_ctrl_fields[] =3D {<= br> > +     { CPY_PACKET_READER0_CTRL_ADR, 4, 0, 0x0000 = },
> +     { CPY_PACKET_READER0_CTRL_CNT, 16, 16, 0x000= 0 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_packet_reader0_data_fields[] =3D {<= br> > +     { CPY_PACKET_READER0_DATA_DYN, 5, 10, 0x0000= },
> +     { CPY_PACKET_READER0_DATA_OFS, 10, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer0_ctrl_fields[] =3D {
> +     { CPY_WRITER0_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER0_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer0_data_fields[] =3D {
> +     { CPY_WRITER0_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER0_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER0_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER0_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER0_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer0_mask_ctrl_fields[] =3D { > +     { CPY_WRITER0_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER0_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer0_mask_data_fields[] =3D { > +     { CPY_WRITER0_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer1_ctrl_fields[] =3D {
> +     { CPY_WRITER1_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER1_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer1_data_fields[] =3D {
> +     { CPY_WRITER1_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER1_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER1_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER1_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER1_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer1_mask_ctrl_fields[] =3D { > +     { CPY_WRITER1_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER1_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer1_mask_data_fields[] =3D { > +     { CPY_WRITER1_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer2_ctrl_fields[] =3D {
> +     { CPY_WRITER2_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER2_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer2_data_fields[] =3D {
> +     { CPY_WRITER2_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER2_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER2_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER2_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER2_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer2_mask_ctrl_fields[] =3D { > +     { CPY_WRITER2_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER2_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer2_mask_data_fields[] =3D { > +     { CPY_WRITER2_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer3_ctrl_fields[] =3D {
> +     { CPY_WRITER3_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER3_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer3_data_fields[] =3D {
> +     { CPY_WRITER3_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER3_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER3_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER3_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER3_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer3_mask_ctrl_fields[] =3D { > +     { CPY_WRITER3_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER3_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer3_mask_data_fields[] =3D { > +     { CPY_WRITER3_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer4_ctrl_fields[] =3D {
> +     { CPY_WRITER4_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER4_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer4_data_fields[] =3D {
> +     { CPY_WRITER4_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER4_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER4_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER4_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER4_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer4_mask_ctrl_fields[] =3D { > +     { CPY_WRITER4_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER4_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer4_mask_data_fields[] =3D { > +     { CPY_WRITER4_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer5_ctrl_fields[] =3D {
> +     { CPY_WRITER5_CTRL_ADR, 4, 0, 0x0000 },
> +     { CPY_WRITER5_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s cpy_writer5_data_fields[] =3D {
> +     { CPY_WRITER5_DATA_DYN, 5, 17, 0x0000 }, { > CPY_WRITER5_DATA_LEN, 5, 22, 0x0000 },
> +     { CPY_WRITER5_DATA_MASK_POINTER, 4, 27, 0x00= 00 }, {
> CPY_WRITER5_DATA_OFS, 14, 3, 0x0000 },
> +     { CPY_WRITER5_DATA_READER_SELECT, 3, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer5_mask_ctrl_fields[] =3D { > +     { CPY_WRITER5_MASK_CTRL_ADR, 4, 0, 0x0000 },=
> +     { CPY_WRITER5_MASK_CTRL_CNT, 16, 16, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s cpy_writer5_mask_data_fields[] =3D { > +     { CPY_WRITER5_MASK_DATA_BYTE_MASK, 16, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_register_init_s cpy_registers[] =3D {
> +     {
> +           &nb= sp; CPY_PACKET_READER0_CTRL, 24, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_packet_reader0_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_PACKET_READER0_DATA, 25, 15,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_packet_reader0_data_fields
> +     },
> +     { CPY_WRITER0_CTRL, 0, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 2,
> cpy_writer0_ctrl_fields },
> +     { CPY_WRITER0_DATA, 1, 31, NTHW_FPGA_REG_TYP= E_WO, 0, 5,
> cpy_writer0_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER0_MASK_CTRL, 2, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer0_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER0_MASK_DATA, 3, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer0_mask_data_fields
> +     },
> +     { CPY_WRITER1_CTRL, 4, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 2,
> cpy_writer1_ctrl_fields },
> +     { CPY_WRITER1_DATA, 5, 31, NTHW_FPGA_REG_TYP= E_WO, 0, 5,
> cpy_writer1_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER1_MASK_CTRL, 6, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer1_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER1_MASK_DATA, 7, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer1_mask_data_fields
> +     },
> +     { CPY_WRITER2_CTRL, 8, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 2,
> cpy_writer2_ctrl_fields },
> +     { CPY_WRITER2_DATA, 9, 31, NTHW_FPGA_REG_TYP= E_WO, 0, 5,
> cpy_writer2_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER2_MASK_CTRL, 10, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer2_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER2_MASK_DATA, 11, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer2_mask_data_fields
> +     },
> +     { CPY_WRITER3_CTRL, 12, 32, NTHW_FPGA_REG_TY= PE_WO, 0, 2,
> cpy_writer3_ctrl_fields },
> +     { CPY_WRITER3_DATA, 13, 31, NTHW_FPGA_REG_TY= PE_WO, 0, 5,
> cpy_writer3_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER3_MASK_CTRL, 14, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer3_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER3_MASK_DATA, 15, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer3_mask_data_fields
> +     },
> +     { CPY_WRITER4_CTRL, 16, 32, NTHW_FPGA_REG_TY= PE_WO, 0, 2,
> cpy_writer4_ctrl_fields },
> +     { CPY_WRITER4_DATA, 17, 31, NTHW_FPGA_REG_TY= PE_WO, 0, 5,
> cpy_writer4_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER4_MASK_CTRL, 18, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer4_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER4_MASK_DATA, 19, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer4_mask_data_fields
> +     },
> +     { CPY_WRITER5_CTRL, 20, 32, NTHW_FPGA_REG_TY= PE_WO, 0, 2,
> cpy_writer5_ctrl_fields },
> +     { CPY_WRITER5_DATA, 21, 31, NTHW_FPGA_REG_TY= PE_WO, 0, 5,
> cpy_writer5_data_fields },
> +     {
> +           &nb= sp; CPY_WRITER5_MASK_CTRL, 22, 32,
> NTHW_FPGA_REG_TYPE_WO, 0, 2,
> +           &nb= sp; cpy_writer5_mask_ctrl_fields
> +     },
> +     {
> +           &nb= sp; CPY_WRITER5_MASK_DATA, 23, 16,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; cpy_writer5_mask_data_fields
> +     },
> +};
> +
> +static nthw_fpga_field_init_s csu_rcp_ctrl_fields[] =3D {
> +     { CSU_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { CSU_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s csu_rcp_data_fields[] =3D {
> +     { CSU_RCP_DATA_IL3_CMD, 2, 5, 0x0000 },
> +     { CSU_RCP_DATA_IL4_CMD, 3, 7, 0x0000 },
> +     { CSU_RCP_DATA_OL3_CMD, 2, 0, 0x0000 },
> +     { CSU_RCP_DATA_OL4_CMD, 3, 2, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s csu_registers[] =3D {
> +     { CSU_RCP_CTRL, 1, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> csu_rcp_ctrl_fields },
> +     { CSU_RCP_DATA, 2, 10, NTHW_FPGA_REG_TYPE_WO= , 0, 4,
> csu_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] =3D {
> +     { DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_am_data_fields[] =3D {
> +     { DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, {<= br> > DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },
> +     { DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS= _RX_AM_DATA_INT,
> 1, 74, 0x0000 },
> +     { DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_control_fields[] =3D {
> +     { DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CO= NTROL_AMS, 4, 8, 8
> },
> +     { DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CON= TROL_QE, 1, 17, 0 },
> +     { DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_C= ONTROL_UWS, 4,
> 13, 5 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] =3D {
> +     { DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] =3D {
> +     { DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS= _RX_DR_DATA_HDR,
> 1, 88, 0x0000 },
> +     { DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS= _RX_DR_DATA_PCKED,
> 1, 87, 0x0000 },
> +     { DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_idle_fields[] =3D {
> +     { DBS_RX_IDLE_BUSY, 1, 8, 0 },
> +     { DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },
> +     { DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_init_fields[] =3D {
> +     { DBS_RX_INIT_BUSY, 1, 8, 0 },
> +     { DBS_RX_INIT_INIT, 1, 0, 0x0000 },
> +     { DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_init_val_fields[] =3D {
> +     { DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },
> +     { DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_ptr_fields[] =3D {
> +     { DBS_RX_PTR_PTR, 16, 0, 0x0000 },
> +     { DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },
> +     { DBS_RX_PTR_VALID, 1, 23, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] =3D {
> +     { DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] =3D {
> +     { DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS= _RX_UW_DATA_HID,
> 8, 64, 0x0000 },
> +     { DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS= _RX_UW_DATA_ISTK,
> 1, 92, 0x0000 },
> +     { DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { > DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },
> +     { DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] =3D {
> +     { DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_am_data_fields[] =3D {
> +     { DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, {<= br> > DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },
> +     { DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS= _TX_AM_DATA_INT,
> 1, 74, 0x0000 },
> +     { DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_control_fields[] =3D {
> +     { DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CO= NTROL_AMS, 4, 8, 5
> },
> +     { DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CON= TROL_QE, 1, 17, 0 },
> +     { DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_C= ONTROL_UWS, 4,
> 13, 8 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] =3D {
> +     { DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] =3D {
> +     { DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS= _TX_DR_DATA_HDR,
> 1, 88, 0x0000 },
> +     { DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS= _TX_DR_DATA_PCKED,
> 1, 87, 0x0000 },
> +     { DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DB= S_TX_DR_DATA_QS,
> 15, 72, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_idle_fields[] =3D {
> +     { DBS_TX_IDLE_BUSY, 1, 8, 0 },
> +     { DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },
> +     { DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_init_fields[] =3D {
> +     { DBS_TX_INIT_BUSY, 1, 8, 0 },
> +     { DBS_TX_INIT_INIT, 1, 0, 0x0000 },
> +     { DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_init_val_fields[] =3D {
> +     { DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },
> +     { DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_ptr_fields[] =3D {
> +     { DBS_TX_PTR_PTR, 16, 0, 0x0000 },
> +     { DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },
> +     { DBS_TX_PTR_VALID, 1, 23, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] =3D {
> +     { DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },
> +     { DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] =3D {
> +     { DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },
> +     { DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },
> +     { DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] =3D {
> +     { DBS_TX_QOS_RATE_DIV, 19, 16, 2 },
> +     { DBS_TX_QOS_RATE_MUL, 16, 0, 1 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] =3D {
> +     { DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] =3D {
> +     { DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] =3D {
> +     { DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },
> +     { DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] =3D {
> +     { DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS= _TX_UW_DATA_HID,
> 8, 64, 0x0000 },
> +     { DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS= _TX_UW_DATA_INT,
> 1, 88, 0x0000 },
> +     { DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { > DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },
> +     { DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS= _TX_UW_DATA_VEC,
> 3, 89, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s dbs_registers[] =3D {
> +     { DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_rx_am_ctrl_fields },
> +     { DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE= _WO, 0, 5,
> dbs_rx_am_data_fields },
> +     { DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_= RW, 43008, 6,
> dbs_rx_control_fields },
> +     { DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_rx_dr_ctrl_fields },
> +     { DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE= _WO, 0, 5,
> dbs_rx_dr_data_fields },
> +     { DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_rx_idle_fields },
> +     { DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_rx_init_fields },
> +     { DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_rx_init_val_fields },
> +     { DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_rx_ptr_fields },
> +     { DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_rx_uw_ctrl_fields },
> +     { DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE= _WO, 0, 7,
> dbs_rx_uw_data_fields },
> +     { DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_tx_am_ctrl_fields },
> +     { DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE= _WO, 0, 5,
> dbs_tx_am_data_fields },
> +     { DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_= RW, 66816, 6,
> dbs_tx_control_fields },
> +     { DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_tx_dr_ctrl_fields },
> +     { DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE= _WO, 0, 6,
> dbs_tx_dr_data_fields },
> +     { DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_tx_idle_fields },
> +     { DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_tx_init_fields },
> +     { DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_tx_init_val_fields },
> +     { DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 3,
> dbs_tx_ptr_fields },
> +     { DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 2,
> dbs_tx_qos_ctrl_fields },
> +     { DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYP= E_WO, 0, 3,
> dbs_tx_qos_data_fields },
> +     { DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYP= E_RW, 131073,
> 2, dbs_tx_qos_rate_fields },
> +     { DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_tx_qp_ctrl_fields },
> +     { DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_= WO, 0, 1,
> dbs_tx_qp_data_fields },
> +     { DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> dbs_tx_uw_ctrl_fields },
> +     { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE= _WO, 0, 8,
> dbs_tx_uw_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s flm_buf_ctrl_fields[] =3D {
> +     { FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 },<= br> > +     { FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 }, > +     { FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_control_fields[] =3D {
> +     { FLM_CONTROL_CRCRD, 1, 12, 0x0000 }, { FLM_= CONTROL_CRCWR,
> 1, 11, 0x0000 },
> +     { FLM_CONTROL_EAB, 5, 18, 0 }, { FLM_CONTROL= _ENABLE, 1, 0, 0 },
> +     { FLM_CONTROL_INIT, 1, 1, 0x0000 }, { FLM_CO= NTROL_LDS, 1, 2,
> 0x0000 },
> +     { FLM_CONTROL_LFS, 1, 3, 0x0000 }, { FLM_CON= TROL_LIS, 1, 4,
> 0x0000 },
> +     { FLM_CONTROL_PDS, 1, 9, 0x0000 }, { FLM_CON= TROL_PIS, 1, 10,
> 0x0000 },
> +     { FLM_CONTROL_RBL, 4, 13, 0 }, { FLM_CONTROL= _RDS, 1, 7, 0x0000
> },
> +     { FLM_CONTROL_RIS, 1, 8, 0x0000 }, {
> FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 },
> +     { FLM_CONTROL_UDS, 1, 5, 0x0000 }, { FLM_CON= TROL_UIS, 1, 6,
> 0x0000 },
> +     { FLM_CONTROL_WPD, 1, 17, 0 },
> +};
> +
> +static nthw_fpga_field_init_s flm_inf_data_fields[] =3D {
> +     { FLM_INF_DATA_BYTES, 64, 0, 0x0000 }, { FLM= _INF_DATA_CAUSE, 3,
> 264, 0x0000 },
> +     { FLM_INF_DATA_EOR, 1, 287, 0x0000 }, { FLM_= INF_DATA_ID, 72,
> 192, 0x0000 },
> +     { FLM_INF_DATA_PACKETS, 64, 64, 0x0000 }, { = FLM_INF_DATA_TS,
> 64, 128, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_load_aps_fields[] =3D {
> +     { FLM_LOAD_APS_APS, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_load_bin_fields[] =3D {
> +     { FLM_LOAD_BIN_BIN, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_load_lps_fields[] =3D {
> +     { FLM_LOAD_LPS_LPS, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_lrn_data_fields[] =3D {
> +     { FLM_LRN_DATA_ADJ, 32, 480, 0x0000 }, { FLM= _LRN_DATA_COLOR,
> 32, 448, 0x0000 },
> +     { FLM_LRN_DATA_DSCP, 6, 734, 0x0000 }, { FLM= _LRN_DATA_ENT, 1,
> 729, 0x0000 },
> +     { FLM_LRN_DATA_EOR, 1, 767, 0x0000 }, { FLM_= LRN_DATA_FILL, 12,
> 584, 0x0000 },
> +     { FLM_LRN_DATA_FT, 4, 596, 0x0000 }, { FLM_L= RN_DATA_FT_MBR, 4,
> 600, 0x0000 },
> +     { FLM_LRN_DATA_FT_MISS, 4, 604, 0x0000 }, { = FLM_LRN_DATA_ID,
> 72, 512, 0x0000 },
> +     { FLM_LRN_DATA_KID, 8, 328, 0x0000 }, { FLM_= LRN_DATA_MBR_ID1,
> 28, 608, 0x0000 },
> +     { FLM_LRN_DATA_MBR_ID2, 28, 636, 0x0000 }, {=
> FLM_LRN_DATA_MBR_ID3, 28, 664, 0x0000 },
> +     { FLM_LRN_DATA_MBR_ID4, 28, 692, 0x0000 }, {=
> FLM_LRN_DATA_NAT_EN, 1, 747, 0x0000 },
> +     { FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 }, {<= br> > FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 },
> +     { FLM_LRN_DATA_NOFI, 1, 752, 0x0000 }, { FLM= _LRN_DATA_OP, 4,
> 730, 0x0000 },
> +     { FLM_LRN_DATA_PRIO, 2, 727, 0x0000 }, { FLM= _LRN_DATA_PROT, 8,
> 320, 0x0000 },
> +     { FLM_LRN_DATA_QFI, 6, 740, 0x0000 }, { FLM_= LRN_DATA_QW0,
> 128, 192, 0x0000 },
> +     { FLM_LRN_DATA_QW4, 128, 64, 0x0000 }, { FLM= _LRN_DATA_RATE,
> 16, 416, 0x0000 },
> +     { FLM_LRN_DATA_RQI, 1, 746, 0x0000 }, {
> FLM_LRN_DATA_SCRUB_PROF, 4, 748, 0x0000 },
> +     { FLM_LRN_DATA_SIZE, 16, 432, 0x0000 }, { > FLM_LRN_DATA_STAT_PROF, 4, 723, 0x0000 },
> +     { FLM_LRN_DATA_SW8, 32, 32, 0x0000 }, { FLM_= LRN_DATA_SW9, 32,
> 0, 0x0000 },
> +     { FLM_LRN_DATA_TEID, 32, 368, 0x0000 }, { > FLM_LRN_DATA_VOL_IDX, 3, 720, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_prio_fields[] =3D {
> +     { FLM_PRIO_FT0, 4, 4, 1 }, { FLM_PRIO_FT1, 4= , 12, 1 }, {
> FLM_PRIO_FT2, 4, 20, 1 },
> +     { FLM_PRIO_FT3, 4, 28, 1 }, { FLM_PRIO_LIMIT= 0, 4, 0, 0 }, {
> FLM_PRIO_LIMIT1, 4, 8, 0 },
> +     { FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LI= MIT3, 4, 24, 0 },
> +};
> +
> +static nthw_fpga_field_init_s flm_pst_ctrl_fields[] =3D {
> +     { FLM_PST_CTRL_ADR, 4, 0, 0x0000 },
> +     { FLM_PST_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_pst_data_fields[] =3D {
> +     { FLM_PST_DATA_BP, 5, 0, 0x0000 },
> +     { FLM_PST_DATA_PP, 5, 5, 0x0000 },
> +     { FLM_PST_DATA_TP, 5, 10, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_rcp_ctrl_fields[] =3D {
> +     { FLM_RCP_CTRL_ADR, 5, 0, 0x0000 },
> +     { FLM_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_rcp_data_fields[] =3D {
> +     { FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x000= 0 },
> +     { FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 }, > +     { FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 }, > +     { FLM_RCP_DATA_IPN, 1, 386, 0x0000 },
> +     { FLM_RCP_DATA_KID, 8, 377, 0x0000 },
> +     { FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 },
> +     { FLM_RCP_DATA_MASK, 320, 57, 0x0000 },
> +     { FLM_RCP_DATA_OPN, 1, 385, 0x0000 },
> +     { FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 },
> +     { FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 },
> +     { FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 },
> +     { FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 },
> +     { FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 },
> +     { FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 },
> +     { FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 },
> +     { FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 },
> +     { FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 },
> +     { FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 },
> +     { FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_scan_fields[] =3D {
> +     { FLM_SCAN_I, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s flm_scrub_ctrl_fields[] =3D {
> +     { FLM_SCRUB_CTRL_ADR, 4, 0, 0x0000 },
> +     { FLM_SCRUB_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_scrub_data_fields[] =3D {
> +     { FLM_SCRUB_DATA_T, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s flm_status_fields[] =3D {
> +     { FLM_STATUS_CALIBDONE, 1, 0, 0x0000 }, { FL= M_STATUS_CRCERR, 1,
> 5, 0x0000 },
> +     { FLM_STATUS_CRITICAL, 1, 3, 0x0000 }, { FLM= _STATUS_EFT_BP, 1, 6,
> 0x0000 },
> +     { FLM_STATUS_IDLE, 1, 2, 0x0000 }, { FLM_STA= TUS_INITDONE, 1, 1,
> 0x0000 },
> +     { FLM_STATUS_PANIC, 1, 4, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_aul_done_fields[] =3D {
> +     { FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_aul_fail_fields[] =3D {
> +     { FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_aul_ignore_fields[] =3D {
> +     { FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_stat_csh_hit_fields[] =3D {
> +     { FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_csh_miss_fields[] =3D {
> +     { FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_csh_unh_fields[] =3D {
> +     { FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_cuc_move_fields[] =3D {
> +     { FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_cuc_start_fields[] =3D {
> +     { FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_flows_fields[] =3D {
> +     { FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_inf_done_fields[] =3D {
> +     { FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_inf_skip_fields[] =3D {
> +     { FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_lrn_done_fields[] =3D {
> +     { FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_lrn_fail_fields[] =3D {
> +     { FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_lrn_ignore_fields[] =3D {
> +     { FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_stat_pck_dis_fields[] =3D {
> +     { FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_pck_hit_fields[] =3D {
> +     { FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_pck_miss_fields[] =3D {
> +     { FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_pck_unh_fields[] =3D {
> +     { FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s flm_stat_prb_done_fields[] =3D {
> +     { FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_prb_ignore_fields[] =3D {
> +     { FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_stat_rel_done_fields[] =3D {
> +     { FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_rel_ignore_fields[] =3D {
> +     { FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_stat_sta_done_fields[] =3D {
> +     { FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_tul_done_fields[] =3D {
> +     { FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_unl_done_fields[] =3D {
> +     { FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s flm_stat_unl_ignore_fields[] =3D {
> +     { FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s flm_sta_data_fields[] =3D {
> +     { FLM_STA_DATA_EOR, 1, 95, 0x0000 }, { FLM_S= TA_DATA_ID, 72, 0,
> 0x0000 },
> +     { FLM_STA_DATA_LDS, 1, 72, 0x0000 }, { FLM_S= TA_DATA_LFS, 1, 73,
> 0x0000 },
> +     { FLM_STA_DATA_LIS, 1, 74, 0x0000 }, { FLM_S= TA_DATA_PDS, 1, 79,
> 0x0000 },
> +     { FLM_STA_DATA_PIS, 1, 80, 0x0000 }, { FLM_S= TA_DATA_RDS, 1, 77,
> 0x0000 },
> +     { FLM_STA_DATA_RIS, 1, 78, 0x0000 }, { FLM_S= TA_DATA_UDS, 1, 75,
> 0x0000 },
> +     { FLM_STA_DATA_UIS, 1, 76, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s flm_registers[] =3D {
> +     { FLM_BUF_CTRL, 14, 48, NTHW_FPGA_REG_TYPE_R= W, 0, 3,
> flm_buf_ctrl_fields },
> +     { FLM_CONTROL, 0, 28, NTHW_FPGA_REG_TYPE_MIX= ED, 134217728,
> 17, flm_control_fields },
> +     { FLM_INF_DATA, 16, 288, NTHW_FPGA_REG_TYPE_= RO, 0, 6,
> flm_inf_data_fields },
> +     { FLM_LOAD_APS, 5, 32, NTHW_FPGA_REG_TYPE_RO= , 0, 1,
> flm_load_aps_fields },
> +     { FLM_LOAD_BIN, 3, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 1,
> flm_load_bin_fields },
> +     { FLM_LOAD_LPS, 4, 32, NTHW_FPGA_REG_TYPE_RO= , 0, 1,
> flm_load_lps_fields },
> +     { FLM_LRN_DATA, 15, 768, NTHW_FPGA_REG_TYPE_= WO, 0, 34,
> flm_lrn_data_fields },
> +     { FLM_PRIO, 6, 32, NTHW_FPGA_REG_TYPE_WO, 26= 9488144, 8,
> flm_prio_fields },
> +     { FLM_PST_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> flm_pst_ctrl_fields },
> +     { FLM_PST_DATA, 13, 15, NTHW_FPGA_REG_TYPE_W= O, 0, 3,
> flm_pst_data_fields },
> +     { FLM_RCP_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> flm_rcp_ctrl_fields },
> +     { FLM_RCP_DATA, 9, 403, NTHW_FPGA_REG_TYPE_W= O, 0, 19,
> flm_rcp_data_fields },
> +     { FLM_SCAN, 2, 16, NTHW_FPGA_REG_TYPE_WO, 0,= 1,
> flm_scan_fields },
> +     { FLM_SCRUB_CTRL, 10, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> flm_scrub_ctrl_fields },
> +     { FLM_SCRUB_DATA, 11, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 1,
> flm_scrub_data_fields },
> +     { FLM_STATUS, 1, 12, NTHW_FPGA_REG_TYPE_MIXE= D, 0, 7,
> flm_status_fields },
> +     { FLM_STAT_AUL_DONE, 41, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_aul_done_fields },
> +     { FLM_STAT_AUL_FAIL, 43, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_aul_fail_fields },
> +     { FLM_STAT_AUL_IGNORE, 42, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> flm_stat_aul_ignore_fields },
> +     { FLM_STAT_CSH_HIT, 52, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> flm_stat_csh_hit_fields },
> +     { FLM_STAT_CSH_MISS, 53, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_csh_miss_fields },
> +     { FLM_STAT_CSH_UNH, 54, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> flm_stat_csh_unh_fields },
> +     { FLM_STAT_CUC_MOVE, 56, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_cuc_move_fields },
> +     { FLM_STAT_CUC_START, 55, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> flm_stat_cuc_start_fields },
> +     { FLM_STAT_FLOWS, 18, 32, NTHW_FPGA_REG_TYPE= _RO, 0, 1,
> flm_stat_flows_fields },
> +     { FLM_STAT_INF_DONE, 46, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_inf_done_fields },
> +     { FLM_STAT_INF_SKIP, 47, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_inf_skip_fields },
> +     { FLM_STAT_LRN_DONE, 32, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_lrn_done_fields },
> +     { FLM_STAT_LRN_FAIL, 34, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_lrn_fail_fields },
> +     { FLM_STAT_LRN_IGNORE, 33, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> flm_stat_lrn_ignore_fields },
> +     { FLM_STAT_PCK_DIS, 51, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> flm_stat_pck_dis_fields },
> +     { FLM_STAT_PCK_HIT, 48, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> flm_stat_pck_hit_fields },
> +     { FLM_STAT_PCK_MISS, 49, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_pck_miss_fields },
> +     { FLM_STAT_PCK_UNH, 50, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> flm_stat_pck_unh_fields },
> +     { FLM_STAT_PRB_DONE, 39, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_prb_done_fields },
> +     { FLM_STAT_PRB_IGNORE, 40, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> flm_stat_prb_ignore_fields },
> +     { FLM_STAT_REL_DONE, 37, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_rel_done_fields },
> +     { FLM_STAT_REL_IGNORE, 38, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> flm_stat_rel_ignore_fields },
> +     { FLM_STAT_STA_DONE, 45, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_sta_done_fields },
> +     { FLM_STAT_TUL_DONE, 44, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_tul_done_fields },
> +     { FLM_STAT_UNL_DONE, 35, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> flm_stat_unl_done_fields },
> +     { FLM_STAT_UNL_IGNORE, 36, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> flm_stat_unl_ignore_fields },
> +     { FLM_STA_DATA, 17, 96, NTHW_FPGA_REG_TYPE_R= O, 0, 11,
> flm_sta_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s gfg_burstsize0_fields[] =3D {
> +     { GFG_BURSTSIZE0_VAL, 24, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_burstsize1_fields[] =3D {
> +     { GFG_BURSTSIZE1_VAL, 24, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_ctrl0_fields[] =3D {
> +     { GFG_CTRL0_ENABLE, 1, 0, 0 },
> +     { GFG_CTRL0_MODE, 3, 1, 0 },
> +     { GFG_CTRL0_PRBS_EN, 1, 4, 0 },
> +     { GFG_CTRL0_SIZE, 14, 16, 64 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_ctrl1_fields[] =3D {
> +     { GFG_CTRL1_ENABLE, 1, 0, 0 },
> +     { GFG_CTRL1_MODE, 3, 1, 0 },
> +     { GFG_CTRL1_PRBS_EN, 1, 4, 0 },
> +     { GFG_CTRL1_SIZE, 14, 16, 64 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_run0_fields[] =3D {
> +     { GFG_RUN0_RUN, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_run1_fields[] =3D {
> +     { GFG_RUN1_RUN, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_sizemask0_fields[] =3D {
> +     { GFG_SIZEMASK0_VAL, 14, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_sizemask1_fields[] =3D {
> +     { GFG_SIZEMASK1_VAL, 14, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_streamid0_fields[] =3D {
> +     { GFG_STREAMID0_VAL, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gfg_streamid1_fields[] =3D {
> +     { GFG_STREAMID1_VAL, 8, 0, 1 },
> +};
> +
> +static nthw_fpga_register_init_s gfg_registers[] =3D {
> +     { GFG_BURSTSIZE0, 3, 24, NTHW_FPGA_REG_TYPE_= WO, 0, 1,
> gfg_burstsize0_fields },
> +     { GFG_BURSTSIZE1, 8, 24, NTHW_FPGA_REG_TYPE_= WO, 0, 1,
> gfg_burstsize1_fields },
> +     { GFG_CTRL0, 0, 30, NTHW_FPGA_REG_TYPE_WO, 4= 194304, 4,
> gfg_ctrl0_fields },
> +     { GFG_CTRL1, 5, 30, NTHW_FPGA_REG_TYPE_WO, 4= 194304, 4,
> gfg_ctrl1_fields },
> +     { GFG_RUN0, 1, 1, NTHW_FPGA_REG_TYPE_WO, 0, = 1, gfg_run0_fields
> },
> +     { GFG_RUN1, 6, 1, NTHW_FPGA_REG_TYPE_WO, 0, = 1, gfg_run1_fields
> },
> +     { GFG_SIZEMASK0, 4, 14, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> gfg_sizemask0_fields },
> +     { GFG_SIZEMASK1, 9, 14, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> gfg_sizemask1_fields },
> +     { GFG_STREAMID0, 2, 8, NTHW_FPGA_REG_TYPE_WO= , 0, 1,
> gfg_streamid0_fields },
> +     { GFG_STREAMID1, 7, 8, NTHW_FPGA_REG_TYPE_WO= , 1, 1,
> gfg_streamid1_fields },
> +};
> +
> +static nthw_fpga_field_init_s gmf_ctrl_fields[] =3D {
> +     { GMF_CTRL_ENABLE, 1, 0, 0 },
> +     { GMF_CTRL_FCS_ALWAYS, 1, 1, 0 },
> +     { GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 }= ,
> +     { GMF_CTRL_IFG_ENABLE, 1, 2, 0 },
> +     { GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 },
> +     { GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 = },
> +     { GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK,= 1, 6, 0 },
> +     { GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 }, > +     { GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 },
> +     { GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 }, > +};
> +
> +static nthw_fpga_field_init_s gmf_debug_lane_marker_fields[] =3D { > +     { GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0,= 16384 },
> +};
> +
> +static nthw_fpga_field_init_s gmf_ifg_max_adjust_slack_fields[] =3D {=
> +     { GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 }= ,
> +};
> +
> +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_fields[] =3D {<= br> > +     { GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 },=
> +};
> +
> +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_adjust_fields[]= =3D {
> +     { GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, = 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gmf_ifg_tx_now_on_ts_fields[] =3D {
> +     { GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gmf_speed_fields[] =3D {
> +     { GMF_SPEED_IFG_SPEED, 64, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gmf_stat_data_buffer_fields[] =3D {
> +     { GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s gmf_stat_max_delayed_pkt_fields[] =3D {=
> +     { GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s gmf_stat_next_pkt_fields[] =3D {
> +     { GMF_STAT_NEXT_PKT_NS, 64, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gmf_stat_sticky_fields[] =3D {
> +     { GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 = },
> +     { GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 }, > +};
> +
> +static nthw_fpga_field_init_s gmf_ts_inject_fields[] =3D {
> +     { GMF_TS_INJECT_OFFSET, 14, 0, 0 },
> +     { GMF_TS_INJECT_POS, 2, 14, 0 },
> +};
> +
> +static nthw_fpga_register_init_s gmf_registers[] =3D {
> +     { GMF_CTRL, 0, 10, NTHW_FPGA_REG_TYPE_WO, 0,= 10,
> gmf_ctrl_fields },
> +     {
> +           &nb= sp; GMF_DEBUG_LANE_MARKER, 7, 16,
> NTHW_FPGA_REG_TYPE_WO, 16384, 1,
> +           &nb= sp; gmf_debug_lane_marker_fields
> +     },
> +     {
> +           &nb= sp; GMF_IFG_MAX_ADJUST_SLACK, 4, 64,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; gmf_ifg_max_adjust_slack_fields
> +     },
> +     {
> +           &nb= sp; GMF_IFG_SET_CLOCK_DELTA, 2, 64,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; gmf_ifg_set_clock_delta_fields
> +     },
> +     {
> +           &nb= sp; GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64,
> NTHW_FPGA_REG_TYPE_WO, 0, 1,
> +           &nb= sp; gmf_ifg_set_clock_delta_adjust_fields
> +     },
> +     { GMF_IFG_TX_NOW_ON_TS, 5, 64, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, gmf_ifg_tx_now_on_ts_fields },
> +     { GMF_SPEED, 1, 64, NTHW_FPGA_REG_TYPE_WO, 0= , 1,
> gmf_speed_fields },
> +     { GMF_STAT_DATA_BUFFER, 9, 15, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> gmf_stat_data_buffer_fields },
> +     {
> +           &nb= sp; GMF_STAT_MAX_DELAYED_PKT, 11, 64,
> NTHW_FPGA_REG_TYPE_RC1, 0, 1,
> +           &nb= sp; gmf_stat_max_delayed_pkt_fields
> +     },
> +     { GMF_STAT_NEXT_PKT, 10, 64, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> gmf_stat_next_pkt_fields },
> +     { GMF_STAT_STICKY, 8, 2, NTHW_FPGA_REG_TYPE_= RC1, 0, 2,
> gmf_stat_sticky_fields },
> +     { GMF_TS_INJECT, 6, 16, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> gmf_ts_inject_fields },
> +};
> +
> +static nthw_fpga_field_init_s gpio_phy_cfg_fields[] =3D {
> +     { GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 }, { > GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 },
> +     { GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 }, {
> GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 },
> +     { GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 }, {<= br> > GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 },
> +     { GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 }, {
> GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 },
> +     { GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 }, {<= br> > GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 },
> +};
> +
> +static nthw_fpga_field_init_s gpio_phy_gpio_fields[] =3D {
> +     { GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 }, {<= br> > GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 },
> +     { GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 },= {
> GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 },
> +     { GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000= }, {
> GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 },
> +     { GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 },= {
> GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 },
> +     { GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000= }, {
> GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 },
> +};
> +
> +static nthw_fpga_register_init_s gpio_phy_registers[] =3D {
> +     { GPIO_PHY_CFG, 0, 10, NTHW_FPGA_REG_TYPE_RW= , 170, 10,
> gpio_phy_cfg_fields },
> +     { GPIO_PHY_GPIO, 1, 10, NTHW_FPGA_REG_TYPE_R= W, 17, 10,
> gpio_phy_gpio_fields },
> +};
> +
> +static nthw_fpga_field_init_s hfu_rcp_ctrl_fields[] =3D {
> +     { HFU_RCP_CTRL_ADR, 6, 0, 0x0000 },
> +     { HFU_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s hfu_rcp_data_fields[] =3D {
> +     { HFU_RCP_DATA_LEN_A_ADD_DYN, 5, 15, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_A_ADD_OFS, 8, 20, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_A_OL4LEN, 1, 1, 0x0000 },=
> +     { HFU_RCP_DATA_LEN_A_POS_DYN, 5, 2, 0x0000 }= ,
> +     { HFU_RCP_DATA_LEN_A_POS_OFS, 8, 7, 0x0000 }= ,
> +     { HFU_RCP_DATA_LEN_A_SUB_DYN, 5, 28, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_A_WR, 1, 0, 0x0000 },
> +     { HFU_RCP_DATA_LEN_B_ADD_DYN, 5, 47, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_B_ADD_OFS, 8, 52, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_B_POS_DYN, 5, 34, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_B_POS_OFS, 8, 39, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_B_SUB_DYN, 5, 60, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_B_WR, 1, 33, 0x0000 }, > +     { HFU_RCP_DATA_LEN_C_ADD_DYN, 5, 79, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_C_ADD_OFS, 8, 84, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_C_POS_DYN, 5, 66, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_C_POS_OFS, 8, 71, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_C_SUB_DYN, 5, 92, 0x0000 = },
> +     { HFU_RCP_DATA_LEN_C_WR, 1, 65, 0x0000 }, > +     { HFU_RCP_DATA_TTL_POS_DYN, 5, 98, 0x0000 },=
> +     { HFU_RCP_DATA_TTL_POS_OFS, 8, 103, 0x0000 }= ,
> +     { HFU_RCP_DATA_TTL_WR, 1, 97, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s hfu_registers[] =3D {
> +     { HFU_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> hfu_rcp_ctrl_fields },
> +     { HFU_RCP_DATA, 1, 111, NTHW_FPGA_REG_TYPE_W= O, 0, 22,
> hfu_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s hif_build_time_fields[] =3D {
> +     { HIF_BUILD_TIME_TIME, 32, 0, 1713859545 },<= br> > +};
> +
> +static nthw_fpga_field_init_s hif_config_fields[] =3D {
> +     { HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 },
> +     { HIF_CONFIG_MAX_READ, 3, 3, 0x0000 },
> +     { HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s hif_control_fields[] =3D {
> +     { HIF_CONTROL_BLESSED, 8, 4, 0 },
> +     { HIF_CONTROL_FSR, 1, 12, 1 },
> +     { HIF_CONTROL_WRAW, 4, 0, 1 },
> +};
> +
> +static nthw_fpga_field_init_s hif_prod_id_ex_fields[] =3D {
> +     { HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 },
> +     { HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 },<= br> > +     { HIF_PROD_ID_EX_RESERVED, 23, 8, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] =3D {
> +     { HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },<= br> > +     { HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 },
> +     { HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },
> +};
> +
> +static nthw_fpga_field_init_s hif_prod_id_msb_fields[] =3D {
> +     { HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 },
> +     { HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 },
> +};
> +
> +static nthw_fpga_field_init_s hif_sample_time_fields[] =3D {
> +     { HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s hif_status_fields[] =3D {
> +     { HIF_STATUS_RD_ERR, 1, 9, 0 },
> +     { HIF_STATUS_TAGS_IN_USE, 8, 0, 0 },
> +     { HIF_STATUS_WR_ERR, 1, 8, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_stat_ctrl_fields[] =3D {
> +     { HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 },
> +     { HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_stat_refclk_fields[] =3D {
> +     { HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_stat_rx_fields[] =3D {
> +     { HIF_STAT_RX_COUNTER, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_stat_tx_fields[] =3D {
> +     { HIF_STAT_TX_COUNTER, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s hif_test0_fields[] =3D {
> +     { HIF_TEST0_DATA, 32, 0, 287454020 },
> +};
> +
> +static nthw_fpga_field_init_s hif_test1_fields[] =3D {
> +     { HIF_TEST1_DATA, 32, 0, 2864434397 },
> +};
> +
> +static nthw_fpga_field_init_s hif_uuid0_fields[] =3D {
> +     { HIF_UUID0_UUID0, 32, 0, 1237800326 },
> +};
> +
> +static nthw_fpga_field_init_s hif_uuid1_fields[] =3D {
> +     { HIF_UUID1_UUID1, 32, 0, 3057550372 },
> +};
> +
> +static nthw_fpga_field_init_s hif_uuid2_fields[] =3D {
> +     { HIF_UUID2_UUID2, 32, 0, 2445752330 },
> +};
> +
> +static nthw_fpga_field_init_s hif_uuid3_fields[] =3D {
> +     { HIF_UUID3_UUID3, 32, 0, 1864147557 },
> +};
> +
> +static nthw_fpga_register_init_s hif_registers[] =3D {
> +     { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE= _RO,
> 1713859545, 1, hif_build_time_fields },
> +     { HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, = 0, 3,
> hif_config_fields },
> +     { HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MI= XED, 4097, 3,
> hif_control_fields },
> +     { HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYP= E_RO, 1, 3,
> hif_prod_id_ex_fields },
> +     { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE= _RO, 626734887,
> 3, hif_prod_id_lsb_fields },
> +     { HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE= _RO, 200, 2,
> hif_prod_id_msb_fields },
> +     { HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE= _WO, 0, 1,
> hif_sample_time_fields },
> +     { HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIX= ED, 0, 3,
> hif_status_fields },
> +     { HIF_STAT_CTRL, 64, 2, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> hif_stat_ctrl_fields },
> +     { HIF_STAT_REFCLK, 72, 32, NTHW_FPGA_REG_TYP= E_RO, 0, 1,
> hif_stat_refclk_fields },
> +     { HIF_STAT_RX, 88, 32, NTHW_FPGA_REG_TYPE_RO= , 0, 1,
> hif_stat_rx_fields },
> +     { HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO= , 0, 1,
> hif_stat_tx_fields },
> +     { HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, = 287454020, 1,
> hif_test0_fields },
> +     { HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, = 2864434397, 1,
> hif_test1_fields },
> +     { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO,= 1237800326, 1,
> hif_uuid0_fields },
> +     { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO,= 3057550372, 1,
> hif_uuid1_fields },
> +     { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO,= 2445752330, 1,
> hif_uuid2_fields },
> +     { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO,= 1864147557, 1,
> hif_uuid3_fields },
> +};
> +
> +static nthw_fpga_field_init_s hsh_rcp_ctrl_fields[] =3D {
> +     { HSH_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { HSH_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s hsh_rcp_data_fields[] =3D {
> +     { HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x000= 0 },
> +     { HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 }, > +     { HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 },<= br> > +     { HSH_RCP_DATA_K, 320, 422, 0x0000 },
> +     { HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 = },
> +     { HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 }= ,
> +     { HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 },
> +     { HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 },
> +     { HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 },
> +     { HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
> +     { HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 },
> +     { HSH_RCP_DATA_SEED, 32, 382, 0x0000 },
> +     { HSH_RCP_DATA_SORT, 2, 4, 0x0000 },
> +     { HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 },
> +     { HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 }, > +     { HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 },
> +     { HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 },
> +     { HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 },
> +     { HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 },
> +     { HSH_RCP_DATA_W9_P, 1, 60, 0x0000 },
> +     { HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 },
> +     { HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 },
> +     { HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 },=
> +};
> +
> +static nthw_fpga_register_init_s hsh_registers[] =3D {
> +     { HSH_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> hsh_rcp_ctrl_fields },
> +     { HSH_RCP_DATA, 1, 743, NTHW_FPGA_REG_TYPE_W= O, 0, 23,
> hsh_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s ifr_counters_ctrl_fields[] =3D {
> +     { IFR_COUNTERS_CTRL_ADR, 4, 0, 0x0000 },
> +     { IFR_COUNTERS_CTRL_CNT, 16, 16, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s ifr_counters_data_fields[] =3D {
> +     { IFR_COUNTERS_DATA_DROP, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s ifr_df_buf_ctrl_fields[] =3D {
> +     { IFR_DF_BUF_CTRL_AVAILABLE, 11, 0, 0x0000 }= ,
> +     { IFR_DF_BUF_CTRL_MTU_PROFILE, 16, 11, 0x000= 0 },
> +};
> +
> +static nthw_fpga_field_init_s ifr_df_buf_data_fields[] =3D {
> +     { IFR_DF_BUF_DATA_FIFO_DAT, 128, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s ifr_rcp_ctrl_fields[] =3D {
> +     { IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s ifr_rcp_data_fields[] =3D {
> +     { IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0x0000 }= , {
> IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 },
> +     { IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x0000 }, {=
> IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 },
> +     { IFR_RCP_DATA_MTU, 14, 2, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s ifr_registers[] =3D {
> +     { IFR_COUNTERS_CTRL, 4, 32, NTHW_FPGA_REG_TY= PE_WO, 0, 2,
> ifr_counters_ctrl_fields },
> +     { IFR_COUNTERS_DATA, 5, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> ifr_counters_data_fields },
> +     { IFR_DF_BUF_CTRL, 2, 27, NTHW_FPGA_REG_TYPE= _RO, 0, 2,
> ifr_df_buf_ctrl_fields },
> +     { IFR_DF_BUF_DATA, 3, 128, NTHW_FPGA_REG_TYP= E_RO, 0, 1,
> ifr_df_buf_data_fields },
> +     { IFR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> ifr_rcp_ctrl_fields },
> +     { IFR_RCP_DATA, 1, 18, NTHW_FPGA_REG_TYPE_WO= , 0, 5,
> ifr_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s iic_adr_fields[] =3D {
> +     { IIC_ADR_SLV_ADR, 7, 1, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_cr_fields[] =3D {
> +     { IIC_CR_EN, 1, 0, 0 }, { IIC_CR_GC_EN, 1, 6= , 0 }, { IIC_CR_MSMS, 1, 2,
> 0 },
> +     { IIC_CR_RST, 1, 7, 0 }, { IIC_CR_RSTA, 1, 5= , 0 }, { IIC_CR_TX, 1, 3, 0 },
> +     { IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RE= SET, 1, 1, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_dgie_fields[] =3D {
> +     { IIC_DGIE_GIE, 1, 31, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_gpo_fields[] =3D {
> +     { IIC_GPO_GPO_VAL, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_ier_fields[] =3D {
> +     { IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1= , 1, 0 }, { IIC_IER_INT2, 1, 2,
> 0 },
> +     { IIC_IER_INT3, 1, 3, 0 }, { IIC_IER_INT4, 1= , 4, 0 }, { IIC_IER_INT5, 1, 5,
> 0 },
> +     { IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1= , 7, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_isr_fields[] =3D {
> +     { IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1= , 1, 0 }, { IIC_ISR_INT2, 1, 2,
> 0 },
> +     { IIC_ISR_INT3, 1, 3, 0 }, { IIC_ISR_INT4, 1= , 4, 0 }, { IIC_ISR_INT5, 1, 5,
> 0 },
> +     { IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1= , 7, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_rx_fifo_fields[] =3D {
> +     { IIC_RX_FIFO_RXDATA, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_rx_fifo_ocy_fields[] =3D {
> +     { IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_rx_fifo_pirq_fields[] =3D {
> +     { IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_softr_fields[] =3D {
> +     { IIC_SOFTR_RKEY, 4, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s iic_sr_fields[] =3D {
> +     { IIC_SR_AAS, 1, 1, 0 }, { IIC_SR_ABGC, 1, 0= , 0 }, { IIC_SR_BB, 1, 2, 0 },
> +     { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 }, { IIC_SR_R= XFIFO_FULL, 1, 5, 0 }, {
> IIC_SR_SRW, 1, 3, 0 },
> +     { IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_T= XFIFO_FULL, 1, 4, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tbuf_fields[] =3D {
> +     { IIC_TBUF_TBUF_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_ten_adr_fields[] =3D {
> +     { IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_thddat_fields[] =3D {
> +     { IIC_THDDAT_THDDAT_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_thdsta_fields[] =3D {
> +     { IIC_THDSTA_THDSTA_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_thigh_fields[] =3D {
> +     { IIC_THIGH_THIGH_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tlow_fields[] =3D {
> +     { IIC_TLOW_TLOW_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tsudat_fields[] =3D {
> +     { IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tsusta_fields[] =3D {
> +     { IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tsusto_fields[] =3D {
> +     { IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tx_fifo_fields[] =3D {
> +     { IIC_TX_FIFO_START, 1, 8, 0 },
> +     { IIC_TX_FIFO_STOP, 1, 9, 0 },
> +     { IIC_TX_FIFO_TXDATA, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s iic_tx_fifo_ocy_fields[] =3D {
> +     { IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s iic_registers[] =3D {
> +     { IIC_ADR, 68, 8, NTHW_FPGA_REG_TYPE_RW, 0, = 1, iic_adr_fields },
> +     { IIC_CR, 64, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8= , iic_cr_fields },
> +     { IIC_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0,= 1, iic_dgie_fields },
> +     { IIC_GPO, 73, 1, NTHW_FPGA_REG_TYPE_RW, 0, = 1, iic_gpo_fields },
> +     { IIC_IER, 10, 8, NTHW_FPGA_REG_TYPE_RW, 0, = 8, iic_ier_fields },
> +     { IIC_ISR, 8, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8= , iic_isr_fields },
> +     { IIC_RX_FIFO, 67, 8, NTHW_FPGA_REG_TYPE_RO,= 0, 1,
> iic_rx_fifo_fields },
> +     { IIC_RX_FIFO_OCY, 70, 4, NTHW_FPGA_REG_TYPE= _RO, 0, 1,
> iic_rx_fifo_ocy_fields },
> +     { IIC_RX_FIFO_PIRQ, 72, 4, NTHW_FPGA_REG_TYP= E_RW, 0, 1,
> iic_rx_fifo_pirq_fields },
> +     { IIC_SOFTR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0= , 1, iic_softr_fields
> },
> +     { IIC_SR, 65, 8, NTHW_FPGA_REG_TYPE_RO, 192,= 8, iic_sr_fields },
> +     { IIC_TBUF, 78, 32, NTHW_FPGA_REG_TYPE_RW, 0= , 1, iic_tbuf_fields },
> +     { IIC_TEN_ADR, 71, 3, NTHW_FPGA_REG_TYPE_RO,= 0, 1,
> iic_ten_adr_fields },
> +     { IIC_THDDAT, 81, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> iic_thddat_fields },
> +     { IIC_THDSTA, 76, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> iic_thdsta_fields },
> +     { IIC_THIGH, 79, 32, NTHW_FPGA_REG_TYPE_RW, = 0, 1, iic_thigh_fields
> },
> +     { IIC_TLOW, 80, 32, NTHW_FPGA_REG_TYPE_RW, 0= , 1, iic_tlow_fields
> },
> +     { IIC_TSUDAT, 77, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> iic_tsudat_fields },
> +     { IIC_TSUSTA, 74, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> iic_tsusta_fields },
> +     { IIC_TSUSTO, 75, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> iic_tsusto_fields },
> +     { IIC_TX_FIFO, 66, 10, NTHW_FPGA_REG_TYPE_WO= , 0, 3,
> iic_tx_fifo_fields },
> +     { IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE= _RO, 0, 1,
> iic_tx_fifo_ocy_fields },
> +};
> +
> +static nthw_fpga_field_init_s ins_rcp_ctrl_fields[] =3D {
> +     { INS_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { INS_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s ins_rcp_data_fields[] =3D {
> +     { INS_RCP_DATA_DYN, 5, 0, 0x0000 },
> +     { INS_RCP_DATA_LEN, 8, 15, 0x0000 },
> +     { INS_RCP_DATA_OFS, 10, 5, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s ins_registers[] =3D {
> +     { INS_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> ins_rcp_ctrl_fields },
> +     { INS_RCP_DATA, 1, 23, NTHW_FPGA_REG_TYPE_WO= , 0, 3,
> ins_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s km_cam_ctrl_fields[] =3D {
> +     { KM_CAM_CTRL_ADR, 13, 0, 0x0000 },
> +     { KM_CAM_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_cam_data_fields[] =3D {
> +     { KM_CAM_DATA_FT0, 4, 192, 0x0000 }, { KM_CA= M_DATA_FT1, 4,
> 196, 0x0000 },
> +     { KM_CAM_DATA_FT2, 4, 200, 0x0000 }, { KM_CA= M_DATA_FT3, 4,
> 204, 0x0000 },
> +     { KM_CAM_DATA_FT4, 4, 208, 0x0000 }, { KM_CA= M_DATA_FT5, 4,
> 212, 0x0000 },
> +     { KM_CAM_DATA_W0, 32, 0, 0x0000 }, { KM_CAM_= DATA_W1, 32, 32,
> 0x0000 },
> +     { KM_CAM_DATA_W2, 32, 64, 0x0000 }, { KM_CAM= _DATA_W3, 32,
> 96, 0x0000 },
> +     { KM_CAM_DATA_W4, 32, 128, 0x0000 }, { KM_CA= M_DATA_W5, 32,
> 160, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_rcp_ctrl_fields[] =3D {
> +     { KM_RCP_CTRL_ADR, 5, 0, 0x0000 },
> +     { KM_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_rcp_data_fields[] =3D {
> +     { KM_RCP_DATA_BANK_A, 12, 694, 0x0000 }, { > KM_RCP_DATA_BANK_B, 12, 706, 0x0000 },
> +     { KM_RCP_DATA_DUAL, 1, 651, 0x0000 }, {
> KM_RCP_DATA_DW0_B_DYN, 5, 729, 0x0000 },
> +     { KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 }, {=
> KM_RCP_DATA_DW10_DYN, 5, 55, 0x0000 },
> +     { KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 }, { > KM_RCP_DATA_DW10_SEL_A, 2, 68, 0x0000 },
> +     { KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 }, {=
> KM_RCP_DATA_DW2_B_DYN, 5, 742, 0x0000 },
> +     { KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 }, {=
> KM_RCP_DATA_DW8_DYN, 5, 36, 0x0000 },
> +     { KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 }, { > KM_RCP_DATA_DW8_SEL_A, 3, 49, 0x0000 },
> +     { KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 }, {<= br> > KM_RCP_DATA_EL_A, 4, 653, 0x0000 },
> +     { KM_RCP_DATA_EL_B, 3, 657, 0x0000 }, { KM_R= CP_DATA_FTM_A,
> 16, 662, 0x0000 },
> +     { KM_RCP_DATA_FTM_B, 16, 678, 0x0000 }, { > KM_RCP_DATA_INFO_A, 1, 660, 0x0000 },
> +     { KM_RCP_DATA_INFO_B, 1, 661, 0x0000 }, { > KM_RCP_DATA_KEYWAY_A, 1, 725, 0x0000 },
> +     { KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 }, {<= br> > KM_RCP_DATA_KL_A, 4, 718, 0x0000 },
> +     { KM_RCP_DATA_KL_B, 3, 722, 0x0000 }, { KM_R= CP_DATA_MASK_A,
> 384, 75, 0x0000 },
> +     { KM_RCP_DATA_MASK_B, 192, 459, 0x0000 }, {<= br> > KM_RCP_DATA_PAIRED, 1, 652, 0x0000 },
> +     { KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 }, {
> KM_RCP_DATA_QW0_OFS, 8, 5, 0x0000 },
> +     { KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 }, {<= br> > KM_RCP_DATA_QW0_SEL_B, 3, 16, 0x0000 },
> +     { KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 }, { > KM_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
> +     { KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 }, {<= br> > KM_RCP_DATA_QW4_SEL_B, 2, 34, 0x0000 },
> +     { KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 }, {=
> KM_RCP_DATA_SW4_B_OFS, 8, 760, 0x0000 },
> +     { KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 }, {=
> KM_RCP_DATA_SW5_B_OFS, 8, 773, 0x0000 },
> +     { KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 }, { > KM_RCP_DATA_SWX_SEL_A, 1, 73, 0x0000 },
> +     { KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 }, {<= br> > KM_RCP_DATA_SYNERGY_MODE, 2, 727, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_status_fields[] =3D {
> +     { KM_STATUS_TCQ_RDY, 1, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tcam_ctrl_fields[] =3D {
> +     { KM_TCAM_CTRL_ADR, 14, 0, 0x0000 },
> +     { KM_TCAM_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tcam_data_fields[] =3D {
> +     { KM_TCAM_DATA_T, 72, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tci_ctrl_fields[] =3D {
> +     { KM_TCI_CTRL_ADR, 10, 0, 0x0000 },
> +     { KM_TCI_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tci_data_fields[] =3D {
> +     { KM_TCI_DATA_COLOR, 32, 0, 0x0000 },
> +     { KM_TCI_DATA_FT, 4, 32, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tcq_ctrl_fields[] =3D {
> +     { KM_TCQ_CTRL_ADR, 7, 0, 0x0000 },
> +     { KM_TCQ_CTRL_CNT, 5, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s km_tcq_data_fields[] =3D {
> +     { KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 }, > +     { KM_TCQ_DATA_QUAL, 3, 12, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s km_registers[] =3D {
> +     { KM_CAM_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_cam_ctrl_fields },
> +     { KM_CAM_DATA, 3, 216, NTHW_FPGA_REG_TYPE_WO= , 0, 12,
> km_cam_data_fields },
> +     { KM_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_rcp_ctrl_fields },
> +     { KM_RCP_DATA, 1, 781, NTHW_FPGA_REG_TYPE_WO= , 0, 44,
> km_rcp_data_fields },
> +     { KM_STATUS, 10, 1, NTHW_FPGA_REG_TYPE_RO, 0= , 1,
> km_status_fields },
> +     { KM_TCAM_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> km_tcam_ctrl_fields },
> +     { KM_TCAM_DATA, 5, 72, NTHW_FPGA_REG_TYPE_WO= , 0, 1,
> km_tcam_data_fields },
> +     { KM_TCI_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_tci_ctrl_fields },
> +     { KM_TCI_DATA, 7, 36, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_tci_data_fields },
> +     { KM_TCQ_CTRL, 8, 21, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_tcq_ctrl_fields },
> +     { KM_TCQ_DATA, 9, 15, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> km_tcq_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] =3D {
> +     { MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_bip_err_fields[] =3D {
> +     { MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_block_lock_fields[] =3D {
> +     { MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s mac_pcs_block_lock_chg_fields[] =3D { > +     { MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_debounce_ctrl_fields[] =3D { > +     { MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY,= 8, 8, 10 },
> +     { MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, = 1, 16, 0 },
> +     { MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8= , 0, 10 },
> +     { MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17,= 2 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_drp_ctrl_fields[] =3D {
> +     { MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 }, {
> MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 },
> +     { MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 }= , {
> MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 },
> +     { MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 }, { > MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_ctrl_fields[] =3D {
> +     { MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_cw_cnt_fields[] =3D {
> +     { MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_0_fields[] =3D { > +     { MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_1_fields[] =3D { > +     { MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_2_fields[] =3D { > +     { MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_3_fields[] =3D { > +     { MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_0_fields[] =3D { > +     { MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_1_fields[] =3D { > +     { MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_2_fields[] =3D { > +     { MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_3_fields[] =3D { > +     { MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_lane_map_fields[] =3D {
> +     { MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_stat_fields[] =3D {
> +     { MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 },=
> +     { MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 }= ,
> +     { MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 }= ,
> +     { MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 }= ,
> +     { MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 }= ,
> +     { MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 = },
> +     { MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 }, > +     { MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x00= 00 },
> +     { MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 }, > +     { MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x00= 00 },
> +     { MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s mac_pcs_fec_ucw_cnt_fields[] =3D {
> +     { MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_ctl_rx_fields[] =3D {
> +     { MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 },= {
> MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 },
> +     { MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 },= {
> MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 },
> +     { MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 },= {
> MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 },
> +     { MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 },= {
> MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 },
> +     { MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 }, {=
> MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 },
> +     { MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 }, {=
> MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 },
> +     { MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 }, = {
> MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 },
> +     { MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 }, = {
> MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 },
> +     { MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 }, { > MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 },
> +     { MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 }, { > MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_ctl_tx_fields[] =3D {
> +     { MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 }, {=
> MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 },
> +     { MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 }, {=
> MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 },
> +     { MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 }, = {
> MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 },
> +     { MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 }, = {
> MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_diff_ctl_fields[] =3D {
> +     { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, = 24 },
> +     { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, = 24 },
> +     { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10,= 24 },
> +     { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15,= 24 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_loop_fields[] =3D {
> +     { MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 },
> +     { MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 },
> +     { MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 },
> +     { MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_post_cursor_fields[] =3D {<= br> > +     { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, = 0, 20 },
> +     { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, = 5, 20 },
> +     { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, = 10, 20 },
> +     { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, = 15, 20 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_prbs_sel_fields[] =3D {
> +     { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16,= 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20,= 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24,= 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28,= 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, = 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, = 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, = 0 },
> +     { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12,= 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_pre_cursor_fields[] =3D { > +     { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0,= 0 },
> +     { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5,= 0 },
> +     { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10= , 0 },
> +     { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15= , 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_rx_buf_stat_fields[] =3D {<= br> > +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, = 0, 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, = 3, 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, = 6, 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, = 9, 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGE= D_0, 3, 12,
> 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGE= D_1, 3, 15,
> 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGE= D_2, 3, 18,
> 0x0000 },
> +     { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGE= D_3, 3, 21,
> 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_scan_ctl_fields[] =3D {
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7,= 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12= , 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13= , 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14= , 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15= , 0 },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 }= ,
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 }= ,
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 = },
> +     { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_scan_stat_fields[] =3D { > +     { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0= , 0x0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1= , 0x0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2= , 0x0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3= , 0x0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x= 0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x= 0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x= 0000 },
> +     { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_gty_stat_fields[] =3D {
> +     { MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0= 000 },
> +     { MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0= 000 },
> +     { MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0= 000 },
> +     { MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x00= 00 },
> +     { MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_link_summary_fields[] =3D {
> +     { MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 },<= br> > +     { MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 = },
> +     { MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13= , 0 },
> +     { MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 1= 4, 0 },
> +     { MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, = 0 },
> +     { MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1,= 3, 0x0000 },
> +     { MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0= x0000 },
> +     { MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x= 0000 },
> +     { MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1,= 1, 0x0000 },
> +     { MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, = 0x0000 },
> +     { MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 },=
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_mac_pcs_config_fields[] =3D { > +     { MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, = 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 = },
> +     { MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1,= 6, 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, = 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1,= 7, 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, = 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 = },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4= , 1 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, = 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9,= 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10,= 0 },
> +     { MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1,= 11, 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_max_pkt_len_fields[] =3D {
> +     { MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_phymac_misc_fields[] =3D {
> +     { MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 },
> +     { MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x= 0000 },
> +     { MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 }= ,
> +     { MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, = 0 },
> +     { MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 },=
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_phy_stat_fields[] =3D {
> +     { MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 }, > +     { MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 },<= br> > +     { MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_fields[] =3D {
> +     { MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 = },
> +     { MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0= 000 },
> +     { MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0= x0000 },
> +     { MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 }= ,
> +     { MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, = 1, 4, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0= 000 },
> +     { MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x00= 00 },
> +     { MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, = 1, 5, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x= 0000 },
> +     { MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_latch_fields[] =3D = {
> +     { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0= x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, = 2, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1= , 9, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x= 0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_F= AULT, 1, 4,
> 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, = 6, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3= , 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_F= AULT, 1, 5,
> 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1,= 7, 0x0000 },
> +     { MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_stat_pcs_tx_fields[] =3D {
> +     { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0= 000 },
> +     { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1= , 5, 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1= , 4, 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CH= ANGED, 1, 9,
> 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, = 1, 3, 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_C= HANGED, 1, 8,
> 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x000= 0 },
> +     { MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, = 7, 0x0000 },
> +     { MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x000= 0 },
> +     { MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, = 6, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_synced_fields[] =3D {
> +     { MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_synced_err_fields[] =3D {
> +     { MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_test_err_fields[] =3D {
> +     { MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_timestamp_comp_fields[] =3D { > +     { MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451= },
> +     { MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 144= 0 },
> +};
> +
> +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_fields[] =3D {
> +     { MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_chg_fields[] =3D { > +     { MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_register_init_s mac_pcs_registers[] =3D {
> +     { MAC_PCS_BAD_CODE, 26, 16, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> mac_pcs_bad_code_fields },
> +     { MAC_PCS_BIP_ERR, 31, 640, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> mac_pcs_bip_err_fields },
> +     { MAC_PCS_BLOCK_LOCK, 27, 20, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_pcs_block_lock_fields },
> +     {
> +           &nb= sp; MAC_PCS_BLOCK_LOCK_CHG, 28, 20,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_block_lock_chg_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_DEBOUNCE_CTRL, 1, 19,
> NTHW_FPGA_REG_TYPE_RW, 264714, 4,
> +           &nb= sp; mac_pcs_debounce_ctrl_fields
> +     },
> +     { MAC_PCS_DRP_CTRL, 43, 32, NTHW_FPGA_REG_TY= PE_MIXED, 0, 6,
> mac_pcs_drp_ctrl_fields },
> +     { MAC_PCS_FEC_CTRL, 2, 5, NTHW_FPGA_REG_TYPE= _RW, 0, 1,
> mac_pcs_fec_ctrl_fields },
> +     { MAC_PCS_FEC_CW_CNT, 9, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> mac_pcs_fec_cw_cnt_fields },
> +     {
> +           &nb= sp; MAC_PCS_FEC_ERR_CNT_0, 11, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_err_cnt_0_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_ERR_CNT_1, 12, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_err_cnt_1_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_ERR_CNT_2, 13, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_err_cnt_2_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_ERR_CNT_3, 14, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_err_cnt_3_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_LANE_DLY_0, 5, 14,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_lane_dly_0_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_LANE_DLY_1, 6, 14,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_lane_dly_1_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_LANE_DLY_2, 7, 14,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_lane_dly_2_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_FEC_LANE_DLY_3, 8, 14,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_fec_lane_dly_3_fields
> +     },
> +     { MAC_PCS_FEC_LANE_MAP, 4, 8, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_pcs_fec_lane_map_fields },
> +     { MAC_PCS_FEC_STAT, 3, 11, NTHW_FPGA_REG_TYP= E_RO, 0, 11,
> mac_pcs_fec_stat_fields },
> +     { MAC_PCS_FEC_UCW_CNT, 10, 32, NTHW_FPGA_REG= _TYPE_RO, 0,
> 1, mac_pcs_fec_ucw_cnt_fields },
> +     { MAC_PCS_GTY_CTL_RX, 38, 28, NTHW_FPGA_REG_= TYPE_RW, 0, 20,
> mac_pcs_gty_ctl_rx_fields },
> +     { MAC_PCS_GTY_CTL_TX, 39, 8, NTHW_FPGA_REG_T= YPE_RW, 0, 8,
> mac_pcs_gty_ctl_tx_fields },
> +     {
> +           &nb= sp; MAC_PCS_GTY_DIFF_CTL, 35, 20,
> NTHW_FPGA_REG_TYPE_RW, 811800, 4,
> +           &nb= sp; mac_pcs_gty_diff_ctl_fields
> +     },
> +     { MAC_PCS_GTY_LOOP, 20, 12, NTHW_FPGA_REG_TY= PE_RW, 0, 4,
> mac_pcs_gty_loop_fields },
> +     {
> +           &nb= sp; MAC_PCS_GTY_POST_CURSOR, 36, 20,
> NTHW_FPGA_REG_TYPE_RW, 676500, 4,
> +           &nb= sp; mac_pcs_gty_post_cursor_fields
> +     },
> +     { MAC_PCS_GTY_PRBS_SEL, 40, 32, NTHW_FPGA_RE= G_TYPE_RW, 0,
> 8, mac_pcs_gty_prbs_sel_fields },
> +     {
> +           &nb= sp; MAC_PCS_GTY_PRE_CURSOR, 37, 20,
> NTHW_FPGA_REG_TYPE_RW, 0, 4,
> +           &nb= sp; mac_pcs_gty_pre_cursor_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_GTY_RX_BUF_STAT, 34, 24,
> NTHW_FPGA_REG_TYPE_RO, 0, 8,
> +           &nb= sp; mac_pcs_gty_rx_buf_stat_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_GTY_SCAN_CTL, 41, 16,
> NTHW_FPGA_REG_TYPE_RW, 0, 16,
> +           &nb= sp; mac_pcs_gty_scan_ctl_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_GTY_SCAN_STAT, 42, 8,
> NTHW_FPGA_REG_TYPE_RO, 0, 8,
> +           &nb= sp; mac_pcs_gty_scan_stat_fields
> +     },
> +     { MAC_PCS_GTY_STAT, 33, 16, NTHW_FPGA_REG_TY= PE_RO, 0, 12,
> mac_pcs_gty_stat_fields },
> +     { MAC_PCS_LINK_SUMMARY, 0, 19, NTHW_FPGA_REG= _TYPE_RO, 0,
> 11, mac_pcs_link_summary_fields },
> +     {
> +           &nb= sp; MAC_PCS_MAC_PCS_CONFIG, 19, 12,
> NTHW_FPGA_REG_TYPE_RW, 272, 12,
> +           &nb= sp; mac_pcs_mac_pcs_config_fields
> +     },
> +     {
> +           &nb= sp; MAC_PCS_MAX_PKT_LEN, 17, 14,
> NTHW_FPGA_REG_TYPE_RW, 10000, 1,
> +           &nb= sp; mac_pcs_max_pkt_len_fields
> +     },
> +     { MAC_PCS_PHYMAC_MISC, 16, 8, NTHW_FPGA_REG_= TYPE_MIXED,
> 9, 5, mac_pcs_phymac_misc_fields },
> +     { MAC_PCS_PHY_STAT, 15, 3, NTHW_FPGA_REG_TYP= E_RO, 0, 3,
> mac_pcs_phy_stat_fields },
> +     { MAC_PCS_STAT_PCS_RX, 21, 10, NTHW_FPGA_REG= _TYPE_RO, 0, 10,
> mac_pcs_stat_pcs_rx_fields },
> +     {
> +           &nb= sp; MAC_PCS_STAT_PCS_RX_LATCH, 22, 10,
> NTHW_FPGA_REG_TYPE_RO, 0, 10,
> +           &nb= sp; mac_pcs_stat_pcs_rx_latch_fields
> +     },
> +     { MAC_PCS_STAT_PCS_TX, 23, 10, NTHW_FPGA_REG= _TYPE_RO, 0, 10,
> mac_pcs_stat_pcs_tx_fields },
> +     { MAC_PCS_SYNCED, 24, 20, NTHW_FPGA_REG_TYPE= _RO, 0, 1,
> mac_pcs_synced_fields },
> +     { MAC_PCS_SYNCED_ERR, 25, 20, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_pcs_synced_err_fields },
> +     { MAC_PCS_TEST_ERR, 32, 16, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> mac_pcs_test_err_fields },
> +     {
> +           &nb= sp; MAC_PCS_TIMESTAMP_COMP, 18, 32,
> NTHW_FPGA_REG_TYPE_RW, 94373291, 2,
> +           &nb= sp; mac_pcs_timestamp_comp_fields
> +     },
> +     { MAC_PCS_VL_DEMUXED, 29, 20, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_pcs_vl_demuxed_fields },
> +     {
> +           &nb= sp; MAC_PCS_VL_DEMUXED_CHG, 30, 20,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_pcs_vl_demuxed_chg_fields
> +     },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_bad_fcs_fields[] =3D {
> +     { MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_fragment_fields[] =3D {
> +     { MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s mac_rx_packet_bad_fcs_fields[] =3D { > +     { MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_packet_small_fields[] =3D {
> +     { MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_total_bytes_fields[] =3D {
> +     { MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_total_good_bytes_fields[] =3D {<= br> > +     { MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_total_good_packets_fields[] =3D = {
> +     { MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_total_packets_fields[] =3D {
> +     { MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s mac_rx_undersize_fields[] =3D {
> +     { MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_register_init_s mac_rx_registers[] =3D {
> +     { MAC_RX_BAD_FCS, 0, 32, NTHW_FPGA_REG_TYPE_= RO, 0, 1,
> mac_rx_bad_fcs_fields },
> +     { MAC_RX_FRAGMENT, 6, 32, NTHW_FPGA_REG_TYPE= _RO, 0, 1,
> mac_rx_fragment_fields },
> +     {
> +           &nb= sp; MAC_RX_PACKET_BAD_FCS, 7, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_rx_packet_bad_fcs_fields
> +     },
> +     { MAC_RX_PACKET_SMALL, 3, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_rx_packet_small_fields },
> +     { MAC_RX_TOTAL_BYTES, 4, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> mac_rx_total_bytes_fields },
> +     {
> +           &nb= sp; MAC_RX_TOTAL_GOOD_BYTES, 5, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_rx_total_good_bytes_fields
> +     },
> +     {
> +           &nb= sp; MAC_RX_TOTAL_GOOD_PACKETS, 2, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_rx_total_good_packets_fields
> +     },
> +     { MAC_RX_TOTAL_PACKETS, 1, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> mac_rx_total_packets_fields },
> +     { MAC_RX_UNDERSIZE, 8, 32, NTHW_FPGA_REG_TYP= E_RO, 0, 1,
> mac_rx_undersize_fields },
> +};
> +
> +static nthw_fpga_field_init_s mac_tx_packet_small_fields[] =3D {
> +     { MAC_TX_PACKET_SMALL_COUNT, 32, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s mac_tx_total_bytes_fields[] =3D {
> +     { MAC_TX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s mac_tx_total_good_bytes_fields[] =3D {<= br> > +     { MAC_TX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s mac_tx_total_good_packets_fields[] =3D = {
> +     { MAC_TX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x= 0000 },
> +};
> +
> +static nthw_fpga_field_init_s mac_tx_total_packets_fields[] =3D {
> +     { MAC_TX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_register_init_s mac_tx_registers[] =3D {
> +     { MAC_TX_PACKET_SMALL, 2, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> mac_tx_packet_small_fields },
> +     { MAC_TX_TOTAL_BYTES, 3, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> mac_tx_total_bytes_fields },
> +     {
> +           &nb= sp; MAC_TX_TOTAL_GOOD_BYTES, 4, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_tx_total_good_bytes_fields
> +     },
> +     {
> +           &nb= sp; MAC_TX_TOTAL_GOOD_PACKETS, 1, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; mac_tx_total_good_packets_fields
> +     },
> +     { MAC_TX_TOTAL_PACKETS, 0, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> mac_tx_total_packets_fields },
> +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] =3D {
> +     { PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_rdaddr_fields[] =3D {
> +     { PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata0_fields[] =3D {
> +     { PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0,= 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata1_fields[] =3D {
> +     { PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0= , 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata2_fields[] =3D {
> +     { PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 },<= br> > +     { PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 },=
> +     { PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 },
> +     { PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_rd_tg_tg_rd_run_fields[] =3D {
> +     { PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0= },
> +};
> +
> +static nthw_fpga_register_init_s pci_rd_tg_registers[] =3D {
> +     { PCI_RD_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYP= E_RO, 0, 1,
> pci_rd_tg_tg_ctrl_fields },
> +     { PCI_RD_TG_TG_RDADDR, 3, 9, NTHW_FPGA_REG_T= YPE_WO, 0, 1,
> pci_rd_tg_tg_rdaddr_fields },
> +     { PCI_RD_TG_TG_RDDATA0, 0, 32, NTHW_FPGA_REG= _TYPE_WO, 0, 1,
> pci_rd_tg_tg_rddata0_fields },
> +     { PCI_RD_TG_TG_RDDATA1, 1, 32, NTHW_FPGA_REG= _TYPE_WO, 0, 1,
> pci_rd_tg_tg_rddata1_fields },
> +     { PCI_RD_TG_TG_RDDATA2, 2, 32, NTHW_FPGA_REG= _TYPE_WO, 0, 4,
> pci_rd_tg_tg_rddata2_fields },
> +     { PCI_RD_TG_TG_RD_RUN, 4, 16, NTHW_FPGA_REG_= TYPE_WO, 0, 1,
> pci_rd_tg_tg_rd_run_fields },
> +};
> +
> +static nthw_fpga_field_init_s pci_ta_control_fields[] =3D {
> +     { PCI_TA_CONTROL_ENABLE, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_ta_length_error_fields[] =3D {
> +     { PCI_TA_LENGTH_ERROR_AMOUNT, 32, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s pci_ta_packet_bad_fields[] =3D {
> +     { PCI_TA_PACKET_BAD_AMOUNT, 32, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s pci_ta_packet_good_fields[] =3D {
> +     { PCI_TA_PACKET_GOOD_AMOUNT, 32, 0, 0x0000 }= ,
> +};
> +
> +static nthw_fpga_field_init_s pci_ta_payload_error_fields[] =3D {
> +     { PCI_TA_PAYLOAD_ERROR_AMOUNT, 32, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_register_init_s pci_ta_registers[] =3D {
> +     { PCI_TA_CONTROL, 0, 1, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> pci_ta_control_fields },
> +     { PCI_TA_LENGTH_ERROR, 3, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> pci_ta_length_error_fields },
> +     { PCI_TA_PACKET_BAD, 2, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> pci_ta_packet_bad_fields },
> +     { PCI_TA_PACKET_GOOD, 1, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> pci_ta_packet_good_fields },
> +     { PCI_TA_PAYLOAD_ERROR, 4, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> pci_ta_payload_error_fields },
> +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_ctrl_fields[] =3D {
> +     { PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_seq_fields[] =3D {
> +     { PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_wraddr_fields[] =3D {
> +     { PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata0_fields[] =3D {
> +     { PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0,= 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata1_fields[] =3D {
> +     { PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0= , 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata2_fields[] =3D {
> +     { PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 },= {
> PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 },
> +     { PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 },= {
> PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 },
> +     { PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pci_wr_tg_tg_wr_run_fields[] =3D {
> +     { PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0= },
> +};
> +
> +static nthw_fpga_register_init_s pci_wr_tg_registers[] =3D {
> +     { PCI_WR_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYP= E_RO, 0, 1,
> pci_wr_tg_tg_ctrl_fields },
> +     { PCI_WR_TG_TG_SEQ, 6, 16, NTHW_FPGA_REG_TYP= E_RW, 0, 1,
> pci_wr_tg_tg_seq_fields },
> +     { PCI_WR_TG_TG_WRADDR, 3, 9, NTHW_FPGA_REG_T= YPE_WO, 0, 1,
> pci_wr_tg_tg_wraddr_fields },
> +     { PCI_WR_TG_TG_WRDATA0, 0, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, pci_wr_tg_tg_wrdata0_fields },
> +     { PCI_WR_TG_TG_WRDATA1, 1, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, pci_wr_tg_tg_wrdata1_fields },
> +     { PCI_WR_TG_TG_WRDATA2, 2, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 5, pci_wr_tg_tg_wrdata2_fields },
> +     { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_= TYPE_WO, 0, 1,
> pci_wr_tg_tg_wr_run_fields },
> +};
> +
> +static nthw_fpga_field_init_s pdb_config_fields[] =3D {
> +     { PDB_CONFIG_PORT_OFS, 6, 3, 0 },
> +     { PDB_CONFIG_TS_FORMAT, 3, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pdb_rcp_ctrl_fields[] =3D {
> +     { PDB_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { PDB_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s pdb_rcp_data_fields[] =3D {
> +     { PDB_RCP_DATA_ALIGN, 1, 17, 0x0000 },
> +     { PDB_RCP_DATA_CRC_OVERWRITE, 1, 16, 0x0000 = },
> +     { PDB_RCP_DATA_DESCRIPTOR, 4, 0, 0x0000 }, > +     { PDB_RCP_DATA_DESC_LEN, 5, 4, 0 },
> +     { PDB_RCP_DATA_DUPLICATE_BIT, 5, 61, 0x0000 = },
> +     { PDB_RCP_DATA_DUPLICATE_EN, 1, 60, 0x0000 }= ,
> +     { PDB_RCP_DATA_IP_PROT_TNL, 1, 57, 0x0000 },=
> +     { PDB_RCP_DATA_OFS0_DYN, 5, 18, 0x0000 }, > +     { PDB_RCP_DATA_OFS0_REL, 8, 23, 0x0000 }, > +     { PDB_RCP_DATA_OFS1_DYN, 5, 31, 0x0000 }, > +     { PDB_RCP_DATA_OFS1_REL, 8, 36, 0x0000 }, > +     { PDB_RCP_DATA_OFS2_DYN, 5, 44, 0x0000 }, > +     { PDB_RCP_DATA_OFS2_REL, 8, 49, 0x0000 }, > +     { PDB_RCP_DATA_PCAP_KEEP_FCS, 1, 66, 0x0000 = },
> +     { PDB_RCP_DATA_PPC_HSH, 2, 58, 0x0000 },
> +     { PDB_RCP_DATA_TX_IGNORE, 1, 14, 0x0000 }, > +     { PDB_RCP_DATA_TX_NOW, 1, 15, 0x0000 },
> +     { PDB_RCP_DATA_TX_PORT, 5, 9, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s pdb_registers[] =3D {
> +     { PDB_CONFIG, 2, 10, NTHW_FPGA_REG_TYPE_WO, = 0, 2,
> pdb_config_fields },
> +     { PDB_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> pdb_rcp_ctrl_fields },
> +     { PDB_RCP_DATA, 1, 67, NTHW_FPGA_REG_TYPE_WO= , 0, 18,
> pdb_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s pdi_cr_fields[] =3D {
> +     { PDI_CR_EN, 1, 0, 0 }, { PDI_CR_PARITY, 1, = 4, 0 }, { PDI_CR_RST, 1, 1, 0
> },
> +     { PDI_CR_RXRST, 1, 2, 0 }, { PDI_CR_STOP, 1,= 5, 0 }, { PDI_CR_TXRST, 1,
> 3, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pdi_drr_fields[] =3D {
> +     { PDI_DRR_DRR, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pdi_dtr_fields[] =3D {
> +     { PDI_DTR_DTR, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pdi_pre_fields[] =3D {
> +     { PDI_PRE_PRE, 7, 0, 3 },
> +};
> +
> +static nthw_fpga_field_init_s pdi_sr_fields[] =3D {
> +     { PDI_SR_DISABLE_BUSY, 1, 2, 0 }, { PDI_SR_D= ONE, 1, 0, 0 },
> +     { PDI_SR_ENABLE_BUSY, 1, 1, 0 }, { PDI_SR_FR= AME_ERR, 1, 5, 0 },
> +     { PDI_SR_OVERRUN_ERR, 1, 7, 0 }, { PDI_SR_PA= RITY_ERR, 1, 6, 0 },
> +     { PDI_SR_RXLVL, 7, 8, 0 }, { PDI_SR_RX_BUSY,= 1, 4, 0 },
> +     { PDI_SR_TXLVL, 7, 15, 0 }, { PDI_SR_TX_BUSY= , 1, 3, 0 },
> +};
> +
> +static nthw_fpga_field_init_s pdi_srr_fields[] =3D {
> +     { PDI_SRR_RST, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s pdi_registers[] =3D {
> +     { PDI_CR, 1, 6, NTHW_FPGA_REG_TYPE_WO, 0, 6,= pdi_cr_fields },
> +     { PDI_DRR, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1= , pdi_drr_fields },
> +     { PDI_DTR, 3, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1= , pdi_dtr_fields },
> +     { PDI_PRE, 5, 7, NTHW_FPGA_REG_TYPE_WO, 3, 1= , pdi_pre_fields },
> +     { PDI_SR, 2, 22, NTHW_FPGA_REG_TYPE_RO, 0, 1= 0, pdi_sr_fields },
> +     { PDI_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1= , pdi_srr_fields },
> +};
> +
> +static nthw_fpga_field_init_s qsl_qen_ctrl_fields[] =3D {
> +     { QSL_QEN_CTRL_ADR, 5, 0, 0x0000 },
> +     { QSL_QEN_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_qen_data_fields[] =3D {
> +     { QSL_QEN_DATA_EN, 4, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_qst_ctrl_fields[] =3D {
> +     { QSL_QST_CTRL_ADR, 12, 0, 0x0000 },
> +     { QSL_QST_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_qst_data_fields[] =3D {
> +     { QSL_QST_DATA_LRE, 1, 9, 0x0000 }, { QSL_QS= T_DATA_QEN, 1, 7,
> 0x0000 },
> +     { QSL_QST_DATA_QUEUE, 7, 0, 0x0000 }, { QSL_= QST_DATA_TCI, 16,
> 10, 0x0000 },
> +     { QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 }, { QS= L_QST_DATA_VEN, 1,
> 26, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_rcp_ctrl_fields[] =3D {
> +     { QSL_RCP_CTRL_ADR, 5, 0, 0x0000 },
> +     { QSL_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_rcp_data_fields[] =3D {
> +     { QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 }, { QS= L_RCP_DATA_DROP, 2,
> 1, 0x0000 },
> +     { QSL_RCP_DATA_LR, 2, 51, 0x0000 }, { QSL_RC= P_DATA_TBL_HI, 12,
> 15, 0x0000 },
> +     { QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 }, {<= br> > QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 },
> +     { QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 }, { = QSL_RCP_DATA_TSA,
> 1, 53, 0x0000 },
> +     { QSL_RCP_DATA_VLI, 2, 54, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_unmq_ctrl_fields[] =3D {
> +     { QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 },
> +     { QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qsl_unmq_data_fields[] =3D {
> +     { QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 },<= br> > +     { QSL_UNMQ_DATA_EN, 1, 7, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s qsl_registers[] =3D {
> +     { QSL_QEN_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> qsl_qen_ctrl_fields },
> +     { QSL_QEN_DATA, 5, 4, NTHW_FPGA_REG_TYPE_WO,= 0, 1,
> qsl_qen_data_fields },
> +     { QSL_QST_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> qsl_qst_ctrl_fields },
> +     { QSL_QST_DATA, 3, 27, NTHW_FPGA_REG_TYPE_WO= , 0, 6,
> qsl_qst_data_fields },
> +     { QSL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> qsl_rcp_ctrl_fields },
> +     { QSL_RCP_DATA, 1, 56, NTHW_FPGA_REG_TYPE_WO= , 0, 9,
> qsl_rcp_data_fields },
> +     { QSL_UNMQ_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_W= O, 0, 2,
> qsl_unmq_ctrl_fields },
> +     { QSL_UNMQ_DATA, 7, 8, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> qsl_unmq_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s qspi_cr_fields[] =3D {
> +     { QSPI_CR_CPHA, 1, 4, 0 }, { QSPI_CR_CPOL, 1= , 3, 0 },
> +     { QSPI_CR_LOOP, 1, 0, 0 }, { QSPI_CR_LSBF, 1= , 9, 0 },
> +     { QSPI_CR_MSSAE, 1, 7, 1 }, { QSPI_CR_MST, 1= , 2, 0 },
> +     { QSPI_CR_MTI, 1, 8, 1 }, { QSPI_CR_RXFIFO_R= ST, 1, 6, 0 },
> +     { QSPI_CR_SPE, 1, 1, 0 }, { QSPI_CR_TXFIFO_R= ST, 1, 5, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_dgie_fields[] =3D {
> +     { QSPI_DGIE_GIE, 1, 31, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_drr_fields[] =3D {
> +     { QSPI_DRR_DATA_VAL, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_dtr_fields[] =3D {
> +     { QSPI_DTR_DATA_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_ier_fields[] =3D {
> +     { QSPI_IER_CMD_ERR, 1, 13, 0 }, { QSPI_IER_C= POL_CPHA_ERR, 1, 9, 0
> },
> +     { QSPI_IER_DRR_FULL, 1, 4, 0 }, { QSPI_IER_D= RR_NEMPTY, 1, 8, 0 },
> +     { QSPI_IER_DRR_OR, 1, 5, 0 }, { QSPI_IER_DTR= _EMPTY, 1, 2, 0 },
> +     { QSPI_IER_DTR_UR, 1, 3, 0 }, { QSPI_IER_LOO= P_ERR, 1, 12, 0 },
> +     { QSPI_IER_MODF, 1, 0, 0 }, { QSPI_IER_MSB_E= RR, 1, 11, 0 },
> +     { QSPI_IER_SLV_ERR, 1, 10, 0 }, { QSPI_IER_S= LV_MODF, 1, 1, 0 },
> +     { QSPI_IER_SLV_MS, 1, 7, 0 }, { QSPI_IER_TXF= IFO_HEMPTY, 1, 6, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_isr_fields[] =3D {
> +     { QSPI_ISR_CMD_ERR, 1, 13, 0 }, { QSPI_ISR_C= POL_CPHA_ERR, 1, 9, 0
> },
> +     { QSPI_ISR_DRR_FULL, 1, 4, 0 }, { QSPI_ISR_D= RR_NEMPTY, 1, 8, 0 },
> +     { QSPI_ISR_DRR_OR, 1, 5, 0 }, { QSPI_ISR_DTR= _EMPTY, 1, 2, 0 },
> +     { QSPI_ISR_DTR_UR, 1, 3, 0 }, { QSPI_ISR_LOO= P_ERR, 1, 12, 0 },
> +     { QSPI_ISR_MODF, 1, 0, 0 }, { QSPI_ISR_MSB_E= RR, 1, 11, 0 },
> +     { QSPI_ISR_SLV_ERR, 1, 10, 0 }, { QSPI_ISR_S= LV_MODF, 1, 1, 0 },
> +     { QSPI_ISR_SLV_MS, 1, 7, 0 }, { QSPI_ISR_TXF= IFO_HEMPTY, 1, 6, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_rx_fifo_ocy_fields[] =3D {
> +     { QSPI_RX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_sr_fields[] =3D {
> +     { QSPI_SR_CMD_ERR, 1, 10, 0 }, { QSPI_SR_CPO= L_CPHA_ERR, 1, 6, 0 },
> +     { QSPI_SR_LOOP_ERR, 1, 9, 0 }, { QSPI_SR_MOD= F, 1, 4, 0 },
> +     { QSPI_SR_MSB_ERR, 1, 8, 0 }, { QSPI_SR_RXEM= PTY, 1, 0, 1 },
> +     { QSPI_SR_RXFULL, 1, 1, 0 }, { QSPI_SR_SLVMS= , 1, 5, 1 },
> +     { QSPI_SR_SLV_ERR, 1, 7, 0 }, { QSPI_SR_TXEM= PTY, 1, 2, 1 },
> +     { QSPI_SR_TXFULL, 1, 3, 0 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_srr_fields[] =3D {
> +     { QSPI_SRR_RST, 4, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_ssr_fields[] =3D {
> +     { QSPI_SSR_SEL_SLV, 32, 0, 4294967295 },
> +};
> +
> +static nthw_fpga_field_init_s qspi_tx_fifo_ocy_fields[] =3D {
> +     { QSPI_TX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s qspi_registers[] =3D {
> +     { QSPI_CR, 24, 10, NTHW_FPGA_REG_TYPE_RW, 38= 4, 10,
> qspi_cr_fields },
> +     { QSPI_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0= , 1,
> qspi_dgie_fields },
> +     { QSPI_DRR, 27, 32, NTHW_FPGA_REG_TYPE_RO, 0= , 1, qspi_drr_fields
> },
> +     { QSPI_DTR, 26, 32, NTHW_FPGA_REG_TYPE_WO, 0= , 1,
> qspi_dtr_fields },
> +     { QSPI_IER, 10, 14, NTHW_FPGA_REG_TYPE_RW, 0= , 14, qspi_ier_fields
> },
> +     { QSPI_ISR, 8, 14, NTHW_FPGA_REG_TYPE_RW, 0,= 14, qspi_isr_fields
> },
> +     { QSPI_RX_FIFO_OCY, 30, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> qspi_rx_fifo_ocy_fields },
> +     { QSPI_SR, 25, 11, NTHW_FPGA_REG_TYPE_RO, 37= , 11, qspi_sr_fields
> },
> +     { QSPI_SRR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0,= 1, qspi_srr_fields
> },
> +     { QSPI_SSR, 28, 32, NTHW_FPGA_REG_TYPE_RW, 4= 294967295, 1,
> qspi_ssr_fields },
> +     { QSPI_TX_FIFO_OCY, 29, 32, NTHW_FPGA_REG_TY= PE_RO, 0, 1,
> qspi_tx_fifo_ocy_fields },
> +};
> +
> +static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] =3D {
> +     { RAC_DBG_CTRL_C, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rac_dbg_data_fields[] =3D {
> +     { RAC_DBG_DATA_D, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_buf_free_fields[] =3D {
> +     { RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 }, { > RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 },
> +     { RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 }, {<= br> > RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 },
> +     { RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_buf_used_fields[] =3D {
> +     { RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 },
> +     { RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 },
> +     { RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ib_hi_fields[] =3D {
> +     { RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ib_lo_fields[] =3D {
> +     { RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ib_rd_fields[] =3D {
> +     { RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ib_wr_fields[] =3D {
> +     { RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ob_hi_fields[] =3D {
> +     { RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ob_lo_fields[] =3D {
> +     { RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_dma_ob_wr_fields[] =3D {
> +     { RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_ib_data_fields[] =3D {
> +     { RAC_RAB_IB_DATA_D, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_init_fields[] =3D {
> +     { RAC_RAB_INIT_RAB, 3, 0, 7 },
> +};
> +
> +static nthw_fpga_field_init_s rac_rab_ob_data_fields[] =3D {
> +     { RAC_RAB_OB_DATA_D, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s rac_registers[] =3D {
> +     { RAC_DBG_CTRL, 4200, 32, NTHW_FPGA_REG_TYPE= _RW, 0, 1,
> rac_dbg_ctrl_fields },
> +     { RAC_DBG_DATA, 4208, 32, NTHW_FPGA_REG_TYPE= _RW, 0, 1,
> rac_dbg_data_fields },
> +     {
> +           &nb= sp; RAC_RAB_BUF_FREE, 4176, 32,
> NTHW_FPGA_REG_TYPE_MIXED, 33489407, 5,
> +           &nb= sp; rac_rab_buf_free_fields
> +     },
> +     { RAC_RAB_BUF_USED, 4184, 32, NTHW_FPGA_REG_= TYPE_MIXED, 0,
> 3, rac_rab_buf_used_fields },
> +     { RAC_RAB_DMA_IB_HI, 4360, 32, NTHW_FPGA_REG= _TYPE_WO, 0, 1,
> rac_rab_dma_ib_hi_fields },
> +     { RAC_RAB_DMA_IB_LO, 4352, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, rac_rab_dma_ib_lo_fields },
> +     { RAC_RAB_DMA_IB_RD, 4424, 16, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> rac_rab_dma_ib_rd_fields },
> +     { RAC_RAB_DMA_IB_WR, 4416, 16, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, rac_rab_dma_ib_wr_fields },
> +     { RAC_RAB_DMA_OB_HI, 4376, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, rac_rab_dma_ob_hi_fields },
> +     { RAC_RAB_DMA_OB_LO, 4368, 32, NTHW_FPGA_REG= _TYPE_WO, 0,
> 1, rac_rab_dma_ob_lo_fields },
> +     { RAC_RAB_DMA_OB_WR, 4480, 16, NTHW_FPGA_REG= _TYPE_RO, 0,
> 1, rac_rab_dma_ob_wr_fields },
> +     { RAC_RAB_IB_DATA, 4160, 32, NTHW_FPGA_REG_T= YPE_WO, 0, 1,
> rac_rab_ib_data_fields },
> +     { RAC_RAB_INIT, 4192, 3, NTHW_FPGA_REG_TYPE_= RW, 7, 1,
> rac_rab_init_fields },
> +     { RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_T= YPE_RC1, 0, 1,
> rac_rab_ob_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s rfd_ctrl_fields[] =3D {
> +     { RFD_CTRL_CFP, 1, 2, 1 },
> +     { RFD_CTRL_ISL, 1, 0, 1 },
> +     { RFD_CTRL_PWMCW, 1, 1, 1 },
> +};
> +
> +static nthw_fpga_field_init_s rfd_max_frame_size_fields[] =3D {
> +     { RFD_MAX_FRAME_SIZE_MAX, 14, 0, 9018 },
> +};
> +
> +static nthw_fpga_field_init_s rfd_tnl_vlan_fields[] =3D {
> +     { RFD_TNL_VLAN_TPID0, 16, 0, 33024 },
> +     { RFD_TNL_VLAN_TPID1, 16, 16, 33024 },
> +};
> +
> +static nthw_fpga_field_init_s rfd_vlan_fields[] =3D {
> +     { RFD_VLAN_TPID0, 16, 0, 33024 },
> +     { RFD_VLAN_TPID1, 16, 16, 33024 },
> +};
> +
> +static nthw_fpga_field_init_s rfd_vxlan_fields[] =3D {
> +     { RFD_VXLAN_DP0, 16, 0, 4789 },
> +     { RFD_VXLAN_DP1, 16, 16, 4789 },
> +};
> +
> +static nthw_fpga_register_init_s rfd_registers[] =3D {
> +     { RFD_CTRL, 0, 3, NTHW_FPGA_REG_TYPE_WO, 7, = 3, rfd_ctrl_fields },
> +     { RFD_MAX_FRAME_SIZE, 1, 14, NTHW_FPGA_REG_T= YPE_WO, 9018,
> 1, rfd_max_frame_size_fields },
> +     { RFD_TNL_VLAN, 3, 32, NTHW_FPGA_REG_TYPE_WO= , 2164293888,
> 2, rfd_tnl_vlan_fields },
> +     { RFD_VLAN, 2, 32, NTHW_FPGA_REG_TYPE_WO, 21= 64293888, 2,
> rfd_vlan_fields },
> +     { RFD_VXLAN, 4, 32, NTHW_FPGA_REG_TYPE_WO, 3= 13856693, 2,
> rfd_vxlan_fields },
> +};
> +
> +static nthw_fpga_field_init_s rmc_ctrl_fields[] =3D {
> +     { RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 }, {
> RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 },
> +     { RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 }, { > RMC_CTRL_BLOCK_STATT, 1, 0, 1 },
> +     { RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rmc_dbg_fields[] =3D {
> +     { RMC_DBG_MERGE, 31, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rmc_mac_if_fields[] =3D {
> +     { RMC_MAC_IF_ERR, 31, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rmc_status_fields[] =3D {
> +     { RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 },
> +     { RMC_STATUS_SF_RAM_OF, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s rmc_registers[] =3D {
> +     { RMC_CTRL, 0, 25, NTHW_FPGA_REG_TYPE_RW, 77= 1, 5,
> rmc_ctrl_fields },
> +     { RMC_DBG, 2, 31, NTHW_FPGA_REG_TYPE_RO, 0, = 1, rmc_dbg_fields
> },
> +     { RMC_MAC_IF, 3, 31, NTHW_FPGA_REG_TYPE_RO, = 0, 1,
> rmc_mac_if_fields },
> +     { RMC_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_RO, = 0, 2,
> rmc_status_fields },
> +};
> +
> +static nthw_fpga_field_init_s rpl_ext_ctrl_fields[] =3D {
> +     { RPL_EXT_CTRL_ADR, 10, 0, 0x0000 },
> +     { RPL_EXT_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpl_ext_data_fields[] =3D {
> +     { RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpl_rcp_ctrl_fields[] =3D {
> +     { RPL_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { RPL_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpl_rcp_data_fields[] =3D {
> +     { RPL_RCP_DATA_DYN, 5, 0, 0x0000 }, {
> RPL_RCP_DATA_ETH_TYPE_WR, 1, 36, 0x0000 },
> +     { RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 }, { = RPL_RCP_DATA_LEN, 8,
> 15, 0x0000 },
> +     { RPL_RCP_DATA_OFS, 10, 5, 0x0000 }, { RPL_R= CP_DATA_RPL_PTR,
> 12, 23, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpl_rpl_ctrl_fields[] =3D {
> +     { RPL_RPL_CTRL_ADR, 12, 0, 0x0000 },
> +     { RPL_RPL_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpl_rpl_data_fields[] =3D {
> +     { RPL_RPL_DATA_VALUE, 128, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s rpl_registers[] =3D {
> +     { RPL_EXT_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> rpl_ext_ctrl_fields },
> +     { RPL_EXT_DATA, 3, 12, NTHW_FPGA_REG_TYPE_WO= , 0, 1,
> rpl_ext_data_fields },
> +     { RPL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> rpl_rcp_ctrl_fields },
> +     { RPL_RCP_DATA, 1, 37, NTHW_FPGA_REG_TYPE_WO= , 0, 6,
> rpl_rcp_data_fields },
> +     { RPL_RPL_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> rpl_rpl_ctrl_fields },
> +     { RPL_RPL_DATA, 5, 128, NTHW_FPGA_REG_TYPE_W= O, 0, 1,
> rpl_rpl_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s rpp_lr_ifr_rcp_ctrl_fields[] =3D {
> +     { RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 }, > +     { RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s rpp_lr_ifr_rcp_data_fields[] =3D {
> +     { RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0= x0000 },
> +     { RPP_LR_IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 = },
> +     { RPP_LR_IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x00= 00 },
> +     { RPP_LR_IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 = },
> +     { RPP_LR_IFR_RCP_DATA_MTU, 14, 2, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s rpp_lr_rcp_ctrl_fields[] =3D {
> +     { RPP_LR_RCP_CTRL_ADR, 4, 0, 0x0000 },
> +     { RPP_LR_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s rpp_lr_rcp_data_fields[] =3D {
> +     { RPP_LR_RCP_DATA_EXP, 14, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s rpp_lr_registers[] =3D {
> +     { RPP_LR_IFR_RCP_CTRL, 2, 32, NTHW_FPGA_REG_= TYPE_WO, 0, 2,
> rpp_lr_ifr_rcp_ctrl_fields },
> +     { RPP_LR_IFR_RCP_DATA, 3, 18, NTHW_FPGA_REG_= TYPE_WO, 0, 5,
> rpp_lr_ifr_rcp_data_fields },
> +     { RPP_LR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> rpp_lr_rcp_ctrl_fields },
> +     { RPP_LR_RCP_DATA, 1, 14, NTHW_FPGA_REG_TYPE= _WO, 0, 1,
> rpp_lr_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s rst9563_ctrl_fields[] =3D {
> +     { RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 }, > +     { RST9563_CTRL_TS_CLKSEL, 1, 1, 1 },
> +     { RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 }= ,
> +};
> +
> +static nthw_fpga_field_init_s rst9563_power_fields[] =3D {
> +     { RST9563_POWER_PU_NSEB, 1, 1, 0 },
> +     { RST9563_POWER_PU_PHY, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rst9563_rst_fields[] =3D {
> +     { RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST95= 63_RST_DDR4, 3, 3,
> 7 },
> +     { RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_R= ST_PERIPH, 1, 13, 0 },
> +     { RST9563_RST_PHY, 2, 7, 3 }, { RST9563_RST_= PTP, 1, 11, 1 },
> +     { RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST956= 3_RST_RPP, 1, 2, 1 },
> +     { RST9563_RST_SDC, 1, 6, 1 }, { RST9563_RST_= SYS, 1, 0, 1 },
> +     { RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST956= 3_RST_TMC, 1, 1, 1
> },
> +     { RST9563_RST_TS, 1, 12, 1 }, { RST9563_RST_= TS_MMCM, 1, 17, 0 },
> +};
> +
> +static nthw_fpga_field_init_s rst9563_stat_fields[] =3D {
> +     { RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x000= 0 },
> +     { RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x000= 0 },
> +     { RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000= },
> +     { RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000= },
> +     { RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000= },
> +     { RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s rst9563_sticky_fields[] =3D {
> +     { RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0= x0000 },
> +     { RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0= x0000 },
> +     { RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x= 0000 },
> +     { RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x= 0000 },
> +     { RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x= 0000 },
> +     { RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0= 000 },
> +};
> +
> +static nthw_fpga_register_init_s rst9563_registers[] =3D {
> +     { RST9563_CTRL, 1, 3, NTHW_FPGA_REG_TYPE_RW,= 7, 3,
> rst9563_ctrl_fields },
> +     { RST9563_POWER, 4, 2, NTHW_FPGA_REG_TYPE_RW= , 0, 2,
> rst9563_power_fields },
> +     { RST9563_RST, 0, 18, NTHW_FPGA_REG_TYPE_RW,= 8191, 14,
> rst9563_rst_fields },
> +     { RST9563_STAT, 2, 6, NTHW_FPGA_REG_TYPE_RO,= 0, 6,
> rst9563_stat_fields },
> +     { RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_R= C1, 0, 6,
> rst9563_sticky_fields },
> +};
> +
> +static nthw_fpga_field_init_s slc_rcp_ctrl_fields[] =3D {
> +     { SLC_RCP_CTRL_ADR, 6, 0, 0x0000 },
> +     { SLC_RCP_CTRL_CNT, 16, 16, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s slc_rcp_data_fields[] =3D {
> +     { SLC_RCP_DATA_HEAD_DYN, 5, 1, 0x0000 }, { > SLC_RCP_DATA_HEAD_OFS, 8, 6, 0x0000 },
> +     { SLC_RCP_DATA_HEAD_SLC_EN, 1, 0, 0x0000 }, = {
> SLC_RCP_DATA_PCAP, 1, 35, 0x0000 },
> +     { SLC_RCP_DATA_TAIL_DYN, 5, 15, 0x0000 }, {<= br> > SLC_RCP_DATA_TAIL_OFS, 15, 20, 0x0000 },
> +     { SLC_RCP_DATA_TAIL_SLC_EN, 1, 14, 0x0000 },=
> +};
> +
> +static nthw_fpga_register_init_s slc_registers[] =3D {
> +     { SLC_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO= , 0, 2,
> slc_rcp_ctrl_fields },
> +     { SLC_RCP_DATA, 1, 36, NTHW_FPGA_REG_TYPE_WO= , 0, 7,
> slc_rcp_data_fields },
> +};
> +
> +static nthw_fpga_field_init_s spim_cfg_fields[] =3D {
> +     { SPIM_CFG_PRE, 3, 0, 5 },
> +};
> +
> +static nthw_fpga_field_init_s spim_cfg_clk_fields[] =3D {
> +     { SPIM_CFG_CLK_MODE, 2, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spim_cr_fields[] =3D {
> +     { SPIM_CR_EN, 1, 1, 0 },
> +     { SPIM_CR_LOOP, 1, 0, 0 },
> +     { SPIM_CR_RXRST, 1, 3, 0 },
> +     { SPIM_CR_TXRST, 1, 2, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spim_drr_fields[] =3D {
> +     { SPIM_DRR_DRR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spim_dtr_fields[] =3D {
> +     { SPIM_DTR_DTR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spim_sr_fields[] =3D {
> +     { SPIM_SR_DONE, 1, 0, 0 }, { SPIM_SR_RXEMPTY= , 1, 2, 1 }, {
> SPIM_SR_RXFULL, 1, 4, 0 },
> +     { SPIM_SR_RXLVL, 8, 16, 0 }, { SPIM_SR_TXEMP= TY, 1, 1, 1 }, {
> SPIM_SR_TXFULL, 1, 3, 0 },
> +     { SPIM_SR_TXLVL, 8, 8, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spim_srr_fields[] =3D {
> +     { SPIM_SRR_RST, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s spim_registers[] =3D {
> +     { SPIM_CFG, 5, 3, NTHW_FPGA_REG_TYPE_WO, 5, = 1, spim_cfg_fields
> },
> +     { SPIM_CFG_CLK, 6, 2, NTHW_FPGA_REG_TYPE_WO,= 0, 1,
> spim_cfg_clk_fields },
> +     { SPIM_CR, 1, 4, NTHW_FPGA_REG_TYPE_WO, 0, 4= , spim_cr_fields },
> +     { SPIM_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0,= 1, spim_drr_fields
> },
> +     { SPIM_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0,= 1, spim_dtr_fields
> },
> +     { SPIM_SR, 2, 24, NTHW_FPGA_REG_TYPE_RO, 6, = 7, spim_sr_fields },
> +     { SPIM_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, = 1, spim_srr_fields
> },
> +};
> +
> +static nthw_fpga_field_init_s spis_cr_fields[] =3D {
> +     { SPIS_CR_DEBUG, 1, 4, 0 }, { SPIS_CR_EN, 1,= 1, 0 }, { SPIS_CR_LOOP,
> 1, 0, 0 },
> +     { SPIS_CR_RXRST, 1, 3, 0 }, { SPIS_CR_TXRST,= 1, 2, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_drr_fields[] =3D {
> +     { SPIS_DRR_DRR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_dtr_fields[] =3D {
> +     { SPIS_DTR_DTR, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_ram_ctrl_fields[] =3D {
> +     { SPIS_RAM_CTRL_ADR, 6, 0, 0 },
> +     { SPIS_RAM_CTRL_CNT, 6, 6, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_ram_data_fields[] =3D {
> +     { SPIS_RAM_DATA_DATA, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_sr_fields[] =3D {
> +     { SPIS_SR_DONE, 1, 0, 0 }, { SPIS_SR_FRAME_E= RR, 1, 24, 0 },
> +     { SPIS_SR_READ_ERR, 1, 25, 0 }, { SPIS_SR_RX= EMPTY, 1, 2, 1 },
> +     { SPIS_SR_RXFULL, 1, 4, 0 }, { SPIS_SR_RXLVL= , 8, 16, 0 },
> +     { SPIS_SR_TXEMPTY, 1, 1, 1 }, { SPIS_SR_TXFU= LL, 1, 3, 0 },
> +     { SPIS_SR_TXLVL, 8, 8, 0 }, { SPIS_SR_WRITE_= ERR, 1, 26, 0 },
> +};
> +
> +static nthw_fpga_field_init_s spis_srr_fields[] =3D {
> +     { SPIS_SRR_RST, 4, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s spis_registers[] =3D {
> +     { SPIS_CR, 1, 5, NTHW_FPGA_REG_TYPE_WO, 0, 5= , spis_cr_fields },
> +     { SPIS_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0,= 1, spis_drr_fields },
> +     { SPIS_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0,= 1, spis_dtr_fields },
> +     { SPIS_RAM_CTRL, 5, 12, NTHW_FPGA_REG_TYPE_R= W, 0, 2,
> spis_ram_ctrl_fields },
> +     { SPIS_RAM_DATA, 6, 32, NTHW_FPGA_REG_TYPE_R= W, 0, 1,
> spis_ram_data_fields },
> +     { SPIS_SR, 2, 27, NTHW_FPGA_REG_TYPE_RO, 6, = 10, spis_sr_fields },
> +     { SPIS_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, = 1, spis_srr_fields },
> +};
> +
> +static nthw_fpga_field_init_s sta_byte_fields[] =3D {
> +     { STA_BYTE_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s sta_cfg_fields[] =3D {
> +     { STA_CFG_CNT_CLEAR, 1, 1, 0 },
> +     { STA_CFG_DMA_ENA, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s sta_cv_err_fields[] =3D {
> +     { STA_CV_ERR_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s sta_fcs_err_fields[] =3D {
> +     { STA_FCS_ERR_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s sta_host_adr_lsb_fields[] =3D {
> +     { STA_HOST_ADR_LSB_LSB, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s sta_host_adr_msb_fields[] =3D {
> +     { STA_HOST_ADR_MSB_MSB, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s sta_load_bin_fields[] =3D {
> +     { STA_LOAD_BIN_BIN, 32, 0, 8388607 },
> +};
> +
> +static nthw_fpga_field_init_s sta_load_bps_rx_0_fields[] =3D {
> +     { STA_LOAD_BPS_RX_0_BPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_bps_rx_1_fields[] =3D {
> +     { STA_LOAD_BPS_RX_1_BPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_bps_tx_0_fields[] =3D {
> +     { STA_LOAD_BPS_TX_0_BPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_bps_tx_1_fields[] =3D {
> +     { STA_LOAD_BPS_TX_1_BPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_pps_rx_0_fields[] =3D {
> +     { STA_LOAD_PPS_RX_0_PPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_pps_rx_1_fields[] =3D {
> +     { STA_LOAD_PPS_RX_1_PPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_pps_tx_0_fields[] =3D {
> +     { STA_LOAD_PPS_TX_0_PPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_load_pps_tx_1_fields[] =3D {
> +     { STA_LOAD_PPS_TX_1_PPS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s sta_pckt_fields[] =3D {
> +     { STA_PCKT_CNT, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s sta_status_fields[] =3D {
> +     { STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x000= 0 },
> +};
> +
> +static nthw_fpga_register_init_s sta_registers[] =3D {
> +     { STA_BYTE, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0,= 1, sta_byte_fields },
> +     { STA_CFG, 0, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2= , sta_cfg_fields },
> +     { STA_CV_ERR, 5, 32, NTHW_FPGA_REG_TYPE_RO, = 0, 1,
> sta_cv_err_fields },
> +     { STA_FCS_ERR, 6, 32, NTHW_FPGA_REG_TYPE_RO,= 0, 1,
> sta_fcs_err_fields },
> +     { STA_HOST_ADR_LSB, 1, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 1,
> sta_host_adr_lsb_fields },
> +     { STA_HOST_ADR_MSB, 2, 32, NTHW_FPGA_REG_TYP= E_WO, 0, 1,
> sta_host_adr_msb_fields },
> +     { STA_LOAD_BIN, 8, 32, NTHW_FPGA_REG_TYPE_WO= , 8388607, 1,
> sta_load_bin_fields },
> +     { STA_LOAD_BPS_RX_0, 11, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_bps_rx_0_fields },
> +     { STA_LOAD_BPS_RX_1, 13, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_bps_rx_1_fields },
> +     { STA_LOAD_BPS_TX_0, 15, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_bps_tx_0_fields },
> +     { STA_LOAD_BPS_TX_1, 17, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_bps_tx_1_fields },
> +     { STA_LOAD_PPS_RX_0, 10, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_pps_rx_0_fields },
> +     { STA_LOAD_PPS_RX_1, 12, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_pps_rx_1_fields },
> +     { STA_LOAD_PPS_TX_0, 14, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_pps_tx_0_fields },
> +     { STA_LOAD_PPS_TX_1, 16, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> sta_load_pps_tx_1_fields },
> +     { STA_PCKT, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0,= 1, sta_pckt_fields },
> +     { STA_STATUS, 7, 1, NTHW_FPGA_REG_TYPE_RC1, = 0, 1,
> sta_status_fields },
> +};
> +
> +static nthw_fpga_field_init_s tempmon_alarms_fields[] =3D {
> +     { TEMPMON_ALARMS_OT, 1, 1, 0x0000 },
> +     { TEMPMON_ALARMS_OT_OVERWR, 1, 2, 0 },
> +     { TEMPMON_ALARMS_OT_OVERWRVAL, 1, 3, 0 }, > +     { TEMPMON_ALARMS_TEMP, 1, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tempmon_stat_fields[] =3D {
> +     { TEMPMON_STAT_TEMP, 12, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_register_init_s tempmon_registers[] =3D {
> +     { TEMPMON_ALARMS, 1, 4, NTHW_FPGA_REG_TYPE_M= IXED, 0, 4,
> tempmon_alarms_fields },
> +     { TEMPMON_STAT, 0, 12, NTHW_FPGA_REG_TYPE_RO= , 0, 1,
> tempmon_stat_fields },
> +};
> +
> +static nthw_fpga_field_init_s tint_ctrl_fields[] =3D {
> +     { TINT_CTRL_INTERVAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tint_status_fields[] =3D {
> +     { TINT_STATUS_DELAYED, 8, 8, 0 },
> +     { TINT_STATUS_SKIPPED, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s tint_registers[] =3D {
> +     { TINT_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0= , 1, tint_ctrl_fields
> },
> +     { TINT_STATUS, 1, 16, NTHW_FPGA_REG_TYPE_RC1= , 0, 2,
> tint_status_fields },
> +};
> +
> +static nthw_fpga_field_init_s tsm_con0_config_fields[] =3D {
> +     { TSM_CON0_CONFIG_BLIND, 5, 8, 9 }, {
> TSM_CON0_CONFIG_DC_SRC, 3, 5, 0 },
> +     { TSM_CON0_CONFIG_PORT, 3, 0, 0 }, {
> TSM_CON0_CONFIG_PPSIN_2_5V, 1, 13, 0 },
> +     { TSM_CON0_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con0_interface_fields[] =3D {
> +     { TSM_CON0_INTERFACE_EX_TERM, 2, 0, 3 }, { > TSM_CON0_INTERFACE_IN_REF_PWM, 8, 12, 128 },
> +     { TSM_CON0_INTERFACE_PWM_ENA, 1, 2, 0 }, { > TSM_CON0_INTERFACE_RESERVED, 1, 3, 0 },
> +     { TSM_CON0_INTERFACE_VTERM_PWM, 8, 4, 0 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con0_sample_hi_fields[] =3D {
> +     { TSM_CON0_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con0_sample_lo_fields[] =3D {
> +     { TSM_CON0_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con1_config_fields[] =3D {
> +     { TSM_CON1_CONFIG_BLIND, 5, 8, 9 }, {
> TSM_CON1_CONFIG_DC_SRC, 3, 5, 0 },
> +     { TSM_CON1_CONFIG_PORT, 3, 0, 0 }, {
> TSM_CON1_CONFIG_PPSIN_2_5V, 1, 13, 0 },
> +     { TSM_CON1_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con1_sample_hi_fields[] =3D {
> +     { TSM_CON1_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con1_sample_lo_fields[] =3D {
> +     { TSM_CON1_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con2_config_fields[] =3D {
> +     { TSM_CON2_CONFIG_BLIND, 5, 8, 9 }, {
> TSM_CON2_CONFIG_DC_SRC, 3, 5, 0 },
> +     { TSM_CON2_CONFIG_PORT, 3, 0, 0 }, {
> TSM_CON2_CONFIG_PPSIN_2_5V, 1, 13, 0 },
> +     { TSM_CON2_CONFIG_SAMPLE_EDGE, 2, 3, 2 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con2_sample_hi_fields[] =3D {
> +     { TSM_CON2_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con2_sample_lo_fields[] =3D {
> +     { TSM_CON2_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con3_config_fields[] =3D {
> +     { TSM_CON3_CONFIG_BLIND, 5, 5, 26 },
> +     { TSM_CON3_CONFIG_PORT, 3, 0, 1 },
> +     { TSM_CON3_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con3_sample_hi_fields[] =3D {
> +     { TSM_CON3_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con3_sample_lo_fields[] =3D {
> +     { TSM_CON3_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con4_config_fields[] =3D {
> +     { TSM_CON4_CONFIG_BLIND, 5, 5, 26 },
> +     { TSM_CON4_CONFIG_PORT, 3, 0, 1 },
> +     { TSM_CON4_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con4_sample_hi_fields[] =3D {
> +     { TSM_CON4_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con4_sample_lo_fields[] =3D {
> +     { TSM_CON4_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con5_config_fields[] =3D {
> +     { TSM_CON5_CONFIG_BLIND, 5, 5, 26 },
> +     { TSM_CON5_CONFIG_PORT, 3, 0, 1 },
> +     { TSM_CON5_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con5_sample_hi_fields[] =3D {
> +     { TSM_CON5_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con5_sample_lo_fields[] =3D {
> +     { TSM_CON5_SAMPLE_LO_TIME, 32, 0, 0x0000 },<= br> > +};
> +
> +static nthw_fpga_field_init_s tsm_con6_config_fields[] =3D {
> +     { TSM_CON6_CONFIG_BLIND, 5, 5, 26 },
> +     { TSM_CON6_CONFIG_PORT, 3, 0, 1 },
> +     { TSM_CON6_CONFIG_SAMPLE_EDGE, 2, 3, 1 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con6_sample_hi_fields[] =3D {
> +     { TSM_CON6_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con6_sample_lo_fields[] =3D {
> +     { TSM_CON6_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_con7_host_sample_hi_fields[] =3D {<= br> > +     { TSM_CON7_HOST_SAMPLE_HI_SEC, 32, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s tsm_con7_host_sample_lo_fields[] =3D {<= br> > +     { TSM_CON7_HOST_SAMPLE_LO_NS, 32, 0, 0x0000 = },
> +};
> +
> +static nthw_fpga_field_init_s tsm_config_fields[] =3D {
> +     { TSM_CONFIG_NTTS_SRC, 2, 5, 0 }, { TSM_CONF= IG_NTTS_SYNC, 1, 4,
> 0 },
> +     { TSM_CONFIG_TIMESET_EDGE, 2, 8, 1 }, {
> TSM_CONFIG_TIMESET_SRC, 3, 10, 0 },
> +     { TSM_CONFIG_TIMESET_UP, 1, 7, 0 }, { TSM_CO= NFIG_TS_FORMAT, 4,
> 0, 1 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_int_config_fields[] =3D {
> +     { TSM_INT_CONFIG_AUTO_DISABLE, 1, 0, 0 }, > +     { TSM_INT_CONFIG_MASK, 19, 1, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_int_stat_fields[] =3D {
> +     { TSM_INT_STAT_CAUSE, 19, 1, 0 },
> +     { TSM_INT_STAT_ENABLE, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_led_fields[] =3D {
> +     { TSM_LED_LED0_BG_COLOR, 2, 3, 0 }, { TSM_LE= D_LED0_COLOR, 2, 1,
> 0 },
> +     { TSM_LED_LED0_MODE, 1, 0, 0 }, { TSM_LED_LE= D0_SRC, 4, 5, 0 },
> +     { TSM_LED_LED1_BG_COLOR, 2, 12, 0 }, { TSM_L= ED_LED1_COLOR, 2,
> 10, 0 },
> +     { TSM_LED_LED1_MODE, 1, 9, 0 }, { TSM_LED_LE= D1_SRC, 4, 14, 1 },
> +     { TSM_LED_LED2_BG_COLOR, 2, 21, 0 }, { TSM_L= ED_LED2_COLOR, 2,
> 19, 0 },
> +     { TSM_LED_LED2_MODE, 1, 18, 0 }, { TSM_LED_L= ED2_SRC, 4, 23, 2 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_config_fields[] =3D {
> +     { TSM_NTTS_CONFIG_AUTO_HARDSET, 1, 5, 1 }, > +     { TSM_NTTS_CONFIG_EXT_CLK_ADJ, 1, 6, 0 }, > +     { TSM_NTTS_CONFIG_HIGH_SAMPLE, 1, 4, 0 }, > +     { TSM_NTTS_CONFIG_TS_SRC_FORMAT, 4, 0, 0 },<= br> > +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_ext_stat_fields[] =3D {
> +     { TSM_NTTS_EXT_STAT_MASTER_ID, 8, 16, 0x0000= },
> +     { TSM_NTTS_EXT_STAT_MASTER_REV, 8, 24, 0x000= 0 },
> +     { TSM_NTTS_EXT_STAT_MASTER_STAT, 16, 0, 0x00= 00 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_limit_hi_fields[] =3D {
> +     { TSM_NTTS_LIMIT_HI_SEC, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_limit_lo_fields[] =3D {
> +     { TSM_NTTS_LIMIT_LO_NS, 32, 0, 100000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_offset_fields[] =3D {
> +     { TSM_NTTS_OFFSET_NS, 30, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_sample_hi_fields[] =3D {
> +     { TSM_NTTS_SAMPLE_HI_SEC, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_sample_lo_fields[] =3D {
> +     { TSM_NTTS_SAMPLE_LO_NS, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_stat_fields[] =3D {
> +     { TSM_NTTS_STAT_NTTS_VALID, 1, 0, 0 },
> +     { TSM_NTTS_STAT_SIGNAL_LOST, 8, 1, 0 },
> +     { TSM_NTTS_STAT_SYNC_LOST, 8, 9, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_ts_t0_hi_fields[] =3D {
> +     { TSM_NTTS_TS_T0_HI_TIME, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_ts_t0_lo_fields[] =3D {
> +     { TSM_NTTS_TS_T0_LO_TIME, 32, 0, 0x0000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_ntts_ts_t0_offset_fields[] =3D { > +     { TSM_NTTS_TS_T0_OFFSET_COUNT, 32, 0, 0x0000= },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pb_ctrl_fields[] =3D {
> +     { TSM_PB_CTRL_INSTMEM_WR, 1, 1, 0 },
> +     { TSM_PB_CTRL_RST, 1, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pb_instmem_fields[] =3D {
> +     { TSM_PB_INSTMEM_MEM_ADDR, 14, 0, 0 },
> +     { TSM_PB_INSTMEM_MEM_DATA, 18, 14, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pi_ctrl_i_fields[] =3D {
> +     { TSM_PI_CTRL_I_VAL, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pi_ctrl_ki_fields[] =3D {
> +     { TSM_PI_CTRL_KI_GAIN, 24, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pi_ctrl_kp_fields[] =3D {
> +     { TSM_PI_CTRL_KP_GAIN, 24, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_pi_ctrl_shl_fields[] =3D {
> +     { TSM_PI_CTRL_SHL_VAL, 4, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_stat_fields[] =3D {
> +     { TSM_STAT_HARD_SYNC, 8, 8, 0 }, { TSM_STAT_= LINK_CON0, 1, 0, 0 },
> +     { TSM_STAT_LINK_CON1, 1, 1, 0 }, { TSM_STAT_= LINK_CON2, 1, 2, 0 },
> +     { TSM_STAT_LINK_CON3, 1, 3, 0 }, { TSM_STAT_= LINK_CON4, 1, 4, 0 },
> +     { TSM_STAT_LINK_CON5, 1, 5, 0 }, { TSM_STAT_= NTTS_INSYNC, 1, 6, 0
> },
> +     { TSM_STAT_PTP_MI_PRESENT, 1, 7, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_timer_ctrl_fields[] =3D {
> +     { TSM_TIMER_CTRL_TIMER_EN_T0, 1, 0, 0 },
> +     { TSM_TIMER_CTRL_TIMER_EN_T1, 1, 1, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_timer_t0_fields[] =3D {
> +     { TSM_TIMER_T0_MAX_COUNT, 30, 0, 50000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_timer_t1_fields[] =3D {
> +     { TSM_TIMER_T1_MAX_COUNT, 30, 0, 50000 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_time_hardset_hi_fields[] =3D {
> +     { TSM_TIME_HARDSET_HI_TIME, 32, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s tsm_time_hardset_lo_fields[] =3D {
> +     { TSM_TIME_HARDSET_LO_TIME, 32, 0, 0x0000 },=
> +};
> +
> +static nthw_fpga_field_init_s tsm_time_hi_fields[] =3D {
> +     { TSM_TIME_HI_SEC, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_time_lo_fields[] =3D {
> +     { TSM_TIME_LO_NS, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_time_rate_adj_fields[] =3D {
> +     { TSM_TIME_RATE_ADJ_FRACTION, 29, 0, 0 }, > +};
> +
> +static nthw_fpga_field_init_s tsm_ts_hi_fields[] =3D {
> +     { TSM_TS_HI_TIME, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_lo_fields[] =3D {
> +     { TSM_TS_LO_TIME, 32, 0, 0x0000 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_offset_fields[] =3D {
> +     { TSM_TS_OFFSET_NS, 30, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_fields[] =3D {
> +     { TSM_TS_STAT_OVERRUN, 1, 16, 0 },
> +     { TSM_TS_STAT_SAMPLES, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_hi_offset_fields[] =3D { > +     { TSM_TS_STAT_HI_OFFSET_NS, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_lo_offset_fields[] =3D { > +     { TSM_TS_STAT_LO_OFFSET_NS, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_tar_hi_fields[] =3D {
> +     { TSM_TS_STAT_TAR_HI_SEC, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_tar_lo_fields[] =3D {
> +     { TSM_TS_STAT_TAR_LO_NS, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_x_fields[] =3D {
> +     { TSM_TS_STAT_X_NS, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_x2_hi_fields[] =3D {
> +     { TSM_TS_STAT_X2_HI_NS, 16, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_ts_stat_x2_lo_fields[] =3D {
> +     { TSM_TS_STAT_X2_LO_NS, 32, 0, 0 },
> +};
> +
> +static nthw_fpga_field_init_s tsm_utc_offset_fields[] =3D {
> +     { TSM_UTC_OFFSET_SEC, 8, 0, 0 },
> +};
> +
> +static nthw_fpga_register_init_s tsm_registers[] =3D {
> +     { TSM_CON0_CONFIG, 24, 14, NTHW_FPGA_REG_TYP= E_RW, 2320, 5,
> tsm_con0_config_fields },
> +     {
> +           &nb= sp; TSM_CON0_INTERFACE, 25, 20, NTHW_FPGA_REG_TYPE_RW,
> 524291, 5,
> +           &nb= sp; tsm_con0_interface_fields
> +     },
> +     { TSM_CON0_SAMPLE_HI, 27, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con0_sample_hi_fields },
> +     { TSM_CON0_SAMPLE_LO, 26, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con0_sample_lo_fields },
> +     { TSM_CON1_CONFIG, 28, 14, NTHW_FPGA_REG_TYP= E_RW, 2320, 5,
> tsm_con1_config_fields },
> +     { TSM_CON1_SAMPLE_HI, 30, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con1_sample_hi_fields },
> +     { TSM_CON1_SAMPLE_LO, 29, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con1_sample_lo_fields },
> +     { TSM_CON2_CONFIG, 31, 14, NTHW_FPGA_REG_TYP= E_RW, 2320, 5,
> tsm_con2_config_fields },
> +     { TSM_CON2_SAMPLE_HI, 33, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con2_sample_hi_fields },
> +     { TSM_CON2_SAMPLE_LO, 32, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con2_sample_lo_fields },
> +     { TSM_CON3_CONFIG, 34, 10, NTHW_FPGA_REG_TYP= E_RW, 841, 3,
> tsm_con3_config_fields },
> +     { TSM_CON3_SAMPLE_HI, 36, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con3_sample_hi_fields },
> +     { TSM_CON3_SAMPLE_LO, 35, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con3_sample_lo_fields },
> +     { TSM_CON4_CONFIG, 37, 10, NTHW_FPGA_REG_TYP= E_RW, 841, 3,
> tsm_con4_config_fields },
> +     { TSM_CON4_SAMPLE_HI, 39, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con4_sample_hi_fields },
> +     { TSM_CON4_SAMPLE_LO, 38, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con4_sample_lo_fields },
> +     { TSM_CON5_CONFIG, 40, 10, NTHW_FPGA_REG_TYP= E_RW, 841, 3,
> tsm_con5_config_fields },
> +     { TSM_CON5_SAMPLE_HI, 42, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con5_sample_hi_fields },
> +     { TSM_CON5_SAMPLE_LO, 41, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con5_sample_lo_fields },
> +     { TSM_CON6_CONFIG, 43, 10, NTHW_FPGA_REG_TYP= E_RW, 841, 3,
> tsm_con6_config_fields },
> +     { TSM_CON6_SAMPLE_HI, 45, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con6_sample_hi_fields },
> +     { TSM_CON6_SAMPLE_LO, 44, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_con6_sample_lo_fields },
> +     {
> +           &nb= sp; TSM_CON7_HOST_SAMPLE_HI, 47, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; tsm_con7_host_sample_hi_fields
> +     },
> +     {
> +           &nb= sp; TSM_CON7_HOST_SAMPLE_LO, 46, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; tsm_con7_host_sample_lo_fields
> +     },
> +     { TSM_CONFIG, 0, 13, NTHW_FPGA_REG_TYPE_RW, = 257, 6,
> tsm_config_fields },
> +     { TSM_INT_CONFIG, 2, 20, NTHW_FPGA_REG_TYPE_= RW, 0, 2,
> tsm_int_config_fields },
> +     { TSM_INT_STAT, 3, 20, NTHW_FPGA_REG_TYPE_MI= XED, 0, 2,
> tsm_int_stat_fields },
> +     { TSM_LED, 4, 27, NTHW_FPGA_REG_TYPE_RW, 167= 93600, 12,
> tsm_led_fields },
> +     { TSM_NTTS_CONFIG, 13, 7, NTHW_FPGA_REG_TYPE= _RW, 32, 4,
> tsm_ntts_config_fields },
> +     { TSM_NTTS_EXT_STAT, 15, 32, NTHW_FPGA_REG_T= YPE_MIXED, 0, 3,
> tsm_ntts_ext_stat_fields },
> +     { TSM_NTTS_LIMIT_HI, 23, 16, NTHW_FPGA_REG_T= YPE_RW, 0, 1,
> tsm_ntts_limit_hi_fields },
> +     { TSM_NTTS_LIMIT_LO, 22, 32, NTHW_FPGA_REG_T= YPE_RW,
> 100000, 1, tsm_ntts_limit_lo_fields },
> +     { TSM_NTTS_OFFSET, 21, 30, NTHW_FPGA_REG_TYP= E_RW, 0, 1,
> tsm_ntts_offset_fields },
> +     { TSM_NTTS_SAMPLE_HI, 19, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_ntts_sample_hi_fields },
> +     { TSM_NTTS_SAMPLE_LO, 18, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_ntts_sample_lo_fields },
> +     { TSM_NTTS_STAT, 14, 17, NTHW_FPGA_REG_TYPE_= RO, 0, 3,
> tsm_ntts_stat_fields },
> +     { TSM_NTTS_TS_T0_HI, 17, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> tsm_ntts_ts_t0_hi_fields },
> +     { TSM_NTTS_TS_T0_LO, 16, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> tsm_ntts_ts_t0_lo_fields },
> +     {
> +           &nb= sp; TSM_NTTS_TS_T0_OFFSET, 20, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; tsm_ntts_ts_t0_offset_fields
> +     },
> +     { TSM_PB_CTRL, 63, 2, NTHW_FPGA_REG_TYPE_WO,= 0, 2,
> tsm_pb_ctrl_fields },
> +     { TSM_PB_INSTMEM, 64, 32, NTHW_FPGA_REG_TYPE= _WO, 0, 2,
> tsm_pb_instmem_fields },
> +     { TSM_PI_CTRL_I, 54, 32, NTHW_FPGA_REG_TYPE_= WO, 0, 1,
> tsm_pi_ctrl_i_fields },
> +     { TSM_PI_CTRL_KI, 52, 24, NTHW_FPGA_REG_TYPE= _RW, 0, 1,
> tsm_pi_ctrl_ki_fields },
> +     { TSM_PI_CTRL_KP, 51, 24, NTHW_FPGA_REG_TYPE= _RW, 0, 1,
> tsm_pi_ctrl_kp_fields },
> +     { TSM_PI_CTRL_SHL, 53, 4, NTHW_FPGA_REG_TYPE= _WO, 0, 1,
> tsm_pi_ctrl_shl_fields },
> +     { TSM_STAT, 1, 16, NTHW_FPGA_REG_TYPE_RO, 0,= 9, tsm_stat_fields
> },
> +     { TSM_TIMER_CTRL, 48, 2, NTHW_FPGA_REG_TYPE_= RW, 0, 2,
> tsm_timer_ctrl_fields },
> +     { TSM_TIMER_T0, 49, 30, NTHW_FPGA_REG_TYPE_R= W, 50000, 1,
> tsm_timer_t0_fields },
> +     { TSM_TIMER_T1, 50, 30, NTHW_FPGA_REG_TYPE_R= W, 50000, 1,
> tsm_timer_t1_fields },
> +     { TSM_TIME_HARDSET_HI, 12, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> tsm_time_hardset_hi_fields },
> +     { TSM_TIME_HARDSET_LO, 11, 32, NTHW_FPGA_REG= _TYPE_RO, 0, 1,
> tsm_time_hardset_lo_fields },
> +     { TSM_TIME_HI, 9, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> tsm_time_hi_fields },
> +     { TSM_TIME_LO, 8, 32, NTHW_FPGA_REG_TYPE_RW,= 0, 1,
> tsm_time_lo_fields },
> +     { TSM_TIME_RATE_ADJ, 10, 29, NTHW_FPGA_REG_T= YPE_RW, 0, 1,
> tsm_time_rate_adj_fields },
> +     { TSM_TS_HI, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0= , 1,
> tsm_ts_hi_fields },
> +     { TSM_TS_LO, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0= , 1,
> tsm_ts_lo_fields },
> +     { TSM_TS_OFFSET, 7, 30, NTHW_FPGA_REG_TYPE_R= W, 0, 1,
> tsm_ts_offset_fields },
> +     { TSM_TS_STAT, 55, 17, NTHW_FPGA_REG_TYPE_RO= , 0, 2,
> tsm_ts_stat_fields },
> +     {
> +           &nb= sp; TSM_TS_STAT_HI_OFFSET, 62, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; tsm_ts_stat_hi_offset_fields
> +     },
> +     {
> +           &nb= sp; TSM_TS_STAT_LO_OFFSET, 61, 32,
> NTHW_FPGA_REG_TYPE_RO, 0, 1,
> +           &nb= sp; tsm_ts_stat_lo_offset_fields
> +     },
> +     { TSM_TS_STAT_TAR_HI, 57, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_ts_stat_tar_hi_fields },
> +     { TSM_TS_STAT_TAR_LO, 56, 32, NTHW_FPGA_REG_= TYPE_RO, 0, 1,
> tsm_ts_stat_tar_lo_fields },
> +     { TSM_TS_STAT_X, 58, 32, NTHW_FPGA_REG_TYPE_= RO, 0, 1,
> tsm_ts_stat_x_fields },
> +     { TSM_TS_STAT_X2_HI, 60, 16, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> tsm_ts_stat_x2_hi_fields },
> +     { TSM_TS_STAT_X2_LO, 59, 32, NTHW_FPGA_REG_T= YPE_RO, 0, 1,
> tsm_ts_stat_x2_lo_fields },
> +     { TSM_UTC_OFFSET, 65, 8, NTHW_FPGA_REG_TYPE_= RW, 0, 1,
> tsm_utc_offset_fields },
> +};
> +
> +static nthw_fpga_module_init_s fpga_modules[] =3D {
> +     { MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_= TYPE_RAB1, 768,
> 34, cat_registers },
> +     { MOD_CSU, 0, MOD_CSU, 0, 0, NTHW_FPGA_BUS_T= YPE_RAB1,
> 9728, 2, csu_registers },
> +     { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_= TYPE_RAB2,
> 12832, 27, dbs_registers },
> +     { MOD_FLM, 0, MOD_FLM, 0, 23, NTHW_FPGA_BUS_= TYPE_RAB1,
> 1280, 43, flm_registers },
> +     { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_T= YPE_RAB2,
> 8704, 10, gfg_registers },
> +     { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_T= YPE_RAB2,
> 9216, 12, gmf_registers },
> +     { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_T= YPE_RAB2,
> 9728, 12, gmf_registers },
> +     {
> +           &nb= sp; MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0,
> NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2,
> +           &nb= sp; gpio_phy_registers
> +     },
> +     { MOD_HFU, 0, MOD_HFU, 0, 2, NTHW_FPGA_BUS_T= YPE_RAB1,
> 9472, 2, hfu_registers },
> +     { MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_T= YPE_PCI, 0, 18,
> hif_registers },
> +     { MOD_HSH, 0, MOD_HSH, 0, 5, NTHW_FPGA_BUS_T= YPE_RAB1,
> 1536, 2, hsh_registers },
> +     { MOD_IFR, 0, MOD_IFR, 0, 7, NTHW_FPGA_BUS_T= YPE_RAB1, 9984,
> 6, ifr_registers },
> +     { MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_T= YPE_RAB0, 768, 22,
> iic_registers },
> +     { MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_T= YPE_RAB0, 896, 22,
> iic_registers },
> +     { MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_T= YPE_RAB0, 24832,
> 22, iic_registers },
> +     { MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_T= YPE_RAB0, 24960,
> 22, iic_registers },
> +     { MOD_KM, 0, MOD_KM, 0, 7, NTHW_FPGA_BUS_TYP= E_RAB1, 1024,
> 11, km_registers },
> +     {
> +           &nb= sp; MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2,
> NTHW_FPGA_BUS_TYPE_RAB2, 10240, 44,
> +           &nb= sp; mac_pcs_registers
> +     },
> +     {
> +           &nb= sp; MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2,
> NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44,
> +           &nb= sp; mac_pcs_registers
> +     },
> +     { MOD_MAC_RX, 0, MOD_MAC_RX, 0, 0,
> NTHW_FPGA_BUS_TYPE_RAB2, 10752, 9, mac_rx_registers },
> +     { MOD_MAC_RX, 1, MOD_MAC_RX, 0, 0,
> NTHW_FPGA_BUS_TYPE_RAB2, 12288, 9, mac_rx_registers },
> +     { MOD_MAC_TX, 0, MOD_MAC_TX, 0, 0,
> NTHW_FPGA_BUS_TYPE_RAB2, 11264, 5, mac_tx_registers },
> +     { MOD_MAC_TX, 1, MOD_MAC_TX, 0, 0,
> NTHW_FPGA_BUS_TYPE_RAB2, 12800, 5, mac_tx_registers },
> +     {
> +           &nb= sp; MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1,
> NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6,
> +           &nb= sp; pci_rd_tg_registers
> +     },
> +     { MOD_PCI_TA, 0, MOD_PCI_TA, 0, 0, NTHW_FPGA= _BUS_TYPE_RAB0,
> 2336, 5, pci_ta_registers },
> +     {
> +           &nb= sp; MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1,
> NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7,
> +           &nb= sp; pci_wr_tg_registers
> +     },
> +     { MOD_PDB, 0, MOD_PDB, 0, 9, NTHW_FPGA_BUS_T= YPE_RAB1,
> 2560, 3, pdb_registers },
> +     { MOD_PDI, 0, MOD_PDI, 1, 1, NTHW_FPGA_BUS_T= YPE_RAB0, 64, 6,
> pdi_registers },
> +     { MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_T= YPE_RAB1, 1792,
> 8, qsl_registers },
> +     { MOD_QSPI, 0, MOD_QSPI, 0, 0, NTHW_FPGA_BUS= _TYPE_RAB0,
> 512, 11, qspi_registers },
> +     { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_T= YPE_PCI, 8192,
> 14, rac_registers },
> +     { MOD_RFD, 0, MOD_RFD, 0, 4, NTHW_FPGA_BUS_T= YPE_RAB1, 256,
> 5, rfd_registers },
> +     { MOD_RMC, 0, MOD_RMC, 1, 3, NTHW_FPGA_BUS_T= YPE_RAB0,
> 12288, 4, rmc_registers },
> +     { MOD_RPP_LR, 0, MOD_RPP_LR, 0, 2,
> NTHW_FPGA_BUS_TYPE_RAB1, 2304, 4, rpp_lr_registers },
> +     { MOD_RST9563, 0, MOD_RST9563, 0, 5,
> NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers },
> +     { MOD_SLC_LR, 0, MOD_SLC, 0, 2, NTHW_FPGA_BU= S_TYPE_RAB1,
> 2048, 2, slc_registers },
> +     { MOD_SPIM, 0, MOD_SPIM, 1, 1, NTHW_FPGA_BUS= _TYPE_RAB0,
> 80, 7, spim_registers },
> +     { MOD_SPIS, 0, MOD_SPIS, 1, 0, NTHW_FPGA_BUS= _TYPE_RAB0, 256,
> 7, spis_registers },
> +     { MOD_STA, 0, MOD_STA, 0, 9, NTHW_FPGA_BUS_T= YPE_RAB0, 2048,
> 17, sta_registers },
> +     {
> +           &nb= sp; MOD_TEMPMON, 0, MOD_TEMPMON, 0, 0,
> NTHW_FPGA_BUS_TYPE_RAB0, 16384, 2,
> +           &nb= sp; tempmon_registers
> +     },
> +     { MOD_TINT, 0, MOD_TINT, 0, 0, NTHW_FPGA_BUS= _TYPE_RAB0,
> 1280, 2, tint_registers },
> +     { MOD_TSM, 0, MOD_TSM, 0, 8, NTHW_FPGA_BUS_T= YPE_RAB2,
> 1024, 66, tsm_registers },
> +     { MOD_TX_CPY, 0, MOD_CPY, 0, 4, NTHW_FPGA_BU= S_TYPE_RAB1,
> 9216, 26, cpy_registers },
> +     { MOD_TX_INS, 0, MOD_INS, 0, 2, NTHW_FPGA_BU= S_TYPE_RAB1,
> 8704, 2, ins_registers },
> +     { MOD_TX_RPL, 0, MOD_RPL, 0, 4, NTHW_FPGA_BU= S_TYPE_RAB1,
> 8960, 6, rpl_registers },
> +};
> +
> +static nthw_fpga_prod_param_s product_parameters[] =3D {
> +     { NT_BUILD_NUMBER, 0 },
> +     { NT_BUILD_TIME, 1713859545 },
> +     { NT_CATEGORIES, 64 },
> +     { NT_CAT_DCT_PRESENT, 0 },
> +     { NT_CAT_END_OFS_SUPPORT, 0 },
> +     { NT_CAT_FUNCS, 64 },
> +     { NT_CAT_KCC_BANKS, 3 },
> +     { NT_CAT_KCC_PRESENT, 0 },
> +     { NT_CAT_KCC_SIZE, 1536 },
> +     { NT_CAT_KM_IF_CNT, 2 },
> +     { NT_CAT_KM_IF_M0, 0 },
> +     { NT_CAT_KM_IF_M1, 1 },
> +     { NT_CAT_N_CMP, 8 },
> +     { NT_CAT_N_EXT, 4 },
> +     { NT_CAT_N_LEN, 8 },
> +     { NT_CB_DEBUG, 0 },
> +     { NT_COR_CATEGORIES, 16 },
> +     { NT_COR_PRESENT, 0 },
> +     { NT_CSU_PRESENT, 1 },
> +     { NT_DBS_PRESENT, 1 },
> +     { NT_DBS_RX_QUEUES, 128 },
> +     { NT_DBS_TX_PORTS, 2 },
> +     { NT_DBS_TX_QUEUES, 128 },
> +     { NT_DDP_PRESENT, 0 },
> +     { NT_DDP_TBL_DEPTH, 4096 },
> +     { NT_EMI_SPLIT_STEPS, 16 },
> +     { NT_EOF_TIMESTAMP_ONLY, 1 },
> +     { NT_EPP_CATEGORIES, 32 },
> +     { NT_FLM_CACHE, 1 },
> +     { NT_FLM_CATEGORIES, 32 },
> +     { NT_FLM_ENTRY_SIZE, 64 },
> +     { NT_FLM_LOAD_APS_MAX, 260000000 },
> +     { NT_FLM_LOAD_LPS_MAX, 300000000 },
> +     { NT_FLM_PRESENT, 1 },
> +     { NT_FLM_PRIOS, 4 },
> +     { NT_FLM_PST_PROFILES, 16 },
> +     { NT_FLM_SCRUB_PROFILES, 16 },
> +     { NT_FLM_SIZE_MB, 12288 },
> +     { NT_FLM_STATEFUL, 1 },
> +     { NT_FLM_VARIANT, 2 },
> +     { NT_GFG_PRESENT, 1 },
> +     { NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 },
> +     { NT_GMF_FCS_PRESENT, 0 },
> +     { NT_GMF_IFG_SPEED_DIV, 33 },
> +     { NT_GMF_IFG_SPEED_DIV100G, 33 },
> +     { NT_GMF_IFG_SPEED_MUL, 20 },
> +     { NT_GMF_IFG_SPEED_MUL100G, 20 },
> +     { NT_GROUP_ID, 9563 },
> +     { NT_HFU_PRESENT, 1 },
> +     { NT_HIF_MSIX_BAR, 1 },
> +     { NT_HIF_MSIX_PBA_OFS, 8192 },
> +     { NT_HIF_MSIX_PRESENT, 1 },
> +     { NT_HIF_MSIX_TBL_OFS, 0 },
> +     { NT_HIF_MSIX_TBL_SIZE, 8 },
> +     { NT_HIF_PER_PS, 4000 },
> +     { NT_HIF_SRIOV_PRESENT, 1 },
> +     { NT_HIF_VF_OFFSET, 4 },
> +     { NT_HSH_CATEGORIES, 16 },
> +     { NT_HSH_TOEPLITZ, 1 },
> +     { NT_HST_CATEGORIES, 32 },
> +     { NT_HST_PRESENT, 0 },
> +     { NT_IOA_CATEGORIES, 1024 },
> +     { NT_IOA_PRESENT, 0 },
> +     { NT_IPF_PRESENT, 0 },
> +     { NT_KM_CAM_BANKS, 3 },
> +     { NT_KM_CAM_RECORDS, 2048 },
> +     { NT_KM_CAM_REC_WORDS, 6 },
> +     { NT_KM_CATEGORIES, 32 },
> +     { NT_KM_END_OFS_SUPPORT, 0 },
> +     { NT_KM_EXT_EXTRACTORS, 1 },
> +     { NT_KM_FLOW_TYPES, 16 },
> +     { NT_KM_PRESENT, 1 },
> +     { NT_KM_SWX_PRESENT, 0 },
> +     { NT_KM_SYNERGY_MATCH, 0 },
> +     { NT_KM_TCAM_BANKS, 12 },
> +     { NT_KM_TCAM_BANK_WIDTH, 72 },
> +     { NT_KM_TCAM_HIT_QUAL, 0 },
> +     { NT_KM_TCAM_KEYWAY, 1 },
> +     { NT_KM_WIDE, 1 },
> +     { NT_LR_PRESENT, 1 },
> +     { NT_MCU_PRESENT, 0 },
> +     { NT_MDG_DEBUG_FLOW_CONTROL, 0 },
> +     { NT_MDG_DEBUG_REG_READ_BACK, 0 },
> +     { NT_MSK_CATEGORIES, 32 },
> +     { NT_MSK_PRESENT, 0 },
> +     { NT_NFV_OVS_PRODUCT, 0 },
> +     { NT_NIMS, 2 },
> +     { NT_PCI_DEVICE_ID, 453 },
> +     { NT_PCI_TA_TG_PRESENT, 1 },
> +     { NT_PCI_VENDOR_ID, 6388 },
> +     { NT_PDB_CATEGORIES, 16 },
> +     { NT_PHY_ANEG_PRESENT, 0 },
> +     { NT_PHY_KRFEC_PRESENT, 0 },
> +     { NT_PHY_PORTS, 2 },
> +     { NT_PHY_PORTS_PER_QUAD, 1 },
> +     { NT_PHY_QUADS, 2 },
> +     { NT_PHY_RSFEC_PRESENT, 1 },
> +     { NT_QM_CELLS, 2097152 },
> +     { NT_QM_CELL_SIZE, 6144 },
> +     { NT_QM_PRESENT, 0 },
> +     { NT_QSL_CATEGORIES, 32 },
> +     { NT_QSL_COLOR_SEL_BW, 7 },
> +     { NT_QSL_QST_SIZE, 4096 },
> +     { NT_QUEUES, 128 },
> +     { NT_RAC_RAB_INTERFACES, 3 },
> +     { NT_RAC_RAB_OB_UPDATE, 0 },
> +     { NT_REVISION_ID, 39 },
> +     { NT_RMC_LAG_GROUPS, 1 },
> +     { NT_RMC_PRESENT, 1 },
> +     { NT_ROA_CATEGORIES, 1024 },
> +     { NT_ROA_PRESENT, 0 },
> +     { NT_RPF_MATURING_DEL_DEFAULT, -150 },
> +     { NT_RPF_PRESENT, 0 },
> +     { NT_RPP_PER_PS, 3333 },
> +     { NT_RTX_PRESENT, 0 },
> +     { NT_RX_HOST_BUFFERS, 128 },
> +     { NT_RX_PORTS, 2 },
> +     { NT_RX_PORT_REPLICATE, 0 },
> +     { NT_SLB_PRESENT, 0 },
> +     { NT_SLC_LR_PRESENT, 1 },
> +     { NT_SLC_PRESENT, 0 },
> +     { NT_STA_COLORS, 64 },
> +     { NT_STA_LOAD_AVG_RX, 1 },
> +     { NT_STA_LOAD_AVG_TX, 1 },
> +     { NT_STA_RX_PORTS, 2 },
> +     { NT_TBH_DEBUG_DLN, 1 },
> +     { NT_TBH_PRESENT, 0 },
> +     { NT_TFD_PRESENT, 1 },
> +     { NT_TPE_CATEGORIES, 16 },
> +     { NT_TSM_OST_ONLY, 0 },
> +     { NT_TS_APPEND, 0 },
> +     { NT_TS_INJECT_PRESENT, 0 },
> +     { NT_TX_CPY_PACKET_READERS, 0 },
> +     { NT_TX_CPY_PRESENT, 1 },
> +     { NT_TX_CPY_SIDEBAND_READERS, 7 },
> +     { NT_TX_CPY_VARIANT, 0 },
> +     { NT_TX_CPY_WRITERS, 6 },
> +     { NT_TX_HOST_BUFFERS, 128 },
> +     { NT_TX_INS_OFS_ZERO, 1 },
> +     { NT_TX_INS_PRESENT, 1 },
> +     { NT_TX_MTU_PROFILE_IFR, 16 },
> +     { NT_TX_ON_TIMESTAMP, 1 },
> +     { NT_TX_PORTS, 2 },
> +     { NT_TX_PORT_REPLICATE, 1 },
> +     { NT_TX_RPL_DEPTH, 4096 },
> +     { NT_TX_RPL_EXT_CATEGORIES, 1024 },
> +     { NT_TX_RPL_OFS_ZERO, 1 },
> +     { NT_TX_RPL_PRESENT, 1 },
> +     { NT_TYPE_ID, 200 },
> +     { NT_USE_TRIPLE_SPEED, 0 },
> +     { NT_VERSION_ID, 55 },
> +     { NT_VLI_PRESENT, 0 },
> +     { 0, -1 },      /* = END */
> +};
> +
> +nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 =3D {
> +     200, 9563, 55, 39, 0, 0, 1713859545, 152, pr= oduct_parameters, 45,
> fpga_modules,
> +};
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c > b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
> new file mode 100644
> index 0000000000..ea731ae979
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
> @@ -0,0 +1,6 @@
> +
> +
> +#include "nthw_fpga_instances.h"
> +nthw_fpga_prod_init_s *nthw_fpga_instances[] =3D {
> &nthw_fpga_9563_055_039_0000, NULL };
> +
> +/* EOF */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
> new file mode 100644
> index 0000000000..c19b43c19b
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
> @@ -0,0 +1,7 @@
> +
> +
> +#include "fpga_model.h"
> +extern nthw_fpga_prod_init_s *nthw_fpga_instances[];
> +extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000;
> +
> +/* EOF */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
> new file mode 100644
> index 0000000000..f2dba47488
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
> @@ -0,0 +1,93 @@
> +/*
> + * nthw_fpga_mod_defs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_MOD_DEFS_H_
> +#define _NTHW_FPGA_MOD_DEFS_H_
> +
> +#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the > first element */
> +#define MOD_CAT (0x30b447c2UL)
> +#define MOD_CB (0x97db0a27UL)
> +#define MOD_COR (0x4754cf79UL)
> +#define MOD_CPY (0x1ddc186fUL)
> +#define MOD_CSU (0x3f470787UL)
> +#define MOD_DBS (0x80b29727UL)
> +#define MOD_DDP (0x4fe1611bUL)
> +#define MOD_EPP (0x608ddc79UL)
> +#define MOD_EQM (0x1a9081e1UL)
> +#define MOD_FHM (0x83d696a0UL)
> +#define MOD_FLM (0xe7ba53a4UL)
> +#define MOD_GFG (0xfc423807UL)
> +#define MOD_GMF (0x68b1d15aUL)
> +#define MOD_GPIO_PHY (0xbbe81659UL)
> +#define MOD_GPIO_PHY_PORTS (0xea12bddaUL)
> +#define MOD_GPIO_SFPP (0x628c8692UL)
> +#define MOD_HFU (0x4a70e72UL)
> +#define MOD_HIF (0x7815363UL)
> +#define MOD_HSH (0x501484bfUL)
> +#define MOD_I2CM (0x93bc7780UL)
> +#define MOD_IFR (0x9b01f1e6UL)
> +#define MOD_IGAM (0xf3b0bfb9UL)
> +#define MOD_IIC (0x7629cddbUL)
> +#define MOD_INS (0x24df4b78UL)
> +#define MOD_IOA (0xce7d0b71UL)
> +#define MOD_IPF (0x9d43904cUL)
> +#define MOD_KM (0xcfbd9dbeUL)
> +#define MOD_MAC (0xb9f9ef0fUL)
> +#define MOD_MAC_PCS (0x7abe24c7UL)
> +#define MOD_MAC_PCS_XXV (0x3ea7bfeaUL)
> +#define MOD_MAC_RX (0x6347b490UL)
> +#define MOD_MAC_TFG (0x1a1aac23UL)
> +#define MOD_MAC_TX (0x351d1316UL)
> +#define MOD_MSK (0xcfd617eeUL)
> +#define MOD_PCIE3 (0xfbc48c18UL)
> +#define MOD_PCI_RD_TG (0x9ad9eed2UL)
> +#define MOD_PCI_TA (0xfb431997UL)
> +#define MOD_PCI_WR_TG (0x274b69e1UL)
> +#define MOD_PCS (0x8286adcaUL)
> +#define MOD_PCS100 (0xa03da74fUL)
> +#define MOD_PDB (0xa7771bffUL)
> +#define MOD_PDI (0x30a5c277UL)
> +#define MOD_PHY_TILE (0x4e0aef6eUL)
> +#define MOD_QSL (0x448ed859UL)
> +#define MOD_QSPI (0x29862c6cUL)
> +#define MOD_R2DRP (0x8b673fa6UL)
> +#define MOD_RAC (0xae830b42UL)
> +#define MOD_RFD (0x7fa60826UL)
> +#define MOD_RMC (0x236444eUL)
> +#define MOD_ROA (0xde0e47e0UL)
> +#define MOD_RPF (0x8d30dcddUL)
> +#define MOD_RPL (0x6de535c3UL)
> +#define MOD_RPP_LR (0xba7f945cUL)
> +#define MOD_RST9563 (0x385d6d1dUL)
> +#define MOD_SDC (0xd2369530UL)
> +#define MOD_SLC (0x1aef1f38UL)
> +#define MOD_SLC_LR (0x969fc50bUL)
> +#define MOD_SPIM (0x1da437bfUL)
> +#define MOD_SPIS (0xe7ab0adcUL)
> +#define MOD_STA (0x76fae64dUL)
> +#define MOD_TEMPMON (0x2f77020dUL)
> +#define MOD_TINT (0xb8aea9feUL)
> +#define MOD_TSM (0x35422a24UL)
> +#define MOD_TX_CPY (0x60acf217UL)
> +#define MOD_TX_CSI (0x5636b1b0UL)
> +#define MOD_TX_CSO (0xbf551485UL)
> +#define MOD_TX_INS (0x59afa100UL)
> +#define MOD_TX_RPL (0x1095dfbbUL)
> +#define MOD_IDX_COUNT (69)
> +
> +/* aliases - only aliases go below this point */
> +#define MOD_MAC10 (MOD_MAC10G)       /*= alias */
> +
> +#endif       /* _NTHW_FPGA_MOD_DEFS_H_ = */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c<= br> > b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
> new file mode 100644
> index 0000000000..51e5cf4649
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
> @@ -0,0 +1,78 @@
> +
> +
> +#include "nthw_fpga_mod_str_map.h"
> +const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] =3D { { > MOD_CAT, "CAT" },
> +     { MOD_CB, "CB" },
> +     { MOD_COR, "COR" },
> +     { MOD_CPY, "CPY" },
> +     { MOD_CSU, "CSU" },
> +     { MOD_DBS, "DBS" },
> +     { MOD_DDP, "DDP" },
> +     { MOD_EPP, "EPP" },
> +     { MOD_EQM, "EQM" },
> +     { MOD_FHM, "FHM" },
> +     { MOD_FLM, "FLM" },
> +     { MOD_GFG, "GFG" },
> +     { MOD_GMF, "GMF" },
> +     { MOD_GPIO_PHY, "GPIO_PHY" },
> +     {
> +           &nb= sp; MOD_GPIO_PHY_PORTS,
> +           &nb= sp; "GPIO_PHY_PORTS"
> +     },
> +     { MOD_GPIO_SFPP, "GPIO_SFPP" }, > +     { MOD_HFU, "HFU" },
> +     { MOD_HIF, "HIF" },
> +     { MOD_HSH, "HSH" },
> +     { MOD_I2CM, "I2CM" },
> +     { MOD_IFR, "IFR" },
> +     { MOD_IGAM, "IGAM" },
> +     { MOD_IIC, "IIC" },
> +     { MOD_INS, "INS" },
> +     { MOD_IOA, "IOA" },
> +     { MOD_IPF, "IPF" },
> +     { MOD_KM, "KM" },
> +     { MOD_MAC, "MAC" },
> +     { MOD_MAC_PCS, "MAC_PCS" },
> +     { MOD_MAC_PCS_XXV, "MAC_PCS_XXV" }= ,
> +     { MOD_MAC_RX, "MAC_RX" },
> +     { MOD_MAC_TFG, "MAC_TFG" },
> +     { MOD_MAC_TX, "MAC_TX" },
> +     { MOD_MSK, "MSK" },
> +     { MOD_PCIE3, "PCIE3" },
> +     { MOD_PCI_RD_TG, "PCI_RD_TG" }, > +     { MOD_PCI_TA, "PCI_TA" },
> +     { MOD_PCI_WR_TG, "PCI_WR_TG" }, > +     { MOD_PCS, "PCS" },
> +     { MOD_PCS100, "PCS100" },
> +     { MOD_PDB, "PDB" },
> +     { MOD_PDI, "PDI" },
> +     { MOD_PHY_TILE, "PHY_TILE" },
> +     { MOD_QSL, "QSL" },
> +     { MOD_QSPI, "QSPI" },
> +     { MOD_R2DRP, "R2DRP" },
> +     { MOD_RAC, "RAC" },
> +     { MOD_RFD, "RFD" },
> +     { MOD_RMC, "RMC" },
> +     { MOD_ROA, "ROA" },
> +     { MOD_RPF, "RPF" },
> +     { MOD_RPL, "RPL" },
> +     { MOD_RPP_LR, "RPP_LR" },
> +     { MOD_RST9563, "RST9563" },
> +     { MOD_SDC, "SDC" },
> +     { MOD_SLC, "SLC" },
> +     { MOD_SLC_LR, "SLC_LR" },
> +     { MOD_SPIM, "SPIM" },
> +     { MOD_SPIS, "SPIS" },
> +     { MOD_STA, "STA" },
> +     { MOD_TEMPMON, "TEMPMON" },
> +     { MOD_TINT, "TINT" },
> +     { MOD_TSM, "TSM" },
> +     { MOD_TX_CPY, "TX_CPY" },
> +     { MOD_TX_CSI, "TX_CSI" },
> +     { MOD_TX_CSO, "TX_CSO" },
> +     { MOD_TX_INS, "TX_INS" },
> +     { MOD_TX_RPL, "TX_RPL" },
> +     { 0UL, NULL }
> +};
> +
> +/* EOF */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h<= br> > b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
> new file mode 100644
> index 0000000000..6bebe56329
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
> @@ -0,0 +1,11 @@
> +
> +
> +#include "nthw_fpga_mod_defs.h"
> +#include "fpga_model.h"
> +struct nthw_fpga_mod_str_s {
> +     const nthw_id_t a;
> +     const char *b;
> +};
> +extern const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[]; > +
> +/* EOF */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
> new file mode 100644
> index 0000000000..a51d8b3888
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
> @@ -0,0 +1,232 @@
> +/*
> + * nthw_fpga_param_defs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_PARAM_DEFS_
> +#define _NTHW_FPGA_PARAM_DEFS_
> +
> +#define NTHW_PARAM_UNKNOWN (0UL)
> +#define NT_BUILD_NUMBER (0x489b50fbUL)
> +#define NT_BUILD_TIME (0x6e66771fUL)
> +#define NT_CATEGORIES (0xfdbcebdcUL)
> +#define NT_CAT_CCT_SIZE (0x3a505ddaUL)
> +#define NT_CAT_CTE_SIZE (0x50a32ea4UL)
> +#define NT_CAT_CTS_SIZE (0x852ccf22UL)
> +#define NT_CAT_DCT_PRESENT (0x898c5638UL)
> +#define NT_CAT_DCT_SIZE (0x309554c3UL)
> +#define NT_CAT_END_OFS_SUPPORT (0x925f11d9UL)
> +#define NT_CAT_FPC (0x417fd17bUL)
> +#define NT_CAT_FTE_SIZE (0x184320c0UL)
> +#define NT_CAT_FUNCS (0x6af66e16UL)
> +#define NT_CAT_KCC_BANKS (0x426534f3UL)
> +#define NT_CAT_KCC_PRESENT (0xd2d58d46UL)
> +#define NT_CAT_KCC_SIZE (0xf766744cUL)
> +#define NT_CAT_KCE_SIZE (0x213f9751UL)
> +#define NT_CAT_KM_IF_CNT (0x8c934524UL)
> +#define NT_CAT_KM_IF_M0 (0x666dd699UL)
> +#define NT_CAT_KM_IF_M1 (0x116ae60fUL)
> +#define NT_CAT_N_CMP (0x3a692ad4UL)
> +#define NT_CAT_N_EXT (0xe3c746bUL)
> +#define NT_CAT_N_LEN (0x3e3da82UL)
> +#define NT_CAT_RCK_SIZE (0x78c1dc21UL)
> +#define NT_CAT_VALUES (0xec523dbbUL)
> +#define NT_CB_DEBUG (0xa0bccd31UL)
> +#define NT_COR_CATEGORIES (0x7392b58dUL)
> +#define NT_COR_PRESENT (0xbe0d1fdeUL)
> +#define NT_CPY_MASK_MEM (0x24f85e48UL)
> +#define NT_CSU_PRESENT (0xe7fe1371UL)
> +#define NT_DBS_PRESENT (0x75b395aeUL)
> +#define NT_DBS_RX_QUEUES (0x927069fUL)
> +#define NT_DBS_TX_PORTS (0xae2d6250UL)
> +#define NT_DBS_TX_QUEUES (0x7a3d7f15UL)
> +#define NT_DDP_PRESENT (0x4120d92cUL)
> +#define NT_DDP_TBL_DEPTH (0xf52e011UL)
> +#define NT_EMI_SPLIT_STEPS (0xe4b3210fUL)
> +#define NT_EOF_TIMESTAMP_ONLY (0xe476891bUL)
> +#define NT_EPP_CATEGORIES (0xf41c134bUL)
> +#define NT_EXT_MEM_NUM (0x43a48169UL)
> +#define NT_EXT_MEM_SINGLE_SIZE_GB (0x1817e71eUL)
> +#define NT_FLM_CACHE (0x414157e4UL)
> +#define NT_FLM_CATEGORIES (0x3477c5a3UL)
> +#define NT_FLM_ENTRY_SIZE (0x9ca7f0b6UL)
> +#define NT_FLM_LOAD_APS_MAX (0xe4d4f4edUL)
> +#define NT_FLM_LOAD_LPS_MAX (0x8503952dUL)
> +#define NT_FLM_PRESENT (0x5714853fUL)
> +#define NT_FLM_PRIOS (0x92afe487UL)
> +#define NT_FLM_PST_PROFILES (0xf4a0d627UL)
> +#define NT_FLM_SCRUB_PROFILES (0x6b6f6b21UL)
> +#define NT_FLM_SIZE_MB (0x5667a5deUL)
> +#define NT_FLM_STATEFUL (0xc8bf17a8UL)
> +#define NT_FLM_VARIANT (0x5beb9485UL)
> +#define NT_GFG_PRESENT (0x149640a8UL)
> +#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (0x7b5ad1e0UL)
> +#define NT_GMF_FCS_PRESENT (0xc15365efUL)
> +#define NT_GMF_IFG_SPEED_DIV (0xc06cdcbdUL)
> +#define NT_GMF_IFG_SPEED_DIV100G (0x43e1fb80UL)
> +#define NT_GMF_IFG_SPEED_DIV100M (0xa334129eUL)
> +#define NT_GMF_IFG_SPEED_DIV10G (0x49197e96UL)
> +#define NT_GMF_IFG_SPEED_DIV1G (0xb1324f18UL)
> +#define NT_GMF_IFG_SPEED_DIV2 (0xafc51de0UL)
> +#define NT_GMF_IFG_SPEED_DIV25G (0x3628348aUL)
> +#define NT_GMF_IFG_SPEED_DIV3 (0xd8c22d76UL)
> +#define NT_GMF_IFG_SPEED_DIV4 (0x46a6b8d5UL)
> +#define NT_GMF_IFG_SPEED_DIV40G (0x4fd2bc7dUL)
> +#define NT_GMF_IFG_SPEED_DIV50G (0x4e10d64aUL)
> +#define NT_GMF_IFG_SPEED_MUL (0xd4a84315UL)
> +#define NT_GMF_IFG_SPEED_MUL100G (0x883df390UL)
> +#define NT_GMF_IFG_SPEED_MUL100M (0x68e81a8eUL)
> +#define NT_GMF_IFG_SPEED_MUL10G (0xf4a2e226UL)
> +#define NT_GMF_IFG_SPEED_MUL1G (0xb75ce3e8UL)
> +#define NT_GMF_IFG_SPEED_MUL2 (0x77dcf2a5UL)
> +#define NT_GMF_IFG_SPEED_MUL25G (0x8b93a83aUL)
> +#define NT_GMF_IFG_SPEED_MUL3 (0xdbc233UL)
> +#define NT_GMF_IFG_SPEED_MUL4 (0x9ebf5790UL)
> +#define NT_GMF_IFG_SPEED_MUL40G (0xf26920cdUL)
> +#define NT_GMF_IFG_SPEED_MUL50G (0xf3ab4afaUL)
> +#define NT_GROUP_ID (0x113978c5UL)
> +#define NT_HFU_PRESENT (0x558de99UL)
> +#define NT_HIF_MSIX_BAR (0xc10014e9UL)
> +#define NT_HIF_MSIX_PBA_OFS (0x900307fbUL)
> +#define NT_HIF_MSIX_PRESENT (0x77a98665UL)
> +#define NT_HIF_MSIX_TBL_OFS (0x9cdce759UL)
> +#define NT_HIF_MSIX_TBL_SIZE (0x6ce7b76UL)
> +#define NT_HIF_PER_PS (0x38c954b1UL)
> +#define NT_HIF_SRIOV_PRESENT (0x49f8c203UL)
> +#define NT_HIF_VF_OFFSET (0x9fb3c9b0UL)
> +#define NT_HSH_CATEGORIES (0xf43894dcUL)
> +#define NT_HSH_TOEPLITZ (0x603f96a3UL)
> +#define NT_HST_CATEGORIES (0xfd2a34a1UL)
> +#define NT_HST_PRESENT (0xd3a48076UL)
> +#define NT_IOA_CATEGORIES (0xda23501aUL)
> +#define NT_IOA_PRESENT (0xc9ef39eeUL)
> +#define NT_IPF_PRESENT (0x7b2b8e42UL)
> +#define NT_KM_CAM_BANKS (0x3cad3371UL)
> +#define NT_KM_CAM_RECORDS (0x24256ab5UL)
> +#define NT_KM_CAM_REC_WORDS (0xe8e0ef3UL)
> +#define NT_KM_CATEGORIES (0x4d2a4c96UL)
> +#define NT_KM_END_OFS_SUPPORT (0x4a90ff33UL)
> +#define NT_KM_EXT_EXTRACTORS (0xf135193cUL)
> +#define NT_KM_FLOW_SETS (0x359cddf3UL)
> +#define NT_KM_FLOW_TYPES (0xb79ff984UL)
> +#define NT_KM_PRESENT (0xb54eaee3UL)
> +#define NT_KM_SWX_PRESENT (0x2715aebeUL)
> +#define NT_KM_SYNERGY_MATCH (0x935e5b7fUL)
> +#define NT_KM_TCAM_BANKS (0x6f6f0894UL)
> +#define NT_KM_TCAM_BANK_WIDTH (0x4c5015aeUL)
> +#define NT_KM_TCAM_HIT_QUAL (0xd3fb2aafUL)
> +#define NT_KM_TCAM_KEYWAY (0x45318c61UL)
> +#define NT_KM_WIDE (0x7ba773c4UL)
> +#define NT_LR_PRESENT (0x24eb383aUL)
> +#define NT_LTX_CATEGORIES (0x9cfff063UL)
> +#define NT_MCU_DRAM_SIZE (0xe33d7922UL)
> +#define NT_MCU_PRESENT (0x9226b99fUL)
> +#define NT_MCU_TYPE (0xce45b840UL)
> +#define NT_MDG_DEBUG_FLOW_CONTROL (0x4f199a18UL)
> +#define NT_MDG_DEBUG_REG_READ_BACK (0xc674095UL)
> +#define NT_MSK_CATEGORIES (0x7052841UL)
> +#define NT_MSK_PRESENT (0xd18aa194UL)
> +#define NT_NAME (0x224bb693UL)
> +#define NT_NFV_OVS_PRODUCT (0xd8223124UL)
> +#define NT_NIMS (0xd88c527aUL)
> +#define NT_PATCH_NUMBER (0xecd14417UL)
> +#define NT_PCI_DEVICE_ID (0x254dede8UL)
> +#define NT_PCI_INT_AVR (0x40c50ef1UL)
> +#define NT_PCI_INT_EQM (0x85853d1fUL)
> +#define NT_PCI_INT_IIC0 (0xbf363717UL)
> +#define NT_PCI_INT_IIC1 (0xc8310781UL)
> +#define NT_PCI_INT_IIC2 (0x5138563bUL)
> +#define NT_PCI_INT_IIC3 (0x263f66adUL)
> +#define NT_PCI_INT_IIC4 (0xb85bf30eUL)
> +#define NT_PCI_INT_IIC5 (0xcf5cc398UL)
> +#define NT_PCI_INT_PORT (0x8facd5e1UL)
> +#define NT_PCI_INT_PORT0 (0x2359a11aUL)
> +#define NT_PCI_INT_PORT1 (0x545e918cUL)
> +#define NT_PCI_INT_PPS (0x7c7c50a6UL)
> +#define NT_PCI_INT_QSPI (0x731ce6cbUL)
> +#define NT_PCI_INT_SPIM (0x473efd18UL)
> +#define NT_PCI_INT_SPIS (0xbd31c07bUL)
> +#define NT_PCI_INT_STA (0xe9ef5ab3UL)
> +#define NT_PCI_INT_TIMER (0x14ad9f2fUL)
> +#define NT_PCI_INT_TINT (0xe2346359UL)
> +#define NT_PCI_TA_TG_PRESENT (0x3cc176a0UL)
> +#define NT_PCI_VENDOR_ID (0x47eac44fUL)
> +#define NT_PDB_CATEGORIES (0x8290fe65UL)
> +#define NT_PHY_ANEG_PRESENT (0x626ddda5UL)
> +#define NT_PHY_KRFEC_PRESENT (0x8ab2cf25UL)
> +#define NT_PHY_PORTS (0x41986112UL)
> +#define NT_PHY_PORTS_PER_QUAD (0xf4b396e6UL)
> +#define NT_PHY_QUADS (0x17fef021UL)
> +#define NT_PHY_RSFEC_PRESENT (0x22852f78UL)
> +#define NT_PORTS (0x32e8ff06UL)
> +#define NT_PROD_ID_LAYOUT_VERSION (0x42106495UL)
> +#define NT_QM_BLOCKS (0xb735e210UL)
> +#define NT_QM_CELLS (0x510e07f1UL)
> +#define NT_QM_CELL_SIZE (0xbddf0f74UL)
> +#define NT_QM_PRESENT (0x85c2bfc2UL)
> +#define NT_QSL_CATEGORIES (0x3fda6c8fUL)
> +#define NT_QSL_COLOR_SEL_BW (0x549c264dUL)
> +#define NT_QSL_QST_SIZE (0x41d03837UL)
> +#define NT_QUEUES (0xf8a94e49UL)
> +#define NT_RAC_RAB_INTERFACES (0x7b742b2bUL)
> +#define NT_RAC_RAB_OB_UPDATE (0x3a44d066UL)
> +#define NT_REVISION_ID (0xd212229fUL)
> +#define NT_RMC_LAG_GROUPS (0xa7d5b2fbUL)
> +#define NT_RMC_PRESENT (0x6e3b82daUL)
> +#define NT_ROA_CATEGORIES (0xf3a9579bUL)
> +#define NT_ROA_PRESENT (0x44387a61UL)
> +#define NT_RPF_MATURING_DEL_DEFAULT (0xd4e7e4d2UL)
> +#define NT_RPF_PRESENT (0xf6fccdcdUL)
> +#define NT_RPP_PER_PS (0xb2f28916UL)
> +#define NT_RTX_PRESENT (0x9b15f454UL)
> +#define NT_RX_HOST_BUFFERS (0x9207c413UL)
> +#define NT_RX_PORTS (0x3639a86eUL)
> +#define NT_RX_PORT_REPLICATE (0xed09d794UL)
> +#define NT_SLB_PRESENT (0x570c2267UL)
> +#define NT_SLC_LR_PRESENT (0xe600975aUL)
> +#define NT_SLC_PRESENT (0x40773624UL)
> +#define NT_STA_COLORS (0xe1e90b5bUL)
> +#define NT_STA_LOAD_AVG_RX (0x94efbfa1UL)
> +#define NT_STA_LOAD_AVG_TX (0xc2b51827UL)
> +#define NT_STA_RX_PORTS (0x75da30f9UL)
> +#define NT_TBH_DEBUG_DLN (0x1faf2e1dUL)
> +#define NT_TBH_PRESENT (0xf5d08dc9UL)
> +#define NT_TFD_PRESENT (0x1a0fdea7UL)
> +#define NT_TPE_CATEGORIES (0x9b1a54bdUL)
> +#define NT_TSM_OST_ONLY (0x4899103aUL)
> +#define NT_TS_APPEND (0x4544c692UL)
> +#define NT_TS_INJECT_PRESENT (0xb2aa4f0eUL)
> +#define NT_TX_CPY_PACKET_READERS (0x37f470f0UL)
> +#define NT_TX_CPY_PRESENT (0xe54af81cUL)
> +#define NT_TX_CPY_SIDEBAND_READERS (0x52220d68UL)
> +#define NT_TX_CPY_VARIANT (0xe9b5e9a6UL)
> +#define NT_TX_CPY_WRITERS (0xd9dbd4UL)
> +#define NT_TX_HOST_BUFFERS (0xb0fd10e1UL)
> +#define NT_TX_INS_OFS_ZERO (0x5510aa2dUL)
> +#define NT_TX_INS_PRESENT (0xabac9b5dUL)
> +#define NT_TX_MTU_PROFILE_IFR (0x8d313bc2UL)
> +#define NT_TX_ON_TIMESTAMP (0x51d7fce0UL)
> +#define NT_TX_PORTS (0xf056a1e9UL)
> +#define NT_TX_PORT_REPLICATE (0x4a3d609cUL)
> +#define NT_TX_RPL_DEPTH (0x61f86eb9UL)
> +#define NT_TX_RPL_EXT_CATEGORIES (0x421e973cUL)
> +#define NT_TX_RPL_OFS_ZERO (0x2bfd677UL)
> +#define NT_TX_RPL_PRESENT (0x6c65e429UL)
> +#define NT_TYPE_ID (0xd03446b2UL)
> +#define NT_USE_TRIPLE_SPEED (0x54350589UL)
> +#define NT_UUID (0xad179833UL)
> +#define NT_VERSION (0x92295f02UL)
> +#define NT_VERSION_ID (0xb4becc51UL)
> +#define NT_VLI_PRESENT (0xa40e10f8UL)
> +
> +#endif       /* _NTHW_FPGA_PARAM_DEFS_ = */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
> new file mode 100644
> index 0000000000..9b24398183
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
> @@ -0,0 +1,94 @@
> +/*
> + * nthw_fpga_reg_defs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_
> +#define _NTHW_FPGA_REG_DEFS_
> +
> +#include "nthw_fpga_reg_defs_cat.h"
> +#include "nthw_fpga_reg_defs_cb.h"
> +#include "nthw_fpga_reg_defs_cor.h"
> +#include "nthw_fpga_reg_defs_cpy.h"
> +#include "nthw_fpga_reg_defs_csu.h"
> +#include "nthw_fpga_reg_defs_dbs.h"
> +#include "nthw_fpga_reg_defs_ddp.h"
> +#include "nthw_fpga_reg_defs_epp.h"
> +#include "nthw_fpga_reg_defs_eqm.h"
> +#include "nthw_fpga_reg_defs_fhm.h"
> +#include "nthw_fpga_reg_defs_flm.h"
> +#include "nthw_fpga_reg_defs_gfg.h"
> +#include "nthw_fpga_reg_defs_gmf.h"
> +#include "nthw_fpga_reg_defs_gpio_phy.h"
> +#include "nthw_fpga_reg_defs_gpio_phy_ports.h"
> +#include "nthw_fpga_reg_defs_gpio_sfpp.h"
> +#include "nthw_fpga_reg_defs_hfu.h"
> +#include "nthw_fpga_reg_defs_hif.h"
> +#include "nthw_fpga_reg_defs_hsh.h"
> +#include "nthw_fpga_reg_defs_i2cm.h"
> +#include "nthw_fpga_reg_defs_ifr.h"
> +#include "nthw_fpga_reg_defs_igam.h"
> +#include "nthw_fpga_reg_defs_iic.h"
> +#include "nthw_fpga_reg_defs_ins.h"
> +#include "nthw_fpga_reg_defs_ioa.h"
> +#include "nthw_fpga_reg_defs_ipf.h"
> +#include "nthw_fpga_reg_defs_km.h"
> +#include "nthw_fpga_reg_defs_mac.h"
> +#include "nthw_fpga_reg_defs_mac_pcs.h"
> +#include "nthw_fpga_reg_defs_mac_pcs_xxv.h"
> +#include "nthw_fpga_reg_defs_mac_rx.h"
> +#include "nthw_fpga_reg_defs_mac_tfg.h"
> +#include "nthw_fpga_reg_defs_mac_tx.h"
> +#include "nthw_fpga_reg_defs_msk.h"
> +#include "nthw_fpga_reg_defs_pcie3.h"
> +#include "nthw_fpga_reg_defs_pci_rd_tg.h"
> +#include "nthw_fpga_reg_defs_pci_ta.h"
> +#include "nthw_fpga_reg_defs_pci_wr_tg.h"
> +#include "nthw_fpga_reg_defs_pcm_nt400dxx.h"
> +#include "nthw_fpga_reg_defs_pcm_nt50b01_01.h"
> +#include "nthw_fpga_reg_defs_pcs.h"
> +#include "nthw_fpga_reg_defs_pcs100.h"
> +#include "nthw_fpga_reg_defs_pdb.h"
> +#include "nthw_fpga_reg_defs_pdi.h"
> +#include "nthw_fpga_reg_defs_phy_tile.h"
> +#include "nthw_fpga_reg_defs_prm_nt400dxx.h"
> +#include "nthw_fpga_reg_defs_prm_nt50b01_01.h"
> +#include "nthw_fpga_reg_defs_qsl.h"
> +#include "nthw_fpga_reg_defs_qspi.h"
> +#include "nthw_fpga_reg_defs_r2drp.h"
> +#include "nthw_fpga_reg_defs_rac.h"
> +#include "nthw_fpga_reg_defs_rfd.h"
> +#include "nthw_fpga_reg_defs_rmc.h"
> +#include "nthw_fpga_reg_defs_roa.h"
> +#include "nthw_fpga_reg_defs_rpf.h"
> +#include "nthw_fpga_reg_defs_rpl.h"
> +#include "nthw_fpga_reg_defs_rpp_lr.h"
> +#include "nthw_fpga_reg_defs_rst9563.h"
> +#include "nthw_fpga_reg_defs_sdc.h"
> +#include "nthw_fpga_reg_defs_slc.h"
> +#include "nthw_fpga_reg_defs_slc_lr.h"
> +#include "nthw_fpga_reg_defs_spim.h"
> +#include "nthw_fpga_reg_defs_spis.h"
> +#include "nthw_fpga_reg_defs_sta.h"
> +#include "nthw_fpga_reg_defs_tempmon.h"
> +#include "nthw_fpga_reg_defs_tint.h"
> +#include "nthw_fpga_reg_defs_tsm.h"
> +#include "nthw_fpga_reg_defs_tx_cpy.h"
> +#include "nthw_fpga_reg_defs_tx_csi.h"
> +#include "nthw_fpga_reg_defs_tx_cso.h"
> +#include "nthw_fpga_reg_defs_tx_ins.h"
> +#include "nthw_fpga_reg_defs_tx_rpl.h"
> +
> +/* aliases */
> +
> +#endif       /* NTHW_FPGA_REG_DEFS_ */<= br> > +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
> new file mode 100644
> index 0000000000..1748a6cbb5
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
> @@ -0,0 +1,237 @@
> +/*
> + * nthw_fpga_reg_defs_cat.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_CAT_
> +#define _NTHW_FPGA_REG_DEFS_CAT_
> +
> +/* CAT */
> +#define NTHW_MOD_CAT (0x30b447c2UL)
> +#define CAT_CCT_CTRL (0x234d3a78UL)
> +#define CAT_CCT_CTRL_ADR (0x6146f230UL)
> +#define CAT_CCT_CTRL_CNT (0x714e6be1UL)
> +#define CAT_CCT_DATA (0x8c9cb861UL)
> +#define CAT_CCT_DATA_COLOR (0x27e29b73UL)
> +#define CAT_CCT_DATA_KM (0x4ac2435fUL)
> +#define CAT_CFN_CTRL (0xd3383422UL)
> +#define CAT_CFN_CTRL_ADR (0x209d4f53UL)
> +#define CAT_CFN_CTRL_CNT (0x3095d682UL)
> +#define CAT_CFN_DATA (0x7ce9b63bUL)
> +#define CAT_CFN_DATA_ENABLE (0xd2ae88e2UL)
> +#define CAT_CFN_DATA_ERR_CV (0x22ca6722UL)
> +#define CAT_CFN_DATA_ERR_FCS (0xc45c40bfUL)
> +#define CAT_CFN_DATA_ERR_INV (0xac48d40UL)
> +#define CAT_CFN_DATA_ERR_L3_CS (0x55fb7895UL)
> +#define CAT_CFN_DATA_ERR_L4_CS (0xc82c402cUL)
> +#define CAT_CFN_DATA_ERR_TNL_L3_CS (0x51e668edUL)
> +#define CAT_CFN_DATA_ERR_TNL_L4_CS (0xcc315054UL)
> +#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (0x948d9686UL)
> +#define CAT_CFN_DATA_ERR_TRUNC (0x237fdf4fUL)
> +#define CAT_CFN_DATA_ERR_TTL_EXP (0x6edc7101UL)
> +#define CAT_CFN_DATA_FLM_OR (0xd82cf0b3UL)
> +#define CAT_CFN_DATA_INV (0xc2e6afa4UL)
> +#define CAT_CFN_DATA_KM0_OR (0xc087b29cUL)
> +#define CAT_CFN_DATA_KM1_OR (0x783bd5f9UL)
> +#define CAT_CFN_DATA_KM_OR (0x58fbb39eUL)
> +#define CAT_CFN_DATA_LC (0x3dfcfb34UL)
> +#define CAT_CFN_DATA_LC_INV (0x72af18aUL)
> +#define CAT_CFN_DATA_MAC_PORT (0xcd340483UL)
> +#define CAT_CFN_DATA_PM_AND_INV (0x3ae1c6afUL)
> +#define CAT_CFN_DATA_PM_CMB (0xf06e8f63UL)
> +#define CAT_CFN_DATA_PM_CMP (0x3d7fe2bUL)
> +#define CAT_CFN_DATA_PM_DCT (0x9f760139UL)
> +#define CAT_CFN_DATA_PM_EXT_INV (0x7bc194b8UL)
> +#define CAT_CFN_DATA_PM_INV (0xcc0e8d0bUL)
> +#define CAT_CFN_DATA_PM_OR_INV (0x7790b2fUL)
> +#define CAT_CFN_DATA_PTC_CFP (0x98d6c9edUL)
> +#define CAT_CFN_DATA_PTC_FRAG (0x9bb1ab3cUL)
> +#define CAT_CFN_DATA_PTC_INV (0xb4fb6306UL)
> +#define CAT_CFN_DATA_PTC_IP_PROT (0xfee4889bUL)
> +#define CAT_CFN_DATA_PTC_ISL (0xb6f5f660UL)
> +#define CAT_CFN_DATA_PTC_L2 (0xdb7388deUL)
> +#define CAT_CFN_DATA_PTC_L3 (0xac74b848UL)
> +#define CAT_CFN_DATA_PTC_L4 (0x32102debUL)
> +#define CAT_CFN_DATA_PTC_MAC (0x59b733feUL)
> +#define CAT_CFN_DATA_PTC_MPLS (0xe0405263UL)
> +#define CAT_CFN_DATA_PTC_TNL_FRAG (0x76e4a788UL)
> +#define CAT_CFN_DATA_PTC_TNL_IP_PROT (0x8b0734cdUL)
> +#define CAT_CFN_DATA_PTC_TNL_L2 (0xec64285eUL)
> +#define CAT_CFN_DATA_PTC_TNL_L3 (0x9b6318c8UL)
> +#define CAT_CFN_DATA_PTC_TNL_L4 (0x5078d6bUL)
> +#define CAT_CFN_DATA_PTC_TNL_MPLS (0xd155ed7UL)
> +#define CAT_CFN_DATA_PTC_TNL_VLAN (0x4999c6c9UL)
> +#define CAT_CFN_DATA_PTC_TUNNEL (0x2ac66873UL)
> +#define CAT_CFN_DATA_PTC_VLAN (0xa4ccca7dUL)
> +#define CAT_CFN_DATA_PTC_VNTAG (0x23d64f2aUL)
> +#define CAT_COT_CTRL (0xe4ed500cUL)
> +#define CAT_COT_CTRL_ADR (0x6b5c60f7UL)
> +#define CAT_COT_CTRL_CNT (0x7b54f926UL)
> +#define CAT_COT_DATA (0x4b3cd215UL)
> +#define CAT_COT_DATA_COLOR (0xbd582288UL)
> +#define CAT_COT_DATA_KM (0x50fea3d1UL)
> +#define CAT_COT_DATA_NFV_SB (0x2219c864UL)
> +#define CAT_CTE_CTRL (0x49be4906UL)
> +#define CAT_CTE_CTRL_ADR (0x2ee7c9aeUL)
> +#define CAT_CTE_CTRL_CNT (0x3eef507fUL)
> +#define CAT_CTE_DATA (0xe66fcb1fUL)
> +#define CAT_CTE_DATA_COL_ENABLE (0xa9ca226bUL)
> +#define CAT_CTE_DATA_COR_ENABLE (0xc0fb0172UL)
> +#define CAT_CTE_DATA_EPP_ENABLE (0xfcb9fbe8UL)
> +#define CAT_CTE_DATA_HSH_ENABLE (0x9f946603UL)
> +#define CAT_CTE_DATA_HST_ENABLE (0xb4804267UL)
> +#define CAT_CTE_DATA_IPF_ENABLE (0x5c5123caUL)
> +#define CAT_CTE_DATA_MSK_ENABLE (0xf732aaa4UL)
> +#define CAT_CTE_DATA_PDB_ENABLE (0xf28c946fUL)
> +#define CAT_CTE_DATA_QSL_ENABLE (0xc065c2dbUL)
> +#define CAT_CTE_DATA_SLC_ENABLE (0x6ec98deaUL)
> +#define CAT_CTE_DATA_TPE_ENABLE (0x8e2e71UL)
> +#define CAT_CTE_DATA_TX_INS_ENABLE (0x585922e3UL)
> +#define CAT_CTE_DATA_TX_RPL_ENABLE (0x468ee298UL)
> +#define CAT_CTS_CTRL (0x9c31a880UL)
> +#define CAT_CTS_CTRL_ADR (0x4573801UL)
> +#define CAT_CTS_CTRL_CNT (0x145fa1d0UL)
> +#define CAT_CTS_DATA (0x33e02a99UL)
> +#define CAT_CTS_DATA_CAT_A (0xa698040aUL)
> +#define CAT_CTS_DATA_CAT_B (0x3f9155b0UL)
> +#define CAT_DCT_CTRL (0x29883361UL)
> +#define CAT_DCT_CTRL_ADR (0x15de1bbfUL)
> +#define CAT_DCT_CTRL_CNT (0x5d6826eUL)
> +#define CAT_DCT_DATA (0x8659b178UL)
> +#define CAT_DCT_DATA_RES (0x74489a9dUL)
> +#define CAT_DCT_SEL (0xeb603410UL)
> +#define CAT_DCT_SEL_LU (0x60e126beUL)
> +#define CAT_EXO_CTRL (0xe9ea0993UL)
> +#define CAT_EXO_CTRL_ADR (0xdce26e40UL)
> +#define CAT_EXO_CTRL_CNT (0xcceaf791UL)
> +#define CAT_EXO_DATA (0x463b8b8aUL)
> +#define CAT_EXO_DATA_DYN (0x20ae0124UL)
> +#define CAT_EXO_DATA_OFS (0x82a78c82UL)
> +#define CAT_FCE_CTRL (0xa327e522UL)
> +#define CAT_FCE_CTRL_ADR (0x31896ff6UL)
> +#define CAT_FCE_CTRL_CNT (0x2181f627UL)
> +#define CAT_FCE_DATA (0xcf6673bUL)
> +#define CAT_FCE_DATA_ENABLE (0x8243e7a7UL)
> +#define CAT_FCS_CTRL (0x76a804a4UL)
> +#define CAT_FCS_CTRL_ADR (0x1b399e59UL)
> +#define CAT_FCS_CTRL_CNT (0xb310788UL)
> +#define CAT_FCS_DATA (0xd97986bdUL)
> +#define CAT_FCS_DATA_CATEGORY (0x69d964f3UL)
> +#define CAT_FTE0_CTRL (0x4f655742UL)
> +#define CAT_FTE0_CTRL_ADR (0xa786315fUL)
> +#define CAT_FTE0_CTRL_CNT (0xb78ea88eUL)
> +#define CAT_FTE0_DATA (0xe0b4d55bUL)
> +#define CAT_FTE0_DATA_ENABLE (0xe06dec95UL)
> +#define CAT_FTE1_CTRL (0x843984e7UL)
> +#define CAT_FTE1_CTRL_ADR (0x48445a61UL)
> +#define CAT_FTE1_CTRL_CNT (0x584cc3b0UL)
> +#define CAT_FTE1_DATA (0x2be806feUL)
> +#define CAT_FTE1_DATA_ENABLE (0x3dfb3510UL)
> +#define CAT_FTE_CTRL (0x15e4762UL)
> +#define CAT_FTE_CTRL_ADR (0xb644bebeUL)
> +#define CAT_FTE_CTRL_CNT (0xa64c276fUL)
> +#define CAT_FTE_DATA (0xae8fc57bUL)
> +#define CAT_FTE_DATA_ENABLE (0x813c710bUL)
> +#define CAT_FTE_FLM_CTRL (0x4a63f99eUL)
> +#define CAT_FTE_FLM_CTRL_ADR (0x3ed2141dUL)
> +#define CAT_FTE_FLM_CTRL_CNT (0x2eda8dccUL)
> +#define CAT_FTE_FLM_DATA (0xe5b27b87UL)
> +#define CAT_FTE_FLM_DATA_ENABLE (0x1786f0a8UL)
> +#define CAT_JOIN (0xf643707UL)
> +#define CAT_JOIN_J1 (0x494d06b2UL)
> +#define CAT_JOIN_J2 (0xd0445708UL)
> +#define CAT_KCC (0x26068f04UL)
> +#define CAT_KCC_CTRL (0xee7b13eeUL)
> +#define CAT_KCC_CTRL_ADR (0xa2381e5fUL)
> +#define CAT_KCC_CTRL_CNT (0xb230878eUL)
> +#define CAT_KCC_DATA (0x41aa91f7UL)
> +#define CAT_KCC_DATA_CATEGORY (0x3f0558aeUL)
> +#define CAT_KCC_DATA_ID (0x734a5784UL)
> +#define CAT_KCC_DATA_KEY (0x308cee9cUL)
> +#define CAT_KCE0_CTRL (0xc8548827UL)
> +#define CAT_KCE0_CTRL_ADR (0x982a5552UL)
> +#define CAT_KCE0_CTRL_CNT (0x8822cc83UL)
> +#define CAT_KCE0_DATA (0x67850a3eUL)
> +#define CAT_KCE0_DATA_ENABLE (0x36443e99UL)
> +#define CAT_KCE1_CTRL (0x3085b82UL)
> +#define CAT_KCE1_CTRL_ADR (0x77e83e6cUL)
> +#define CAT_KCE1_CTRL_CNT (0x67e0a7bdUL)
> +#define CAT_KCE1_DATA (0xacd9d99bUL)
> +#define CAT_KCE1_DATA_ENABLE (0xebd2e71cUL)
> +#define CAT_KCE_CTRL (0x3822f0f3UL)
> +#define CAT_KCE_CTRL_ADR (0xaf266e18UL)
> +#define CAT_KCE_CTRL_CNT (0xbf2ef7c9UL)
> +#define CAT_KCE_DATA (0x97f372eaUL)
> +#define CAT_KCE_DATA_ENABLE (0x7e4d95abUL)
> +#define CAT_KCS0_CTRL (0xcc5a21d3UL)
> +#define CAT_KCS0_CTRL_ADR (0xde695bdaUL)
> +#define CAT_KCS0_CTRL_CNT (0xce61c20bUL)
> +#define CAT_KCS0_DATA (0x638ba3caUL)
> +#define CAT_KCS0_DATA_CATEGORY (0x43dbd3eUL)
> +#define CAT_KCS1_CTRL (0x706f276UL)
> +#define CAT_KCS1_CTRL_ADR (0x31ab30e4UL)
> +#define CAT_KCS1_CTRL_CNT (0x21a3a935UL)
> +#define CAT_KCS1_DATA (0xa8d7706fUL)
> +#define CAT_KCS1_DATA_CATEGORY (0xbdc666d6UL)
> +#define CAT_KCS_CTRL (0xedad1175UL)
> +#define CAT_KCS_CTRL_ADR (0x85969fb7UL)
> +#define CAT_KCS_CTRL_CNT (0x959e0666UL)
> +#define CAT_KCS_DATA (0x427c936cUL)
> +#define CAT_KCS_DATA_CATEGORY (0x7b67c7e1UL)
> +#define CAT_LEN_CTRL (0x3bf03c13UL)
> +#define CAT_LEN_CTRL_ADR (0xcbebb623UL)
> +#define CAT_LEN_CTRL_CNT (0xdbe32ff2UL)
> +#define CAT_LEN_DATA (0x9421be0aUL)
> +#define CAT_LEN_DATA_DYN1 (0x6b539c5dUL)
> +#define CAT_LEN_DATA_DYN2 (0xf25acde7UL)
> +#define CAT_LEN_DATA_INV (0x299056d4UL)
> +#define CAT_LEN_DATA_LOWER (0x5f70c60fUL)
> +#define CAT_LEN_DATA_UPPER (0x3fb562b0UL)
> +#define CAT_RCK_CTRL (0x61dcbb83UL)
> +#define CAT_RCK_CTRL_ADR (0x205e89c6UL)
> +#define CAT_RCK_CTRL_CNT (0x30561017UL)
> +#define CAT_RCK_DATA (0xce0d399aUL)
> +#define CAT_RCK_DATA_CM0U (0xc643fdb9UL)
> +#define CAT_RCK_DATA_CM1U (0xdf58ccf8UL)
> +#define CAT_RCK_DATA_CM2U (0xf4759f3bUL)
> +#define CAT_RCK_DATA_CM3U (0xed6eae7aUL)
> +#define CAT_RCK_DATA_CM4U (0xa22f38bdUL)
> +#define CAT_RCK_DATA_CM5U (0xbb3409fcUL)
> +#define CAT_RCK_DATA_CM6U (0x90195a3fUL)
> +#define CAT_RCK_DATA_CM7U (0x89026b7eUL)
> +#define CAT_RCK_DATA_CML0 (0x78115e94UL)
> +#define CAT_RCK_DATA_CML1 (0xf166e02UL)
> +#define CAT_RCK_DATA_CML2 (0x961f3fb8UL)
> +#define CAT_RCK_DATA_CML3 (0xe1180f2eUL)
> +#define CAT_RCK_DATA_CML4 (0x7f7c9a8dUL)
> +#define CAT_RCK_DATA_CML5 (0x87baa1bUL)
> +#define CAT_RCK_DATA_CML6 (0x9172fba1UL)
> +#define CAT_RCK_DATA_CML7 (0xe675cb37UL)
> +#define CAT_RCK_DATA_SEL0 (0x261b58b3UL)
> +#define CAT_RCK_DATA_SEL1 (0x511c6825UL)
> +#define CAT_RCK_DATA_SEL2 (0xc815399fUL)
> +#define CAT_RCK_DATA_SEL3 (0xbf120909UL)
> +#define CAT_RCK_DATA_SEL4 (0x21769caaUL)
> +#define CAT_RCK_DATA_SEL5 (0x5671ac3cUL)
> +#define CAT_RCK_DATA_SEL6 (0xcf78fd86UL)
> +#define CAT_RCK_DATA_SEL7 (0xb87fcd10UL)
> +#define CAT_RCK_DATA_SEU0 (0xbd1bf1abUL)
> +#define CAT_RCK_DATA_SEU1 (0xca1cc13dUL)
> +#define CAT_RCK_DATA_SEU2 (0x53159087UL)
> +#define CAT_RCK_DATA_SEU3 (0x2412a011UL)
> +#define CAT_RCK_DATA_SEU4 (0xba7635b2UL)
> +#define CAT_RCK_DATA_SEU5 (0xcd710524UL)
> +#define CAT_RCK_DATA_SEU6 (0x5478549eUL)
> +#define CAT_RCK_DATA_SEU7 (0x237f6408UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_CAT= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h<= br> > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
> new file mode 100644
> index 0000000000..6389754e68
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
> @@ -0,0 +1,73 @@
> +/*
> + * nthw_fpga_reg_defs_cb.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_CB_
> +#define _NTHW_FPGA_REG_DEFS_CB_
> +
> +/* CB */
> +#define NTHW_MOD_CB (0x97db0a27UL)
> +#define CB_CTRL (0xea0f0d6UL)
> +#define CB_CTRL_BP (0x2fd8c552UL)
> +#define CB_CTRL_BYPASS (0xe1a5ba2dUL)
> +#define CB_CTRL_ENABLE (0xfd0df46bUL)
> +#define CB_CTRL_QMA (0xb79f07a3UL)
> +#define CB_CTRL_QME (0xb0f2c3baUL)
> +#define CB_DBG_BP (0x92018b7UL)
> +#define CB_DBG_BP_CNT (0x6f41db03UL)
> +#define CB_DBG_DQ (0x287d8fa7UL)
> +#define CB_DBG_DQ_MAX (0xc86c40UL)
> +#define CB_DBG_EGS_QUEUE (0x98831815UL)
> +#define CB_DBG_EGS_QUEUE_ADD (0x6edd6af5UL)
> +#define CB_DBG_EGS_QUEUE_AND (0x9432827fUL)
> +#define CB_DBG_FREE1200 (0x3ca31ccUL)
> +#define CB_DBG_FREE1200_CNT (0xa0a77389UL)
> +#define CB_DBG_FREE1800 (0xe5db41aUL)
> +#define CB_DBG_FREE1800_CNT (0x4d72cc7UL)
> +#define CB_DBG_FREE600 (0x44c0c493UL)
> +#define CB_DBG_FREE600_CNT (0x9291e1ffUL)
> +#define CB_DBG_H16 (0x39c5a313UL)
> +#define CB_DBG_H16_CNT (0x619373a5UL)
> +#define CB_DBG_H32 (0xc9e0588UL)
> +#define CB_DBG_H32_CNT (0xd9db746eUL)
> +#define CB_DBG_H64 (0x988a54f8UL)
> +#define CB_DBG_H64_CNT (0x656107dUL)
> +#define CB_DBG_HAVE (0x613fdd18UL)
> +#define CB_DBG_HAVE_CNT (0x631e610fUL)
> +#define CB_DBG_IGS_QUEUE (0x7eb7eb01UL)
> +#define CB_DBG_IGS_QUEUE_ADD (0xf467d30eUL)
> +#define CB_DBG_IGS_QUEUE_AND (0xe883b84UL)
> +#define CB_DBG_QM_CELL_CNT (0x72b9e681UL)
> +#define CB_DBG_QM_CELL_CNT_CNT (0x620fbb43UL)
> +#define CB_DBG_QM_CELL_XOR (0x92b23e64UL)
> +#define CB_DBG_QM_CELL_XOR_XOR (0xa3c18d97UL)
> +#define CB_QPM_CTRL (0xd4e2d7ecUL)
> +#define CB_QPM_CTRL_ADR (0xf81800a9UL)
> +#define CB_QPM_CTRL_CNT (0xe8109978UL)
> +#define CB_QPM_DATA (0x7b3355f5UL)
> +#define CB_QPM_DATA_P (0x537f8197UL)
> +#define CB_QUEUE_MAX (0x3edbf10bUL)
> +#define CB_QUEUE_MAX_MAX (0x55932199UL)
> +#define CB_STATUS (0x4de72da7UL)
> +#define CB_STATUS_BP (0xa6c5a817UL)
> +#define CB_STATUS_DB (0x3267ed9UL)
> +#define CB_STATUS_EMPTY (0xdb77607dUL)
> +#define CB_STATUS_IDLE (0xa0322cdUL)
> +#define CB_STATUS_OVF (0x904a7f92UL)
> +#define CB_TS_RATE (0xea3c6e96UL)
> +#define CB_TS_RATE_CNT (0xf8c7e925UL)
> +#define CB_TS_SAVE (0x60b66b71UL)
> +#define CB_TS_SAVE_MAX (0xfd15355eUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_CB_= */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
> new file mode 100644
> index 0000000000..e033672590
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
> @@ -0,0 +1,81 @@
> +/*
> + * nthw_fpga_reg_defs_cor.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_COR_
> +#define _NTHW_FPGA_REG_DEFS_COR_
> +
> +/* COR */
> +#define NTHW_MOD_COR (0x4754cf79UL)
> +#define COR_CTRL (0xa34106eaUL)
> +#define COR_CTRL_EN (0x220ce67aUL)
> +#define COR_DBG_COR_CNT (0xeb30470fUL)
> +#define COR_DBG_COR_CNT_VAL (0x5ab8a0fcUL)
> +#define COR_DBG_COR_ID (0x2b214123UL)
> +#define COR_DBG_COR_ID_VAL (0x7c6c2d68UL)
> +#define COR_DBG_COR_LO (0xc1846ceeUL)
> +#define COR_DBG_COR_LO_VAL (0x5b718dcaUL)
> +#define COR_DBG_COR_UP (0xd78cc803UL)
> +#define COR_DBG_COR_UP_VAL (0x9d18decaUL)
> +#define COR_DCEO (0xbb755e8aUL)
> +#define COR_DCEO_VAL (0x75ad94beUL)
> +#define COR_DCSO (0xa7edeb5dUL)
> +#define COR_DCSO_VAL (0xa0227538UL)
> +#define COR_DEEO (0xbff82238UL)
> +#define COR_DEEO_VAL (0x167da184UL)
> +#define COR_DEO (0xc7fcb744UL)
> +#define COR_DEO_VAL (0xf6fef8b1UL)
> +#define COR_DESO (0xa36097efUL)
> +#define COR_DESO_VAL (0xc3f24002UL)
> +#define COR_DSEO (0xa753fdfaUL)
> +#define COR_DSEO_VAL (0x12730870UL)
> +#define COR_DSO (0xdb640293UL)
> +#define COR_DSO_VAL (0x23711937UL)
> +#define COR_DSSO (0xbbcb482dUL)
> +#define COR_DSSO_VAL (0xc7fce9f6UL)
> +#define COR_RCP_CTRL (0x57a5129aUL)
> +#define COR_RCP_CTRL_ADR (0xeaa1a01aUL)
> +#define COR_RCP_CTRL_CNT (0xfaa939cbUL)
> +#define COR_RCP_DATA (0xf8749083UL)
> +#define COR_RCP_DATA_CBM1 (0x92fe79a8UL)
> +#define COR_RCP_DATA_EN (0x14a2ff31UL)
> +#define COR_RCP_DATA_END_PROT (0xd9954b3eUL)
> +#define COR_RCP_DATA_END_STATIC (0xc6775c54UL)
> +#define COR_RCP_DATA_IP_CHK (0xc1aee6c3UL)
> +#define COR_RCP_DATA_IP_DSCP (0xfeb87db5UL)
> +#define COR_RCP_DATA_IP_DST (0xe0df3629UL)
> +#define COR_RCP_DATA_IP_ECN (0x56bdb735UL)
> +#define COR_RCP_DATA_IP_FLAGS (0xef2854ecUL)
> +#define COR_RCP_DATA_IP_FLOW (0x711a8bdcUL)
> +#define COR_RCP_DATA_IP_HOP (0x8df5609UL)
> +#define COR_RCP_DATA_IP_IDENT (0xe0636de4UL)
> +#define COR_RCP_DATA_IP_NXTHDR (0xee1f8e7bUL)
> +#define COR_RCP_DATA_IP_SRC (0x637e375aUL)
> +#define COR_RCP_DATA_IP_TC (0x52c0454dUL)
> +#define COR_RCP_DATA_IP_TTL (0xa0d49bc8UL)
> +#define COR_RCP_DATA_MAX_LEN (0x4c6afabeUL)
> +#define COR_RCP_DATA_PROT_OFS1 (0x875455efUL)
> +#define COR_RCP_DATA_START_PROT (0xaf6a6510UL)
> +#define COR_RCP_DATA_START_STATIC (0x11a62e48UL)
> +#define COR_RCP_DATA_STTC_OFS1 (0x3bc9abaUL)
> +#define COR_RCP_DATA_TCP_CHK (0xd0c0496UL)
> +#define COR_RCP_DATA_TCP_DST (0x2c7dd47cUL)
> +#define COR_RCP_DATA_TCP_SEQ (0x59e620d1UL)
> +#define COR_RCP_DATA_TCP_SRC (0xafdcd50fUL)
> +#define COR_RCP_DATA_TNL (0xe14689b4UL)
> +#define COR_RCP_DATA_UDP_CHK (0xb67e3f9aUL)
> +#define COR_RCP_DATA_UDP_DST (0x970fef70UL)
> +#define COR_RCP_DATA_UDP_SRC (0x14aeee03UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_COR= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
> new file mode 100644
> index 0000000000..88b23c3de1
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
> @@ -0,0 +1,112 @@
> +/*
> + * nthw_fpga_reg_defs_cpy.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_CPY_
> +#define _NTHW_FPGA_REG_DEFS_CPY_
> +
> +/* CPY */
> +#define NTHW_MOD_CPY (0x1ddc186fUL)
> +#define CPY_PACKET_READER0_CTRL (0x59359b7UL)
> +#define CPY_PACKET_READER0_CTRL_ADR (0xc84f1475UL)
> +#define CPY_PACKET_READER0_CTRL_CNT (0xd8478da4UL)
> +#define CPY_PACKET_READER0_DATA (0xaa42dbaeUL)
> +#define CPY_PACKET_READER0_DATA_DYN (0x34037b11UL)
> +#define CPY_PACKET_READER0_DATA_OFS (0x960af6b7UL)
> +#define CPY_WRITER0_CTRL (0xe9b3268eUL)
> +#define CPY_WRITER0_CTRL_ADR (0x26f906c2UL)
> +#define CPY_WRITER0_CTRL_CNT (0x36f19f13UL)
> +#define CPY_WRITER0_DATA (0x4662a497UL)
> +#define CPY_WRITER0_DATA_DYN (0xdab569a6UL)
> +#define CPY_WRITER0_DATA_LEN (0x32d16543UL)
> +#define CPY_WRITER0_DATA_MASK_POINTER (0x64db2b2dUL)
> +#define CPY_WRITER0_DATA_OFS (0x78bce400UL)
> +#define CPY_WRITER0_DATA_READER_SELECT (0x63a38cf9UL)
> +#define CPY_WRITER0_MASK_CTRL (0xed52c5f9UL)
> +#define CPY_WRITER0_MASK_CTRL_ADR (0x3bbdf6aaUL)
> +#define CPY_WRITER0_MASK_CTRL_CNT (0x2bb56f7bUL)
> +#define CPY_WRITER0_MASK_DATA (0x428347e0UL)
> +#define CPY_WRITER0_MASK_DATA_BYTE_MASK (0xd1d0e256UL)
> +#define CPY_WRITER1_CTRL (0x22eff52bUL)
> +#define CPY_WRITER1_CTRL_ADR (0xc93b6dfcUL)
> +#define CPY_WRITER1_CTRL_CNT (0xd933f42dUL)
> +#define CPY_WRITER1_DATA (0x8d3e7732UL)
> +#define CPY_WRITER1_DATA_DYN (0x35770298UL)
> +#define CPY_WRITER1_DATA_LEN (0xdd130e7dUL)
> +#define CPY_WRITER1_DATA_MASK_POINTER (0xb339ab75UL)
> +#define CPY_WRITER1_DATA_OFS (0x977e8f3eUL)
> +#define CPY_WRITER1_DATA_READER_SELECT (0x6c4b7bfUL)
> +#define CPY_WRITER1_MASK_CTRL (0x2cdc1a39UL)
> +#define CPY_WRITER1_MASK_CTRL_ADR (0x82462d42UL)
> +#define CPY_WRITER1_MASK_CTRL_CNT (0x924eb493UL)
> +#define CPY_WRITER1_MASK_DATA (0x830d9820UL)
> +#define CPY_WRITER1_MASK_DATA_BYTE_MASK (0x4e0a61c8UL)
> +#define CPY_WRITER2_CTRL (0xa47b8785UL)
> +#define CPY_WRITER2_CTRL_ADR (0x220cd6ffUL)
> +#define CPY_WRITER2_CTRL_CNT (0x32044f2eUL)
> +#define CPY_WRITER2_DATA (0xbaa059cUL)
> +#define CPY_WRITER2_DATA_DYN (0xde40b99bUL)
> +#define CPY_WRITER2_DATA_LEN (0x3624b57eUL)
> +#define CPY_WRITER2_DATA_MASK_POINTER (0x106f2ddcUL)
> +#define CPY_WRITER2_DATA_OFS (0x7c49343dUL)
> +#define CPY_WRITER2_DATA_READER_SELECT (0xa96dfa75UL)
> +#define CPY_WRITER2_MASK_CTRL (0xb53e7c38UL)
> +#define CPY_WRITER2_MASK_CTRL_ADR (0x933b473bUL)
> +#define CPY_WRITER2_MASK_CTRL_CNT (0x8333deeaUL)
> +#define CPY_WRITER2_MASK_DATA (0x1aeffe21UL)
> +#define CPY_WRITER2_MASK_DATA_BYTE_MASK (0x3514e32bUL)
> +#define CPY_WRITER3_CTRL (0x6f275420UL)
> +#define CPY_WRITER3_CTRL_ADR (0xcdcebdc1UL)
> +#define CPY_WRITER3_CTRL_CNT (0xddc62410UL)
> +#define CPY_WRITER3_DATA (0xc0f6d639UL)
> +#define CPY_WRITER3_DATA_DYN (0x3182d2a5UL)
> +#define CPY_WRITER3_DATA_LEN (0xd9e6de40UL)
> +#define CPY_WRITER3_DATA_MASK_POINTER (0xc78dad84UL)
> +#define CPY_WRITER3_DATA_OFS (0x938b5f03UL)
> +#define CPY_WRITER3_DATA_READER_SELECT (0xcc0ac133UL)
> +#define CPY_WRITER3_MASK_CTRL (0x74b0a3f8UL)
> +#define CPY_WRITER3_MASK_CTRL_ADR (0x2ac09cd3UL)
> +#define CPY_WRITER3_MASK_CTRL_CNT (0x3ac80502UL)
> +#define CPY_WRITER3_MASK_DATA (0xdb6121e1UL)
> +#define CPY_WRITER3_MASK_DATA_BYTE_MASK (0xaace60b5UL)
> +#define CPY_WRITER4_CTRL (0x72226498UL)
> +#define CPY_WRITER4_CTRL_ADR (0x2f12a6b8UL)
> +#define CPY_WRITER4_CTRL_CNT (0x3f1a3f69UL)
> +#define CPY_WRITER4_DATA (0xddf3e681UL)
> +#define CPY_WRITER4_DATA_DYN (0xd35ec9dcUL)
> +#define CPY_WRITER4_DATA_LEN (0x3b3ac539UL)
> +#define CPY_WRITER4_DATA_MASK_POINTER (0x8db326cfUL)
> +#define CPY_WRITER4_DATA_OFS (0x7157447aUL)
> +#define CPY_WRITER4_DATA_READER_SELECT (0x2d4e67a0UL)
> +#define CPY_WRITER4_MASK_CTRL (0x5d8bb67bUL)
> +#define CPY_WRITER4_MASK_CTRL_ADR (0xb1c193c9UL)
> +#define CPY_WRITER4_MASK_CTRL_CNT (0xa1c90a18UL)
> +#define CPY_WRITER4_MASK_DATA (0xf25a3462UL)
> +#define CPY_WRITER4_MASK_DATA_BYTE_MASK (0xc329e6edUL)
> +#define CPY_WRITER5_CTRL (0xb97eb73dUL)
> +#define CPY_WRITER5_CTRL_ADR (0xc0d0cd86UL)
> +#define CPY_WRITER5_CTRL_CNT (0xd0d85457UL)
> +#define CPY_WRITER5_DATA (0x16af3524UL)
> +#define CPY_WRITER5_DATA_DYN (0x3c9ca2e2UL)
> +#define CPY_WRITER5_DATA_LEN (0xd4f8ae07UL)
> +#define CPY_WRITER5_DATA_MASK_POINTER (0x5a51a697UL)
> +#define CPY_WRITER5_DATA_OFS (0x9e952f44UL)
> +#define CPY_WRITER5_DATA_READER_SELECT (0x48295ce6UL)
> +#define CPY_WRITER5_MASK_CTRL (0x9c0569bbUL)
> +#define CPY_WRITER5_MASK_CTRL_ADR (0x83a4821UL)
> +#define CPY_WRITER5_MASK_CTRL_CNT (0x1832d1f0UL)
> +#define CPY_WRITER5_MASK_DATA (0x33d4eba2UL)
> +#define CPY_WRITER5_MASK_DATA_BYTE_MASK (0x5cf36573UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_CPY= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
> new file mode 100644
> index 0000000000..eb68ccab33
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
> @@ -0,0 +1,30 @@
> +/*
> + * nthw_fpga_reg_defs_csu.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_CSU_
> +#define _NTHW_FPGA_REG_DEFS_CSU_
> +
> +/* CSU */
> +#define NTHW_MOD_CSU (0x3f470787UL)
> +#define CSU_RCP_CTRL (0x11955fefUL)
> +#define CSU_RCP_CTRL_ADR (0x8efb3c71UL)
> +#define CSU_RCP_CTRL_CNT (0x9ef3a5a0UL)
> +#define CSU_RCP_DATA (0xbe44ddf6UL)
> +#define CSU_RCP_DATA_IL3_CMD (0xdbac8e0dUL)
> +#define CSU_RCP_DATA_IL4_CMD (0x698c521dUL)
> +#define CSU_RCP_DATA_OL3_CMD (0xb87cbb37UL)
> +#define CSU_RCP_DATA_OL4_CMD (0xa5c6727UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_CSU= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
> new file mode 100644
> index 0000000000..2ff31fdf4d
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
> @@ -0,0 +1,144 @@
> +/*
> + * nthw_fpga_reg_defs_dbs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_DBS_
> +#define _NTHW_FPGA_REG_DEFS_DBS_
> +
> +/* DBS */
> +#define NTHW_MOD_DBS (0x80b29727UL)
> +#define DBS_RX_AM_CTRL (0x7359feUL)
> +#define DBS_RX_AM_CTRL_ADR (0x4704a1UL)
> +#define DBS_RX_AM_CTRL_CNT (0x104f9d70UL)
> +#define DBS_RX_AM_DATA (0xafa2dbe7UL)
> +#define DBS_RX_AM_DATA_ENABLE (0x11658278UL)
> +#define DBS_RX_AM_DATA_GPA (0xbf307344UL)
> +#define DBS_RX_AM_DATA_HID (0x5f0669eeUL)
> +#define DBS_RX_AM_DATA_INT (0xc32857aUL)
> +#define DBS_RX_AM_DATA_PCKED (0x7d840fb4UL)
> +#define DBS_RX_CONTROL (0xb18b2866UL)
> +#define DBS_RX_CONTROL_AME (0x1f9219acUL)
> +#define DBS_RX_CONTROL_AMS (0xeb46acfdUL)
> +#define DBS_RX_CONTROL_LQ (0xe65f90b2UL)
> +#define DBS_RX_CONTROL_QE (0x3e928d3UL)
> +#define DBS_RX_CONTROL_UWE (0xb490e8dbUL)
> +#define DBS_RX_CONTROL_UWS (0x40445d8aUL)
> +#define DBS_RX_DR_CTRL (0xa0cbc617UL)
> +#define DBS_RX_DR_CTRL_ADR (0xa7b57286UL)
> +#define DBS_RX_DR_CTRL_CNT (0xb7bdeb57UL)
> +#define DBS_RX_DR_DATA (0xf1a440eUL)
> +#define DBS_RX_DR_DATA_GPA (0x18c20563UL)
> +#define DBS_RX_DR_DATA_HDR (0xb98ed4d5UL)
> +#define DBS_RX_DR_DATA_HID (0xf8f41fc9UL)
> +#define DBS_RX_DR_DATA_PCKED (0x1e27ce2aUL)
> +#define DBS_RX_DR_DATA_QS (0xffb980ddUL)
> +#define DBS_RX_IDLE (0x93c723bfUL)
> +#define DBS_RX_IDLE_BUSY (0x8e043b5bUL)
> +#define DBS_RX_IDLE_IDLE (0x9dba27ccUL)
> +#define DBS_RX_IDLE_QUEUE (0xbbddab49UL)
> +#define DBS_RX_INIT (0x899772deUL)
> +#define DBS_RX_INIT_BUSY (0x8576d90aUL)
> +#define DBS_RX_INIT_INIT (0x8c9894fcUL)
> +#define DBS_RX_INIT_QUEUE (0xa7bab8c9UL)
> +#define DBS_RX_INIT_VAL (0x7789b4d8UL)
> +#define DBS_RX_INIT_VAL_IDX (0xead0e2beUL)
> +#define DBS_RX_INIT_VAL_PTR (0x5330810eUL)
> +#define DBS_RX_PTR (0x628ce523UL)
> +#define DBS_RX_PTR_PTR (0x7f834481UL)
> +#define DBS_RX_PTR_QUEUE (0x4f3fa6d1UL)
> +#define DBS_RX_PTR_VALID (0xbcc5ec4dUL)
> +#define DBS_RX_UW_CTRL (0x31afc0deUL)
> +#define DBS_RX_UW_CTRL_ADR (0x2ee4a2c9UL)
> +#define DBS_RX_UW_CTRL_CNT (0x3eec3b18UL)
> +#define DBS_RX_UW_DATA (0x9e7e42c7UL)
> +#define DBS_RX_UW_DATA_GPA (0x9193d52cUL)
> +#define DBS_RX_UW_DATA_HID (0x71a5cf86UL)
> +#define DBS_RX_UW_DATA_INT (0x22912312UL)
> +#define DBS_RX_UW_DATA_ISTK (0xd469a7ddUL)
> +#define DBS_RX_UW_DATA_PCKED (0xef15c665UL)
> +#define DBS_RX_UW_DATA_QS (0x7d422f44UL)
> +#define DBS_RX_UW_DATA_VEC (0x55cc9b53UL)
> +#define DBS_STATUS (0xb5f35220UL)
> +#define DBS_STATUS_OK (0xcf09a30fUL)
> +#define DBS_TX_AM_CTRL (0xd6d29b9UL)
> +#define DBS_TX_AM_CTRL_ADR (0xf8854f17UL)
> +#define DBS_TX_AM_CTRL_CNT (0xe88dd6c6UL)
> +#define DBS_TX_AM_DATA (0xa2bcaba0UL)
> +#define DBS_TX_AM_DATA_ENABLE (0xb6513570UL)
> +#define DBS_TX_AM_DATA_GPA (0x47f238f2UL)
> +#define DBS_TX_AM_DATA_HID (0xa7c42258UL)
> +#define DBS_TX_AM_DATA_INT (0xf4f0ceccUL)
> +#define DBS_TX_AM_DATA_PCKED (0x2e156650UL)
> +#define DBS_TX_CONTROL (0xbc955821UL)
> +#define DBS_TX_CONTROL_AME (0xe750521aUL)
> +#define DBS_TX_CONTROL_AMS (0x1384e74bUL)
> +#define DBS_TX_CONTROL_LQ (0x46ba4f6fUL)
> +#define DBS_TX_CONTROL_QE (0xa30cf70eUL)
> +#define DBS_TX_CONTROL_UWE (0x4c52a36dUL)
> +#define DBS_TX_CONTROL_UWS (0xb886163cUL)
> +#define DBS_TX_DR_CTRL (0xadd5b650UL)
> +#define DBS_TX_DR_CTRL_ADR (0x5f773930UL)
> +#define DBS_TX_DR_CTRL_CNT (0x4f7fa0e1UL)
> +#define DBS_TX_DR_DATA (0x2043449UL)
> +#define DBS_TX_DR_DATA_GPA (0xe0004ed5UL)
> +#define DBS_TX_DR_DATA_HDR (0x414c9f63UL)
> +#define DBS_TX_DR_DATA_HID (0x36547fUL)
> +#define DBS_TX_DR_DATA_PCKED (0x4db6a7ceUL)
> +#define DBS_TX_DR_DATA_PORT (0xf306968cUL)
> +#define DBS_TX_DR_DATA_QS (0x5f5c5f00UL)
> +#define DBS_TX_IDLE (0xf0171685UL)
> +#define DBS_TX_IDLE_BUSY (0x61399ebbUL)
> +#define DBS_TX_IDLE_IDLE (0x7287822cUL)
> +#define DBS_TX_IDLE_QUEUE (0x1b387494UL)
> +#define DBS_TX_INIT (0xea4747e4UL)
> +#define DBS_TX_INIT_BUSY (0x6a4b7ceaUL)
> +#define DBS_TX_INIT_INIT (0x63a5311cUL)
> +#define DBS_TX_INIT_QUEUE (0x75f6714UL)
> +#define DBS_TX_INIT_VAL (0x9f3c7e9bUL)
> +#define DBS_TX_INIT_VAL_IDX (0xc82a364cUL)
> +#define DBS_TX_INIT_VAL_PTR (0x71ca55fcUL)
> +#define DBS_TX_PTR (0xb4d5063eUL)
> +#define DBS_TX_PTR_PTR (0x729d34c6UL)
> +#define DBS_TX_PTR_QUEUE (0xa0020331UL)
> +#define DBS_TX_PTR_VALID (0x53f849adUL)
> +#define DBS_TX_QOS_CTRL (0x3b2c3286UL)
> +#define DBS_TX_QOS_CTRL_ADR (0x666600acUL)
> +#define DBS_TX_QOS_CTRL_CNT (0x766e997dUL)
> +#define DBS_TX_QOS_DATA (0x94fdb09fUL)
> +#define DBS_TX_QOS_DATA_BS (0x2c394071UL)
> +#define DBS_TX_QOS_DATA_EN (0x7eba6fUL)
> +#define DBS_TX_QOS_DATA_IR (0xb8caa92cUL)
> +#define DBS_TX_QOS_DATA_MUL (0xd7407a67UL)
> +#define DBS_TX_QOS_RATE (0xe6e27cc5UL)
> +#define DBS_TX_QOS_RATE_DIV (0x8cd07ba3UL)
> +#define DBS_TX_QOS_RATE_MUL (0x9814e40bUL)
> +#define DBS_TX_QP_CTRL (0xd5fba432UL)
> +#define DBS_TX_QP_CTRL_ADR (0x84238184UL)
> +#define DBS_TX_QP_CTRL_CNT (0x942b1855UL)
> +#define DBS_TX_QP_DATA (0x7a2a262bUL)
> +#define DBS_TX_QP_DATA_VPORT (0xda741d67UL)
> +#define DBS_TX_UW_CTRL (0x3cb1b099UL)
> +#define DBS_TX_UW_CTRL_ADR (0xd626e97fUL)
> +#define DBS_TX_UW_CTRL_CNT (0xc62e70aeUL)
> +#define DBS_TX_UW_DATA (0x93603280UL)
> +#define DBS_TX_UW_DATA_GPA (0x69519e9aUL)
> +#define DBS_TX_UW_DATA_HID (0x89678430UL)
> +#define DBS_TX_UW_DATA_INO (0x5036a148UL)
> +#define DBS_TX_UW_DATA_INT (0xda5368a4UL)
> +#define DBS_TX_UW_DATA_ISTK (0xf693732fUL)
> +#define DBS_TX_UW_DATA_PCKED (0xbc84af81UL)
> +#define DBS_TX_UW_DATA_QS (0xdda7f099UL)
> +#define DBS_TX_UW_DATA_VEC (0xad0ed0e5UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_DBS= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
> new file mode 100644
> index 0000000000..88ed30f494
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
> @@ -0,0 +1,34 @@
> +/*
> + * nthw_fpga_reg_defs_ddp.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_DDP_
> +#define _NTHW_FPGA_REG_DEFS_DDP_
> +
> +/* DDP */
> +#define NTHW_MOD_DDP (0x4fe1611bUL)
> +#define DDP_AGING_CTRL (0x85ef88bbUL)
> +#define DDP_AGING_CTRL_AGING_RATE (0x410fda66UL)
> +#define DDP_AGING_CTRL_MAX_CNT (0x2d5ac5adUL)
> +#define DDP_CTRL (0xe64bfa02UL)
> +#define DDP_CTRL_INIT (0x8e86234cUL)
> +#define DDP_CTRL_INIT_DONE (0x14a11a6bUL)
> +#define DDP_RCP_CTRL (0x4e9ac6cUL)
> +#define DDP_RCP_CTRL_ADR (0x28c23a3cUL)
> +#define DDP_RCP_CTRL_CNT (0x38caa3edUL)
> +#define DDP_RCP_DATA (0xab382e75UL)
> +#define DDP_RCP_DATA_EN (0xa0c77e8dUL)
> +#define DDP_RCP_DATA_GROUPID (0xc71ed409UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_DDP= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
> new file mode 100644
> index 0000000000..fc181e461b
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
> @@ -0,0 +1,64 @@
> +/*
> + * nthw_fpga_reg_defs_epp.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_EPP_
> +#define _NTHW_FPGA_REG_DEFS_EPP_
> +
> +/* EPP */
> +#define NTHW_MOD_EPP (0x608ddc79UL)
> +#define EPP_QUEUE_MTU_CTRL (0xcfd3b1a4UL)
> +#define EPP_QUEUE_MTU_CTRL_ADR (0xa6da09b7UL)
> +#define EPP_QUEUE_MTU_CTRL_CNT (0xb6d29066UL)
> +#define EPP_QUEUE_MTU_DATA (0x600233bdUL)
> +#define EPP_QUEUE_MTU_DATA_MAX_MTU (0x4e1d70c4UL)
> +#define EPP_QUEUE_VPORT_CTRL (0x5daeb386UL)
> +#define EPP_QUEUE_VPORT_CTRL_ADR (0x2bf54fbfUL)
> +#define EPP_QUEUE_VPORT_CTRL_CNT (0x3bfdd66eUL)
> +#define EPP_QUEUE_VPORT_DATA (0xf27f319fUL)
> +#define EPP_QUEUE_VPORT_DATA_VPORT (0x9a1ab23eUL)
> +#define EPP_RCP_CTRL (0x8163574aUL)
> +#define EPP_RCP_CTRL_ADR (0x48b45181UL)
> +#define EPP_RCP_CTRL_CNT (0x58bcc850UL)
> +#define EPP_RCP_DATA (0x2eb2d553UL)
> +#define EPP_RCP_DATA_FIXED_18B_L2_MTU (0xf188c234UL)
> +#define EPP_RCP_DATA_QUEUE_MTU_EPP_EN (0x6ff74333UL)
> +#define EPP_RCP_DATA_QUEUE_QOS_EPP_EN (0xba9ff77eUL)
> +#define EPP_RCP_DATA_SIZE_ADJUST_TXP (0xd4e82cc4UL)
> +#define EPP_RCP_DATA_SIZE_ADJUST_VPORT (0x90128d47UL)
> +#define EPP_RCP_DATA_TX_MTU_EPP_EN (0x377c3d8bUL)
> +#define EPP_RCP_DATA_TX_QOS_EPP_EN (0xe21489c6UL)
> +#define EPP_TXP_MTU_CTRL (0x30a7bec7UL)
> +#define EPP_TXP_MTU_CTRL_ADR (0xe2444518UL)
> +#define EPP_TXP_MTU_CTRL_CNT (0xf24cdcc9UL)
> +#define EPP_TXP_MTU_DATA (0x9f763cdeUL)
> +#define EPP_TXP_MTU_DATA_MAX_MTU (0xbce62f2eUL)
> +#define EPP_TXP_QOS_CTRL (0xa833b18aUL)
> +#define EPP_TXP_QOS_CTRL_ADR (0x6b9fd6adUL)
> +#define EPP_TXP_QOS_CTRL_CNT (0x7b974f7cUL)
> +#define EPP_TXP_QOS_DATA (0x7e23393UL)
> +#define EPP_TXP_QOS_DATA_BS (0xb8857ffbUL)
> +#define EPP_TXP_QOS_DATA_EN (0x94c285e5UL)
> +#define EPP_TXP_QOS_DATA_IR (0x2c7696a6UL)
> +#define EPP_TXP_QOS_DATA_IR_FRACTION (0x972b2506UL)
> +#define EPP_VPORT_QOS_CTRL (0x24c5b00eUL)
> +#define EPP_VPORT_QOS_CTRL_ADR (0xae8e14c6UL)
> +#define EPP_VPORT_QOS_CTRL_CNT (0xbe868d17UL)
> +#define EPP_VPORT_QOS_DATA (0x8b143217UL)
> +#define EPP_VPORT_QOS_DATA_BS (0x137caa43UL)
> +#define EPP_VPORT_QOS_DATA_EN (0x3f3b505dUL)
> +#define EPP_VPORT_QOS_DATA_IR (0x878f431eUL)
> +#define EPP_VPORT_QOS_DATA_IR_FRACTION (0xa857a1dcUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_EPP= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
> new file mode 100644
> index 0000000000..5f1fa85001
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
> @@ -0,0 +1,45 @@
> +/*
> + * nthw_fpga_reg_defs_eqm.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_EQM_
> +#define _NTHW_FPGA_REG_DEFS_EQM_
> +
> +/* EQM */
> +#define NTHW_MOD_EQM (0x1a9081e1UL)
> +#define EQM_CTRL (0xa04f58b0UL)
> +#define EQM_CTRL_DBG_CRC_ERR (0xbe59fcc9UL)
> +#define EQM_CTRL_DBG_FORCE_ERR (0x1195289fUL)
> +#define EQM_CTRL_DBG_RMT_ERR (0x5fb0906fUL)
> +#define EQM_CTRL_DBG_SYNC_ERR (0xf49ef23fUL)
> +#define EQM_CTRL_ENABLE (0xe714200fUL)
> +#define EQM_CTRL_MODE (0xf3774a36UL)
> +#define EQM_CTRL_PP_RST (0x60d53774UL)
> +#define EQM_DBG (0x3edaff33UL)
> +#define EQM_DBG_FIFO_OF (0x29e8a88aUL)
> +#define EQM_DBG_LCL_EGS_QKA_OF (0x3074364UL)
> +#define EQM_DBG_LCL_EGS_QLVL_OF (0x47ec3248UL)
> +#define EQM_DBG_QBLK_CREDITS (0xcf0f2e3eUL)
> +#define EQM_STATUS (0xa64d64b3UL)
> +#define EQM_STATUS_LCL_EGS_OF_ERR (0x613933faUL)
> +#define EQM_STATUS_NIF_CRC_ERR (0x916ce965UL)
> +#define EQM_STATUS_NIF_PP_LOOP_LCK (0xffa2b3c4UL)
> +#define EQM_STATUS_NIF_RX_OF_ERR (0xa81de080UL)
> +#define EQM_STATUS_NIF_SYNC_ERR (0x2bd128e9UL)
> +#define EQM_STATUS_QM_CRC_ERR (0xd4dbf0f2UL)
> +#define EQM_STATUS_RMT_EGS_OF_ERR (0x3ce2cda4UL)
> +#define EQM_STATUS_RMT_ERR (0xc037b2cdUL)
> +#define EQM_STATUS_RMT_IGS_OF_ERR (0x26de2d2aUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_EQM= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
> new file mode 100644
> index 0000000000..26da7100b3
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
> @@ -0,0 +1,48 @@
> +/*
> + * nthw_fpga_reg_defs_fhm.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_FHM_
> +#define _NTHW_FPGA_REG_DEFS_FHM_
> +
> +/* FHM */
> +#define NTHW_MOD_FHM (0x83d696a0UL)
> +#define FHM_BACK_PRESSURE (0x7eeb6d04UL)
> +#define FHM_BACK_PRESSURE_NIF (0x60f30e0aUL)
> +#define FHM_BACK_PRESSURE_RMC (0x61c96595UL)
> +#define FHM_BACK_PRESSURE_RMC_S (0xbf76d96bUL)
> +#define FHM_CRC_ERROR_NIF (0x7b140652UL)
> +#define FHM_CRC_ERROR_NIF_CNT (0x9d790794UL)
> +#define FHM_CRC_ERROR_SDC (0xaa2ebcb3UL)
> +#define FHM_CRC_ERROR_SDC_CNT (0xef0e6634UL)
> +#define FHM_CTRL (0xdc86864eUL)
> +#define FHM_CTRL_CNT_CLR (0x6fdab4c8UL)
> +#define FHM_CTRL_ENABLE (0x3e8d895aUL)
> +#define FHM_CTRL_MODE (0xdf0cf195UL)
> +#define FHM_DEBUG_CRC (0xdaa801daUL)
> +#define FHM_DEBUG_CRC_FORCE_ERROR (0xebcc0719UL)
> +#define FHM_DEBUG_SDRAM_SIZE (0x13b07f7bUL)
> +#define FHM_DEBUG_SDRAM_SIZE_MASK (0xc9824976UL)
> +#define FHM_FILL_LEVEL (0x7244a4d9UL)
> +#define FHM_FILL_LEVEL_CELLS (0x1b463c75UL)
> +#define FHM_MAC_MICRO_DROP (0x643f5329UL)
> +#define FHM_MAC_MICRO_DROP_CNT (0xb0483cceUL)
> +#define FHM_MAX_FILL_LEVEL (0x7a5980a6UL)
> +#define FHM_MAX_FILL_LEVEL_CELLS (0x7913d45fUL)
> +#define FHM_PKT_DROP (0xa8f4d538UL)
> +#define FHM_PKT_DROP_CNT (0x789eb18UL)
> +#define FHM_PKT_DROP_BYTES (0xbba69523UL)
> +#define FHM_PKT_DROP_BYTES_CNT (0xfc38c84eUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_FHM= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
> new file mode 100644
> index 0000000000..67f9a5c1e9
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
> @@ -0,0 +1,237 @@
> +/*
> + * nthw_fpga_reg_defs_flm.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_FLM_
> +#define _NTHW_FPGA_REG_DEFS_FLM_
> +
> +/* FLM */
> +#define NTHW_MOD_FLM (0xe7ba53a4UL)
> +#define FLM_BUF_CTRL (0x2d7ba0b7UL)
> +#define FLM_BUF_CTRL_INF_AVAIL (0x55993c46UL)
> +#define FLM_BUF_CTRL_LRN_FREE (0x60b97a24UL)
> +#define FLM_BUF_CTRL_STA_AVAIL (0x44abe7c4UL)
> +#define FLM_CONTROL (0xdbb393a2UL)
> +#define FLM_CONTROL_CRCRD (0x35ba7f13UL)
> +#define FLM_CONTROL_CRCWR (0xbc193e07UL)
> +#define FLM_CONTROL_EAB (0xa09637c2UL)
> +#define FLM_CONTROL_ENABLE (0x5d80d95eUL)
> +#define FLM_CONTROL_INIT (0x69b06e85UL)
> +#define FLM_CONTROL_LDS (0xb880d8faUL)
> +#define FLM_CONTROL_LFS (0x8ab6ba78UL)
> +#define FLM_CONTROL_LIS (0xd2ea6b7UL)
> +#define FLM_CONTROL_PDS (0xadbc82eeUL)
> +#define FLM_CONTROL_PIS (0x1812fca3UL)
> +#define FLM_CONTROL_RBL (0x756afcf3UL)
> +#define FLM_CONTROL_RDS (0xae385680UL)
> +#define FLM_CONTROL_RIS (0x1b9628cdUL)
> +#define FLM_CONTROL_SPLIT_SDRAM_USAGE (0x71e7a8a4UL)
> +#define FLM_CONTROL_UDS (0xab774005UL)
> +#define FLM_CONTROL_UIS (0x1ed93e48UL)
> +#define FLM_CONTROL_WPD (0x58ec6f9UL)
> +#define FLM_INF_DATA (0xba19f6ccUL)
> +#define FLM_INF_DATA_BYTES (0x480dab67UL)
> +#define FLM_INF_DATA_BYT_A (0xb9920f4UL)
> +#define FLM_INF_DATA_BYT_B (0x9290714eUL)
> +#define FLM_INF_DATA_CAUSE (0x94e9716UL)
> +#define FLM_INF_DATA_EOR (0xd81a867eUL)
> +#define FLM_INF_DATA_ID (0x23a04258UL)
> +#define FLM_INF_DATA_PACKETS (0x33a4ab9eUL)
> +#define FLM_INF_DATA_PCK_A (0x3967b7a0UL)
> +#define FLM_INF_DATA_PCK_B (0xa06ee61aUL)
> +#define FLM_INF_DATA_RTX_A (0x900996cfUL)
> +#define FLM_INF_DATA_RTX_B (0x900c775UL)
> +#define FLM_INF_DATA_TCP_A (0xdc945df1UL)
> +#define FLM_INF_DATA_TCP_B (0x459d0c4bUL)
> +#define FLM_INF_DATA_TS (0x5f1fab83UL)
> +#define FLM_LOAD_APS (0x4e7601e5UL)
> +#define FLM_LOAD_APS_APS (0x504ad426UL)
> +#define FLM_LOAD_BIN (0xb4367a7dUL)
> +#define FLM_LOAD_BIN_BIN (0x274bb543UL)
> +#define FLM_LOAD_LPS (0x46ae92b6UL)
> +#define FLM_LOAD_LPS_LPS (0x394526b5UL)
> +#define FLM_LRN_CTRL (0x11050e66UL)
> +#define FLM_LRN_CTRL_FREE (0x4193813dUL)
> +#define FLM_LRN_DATA (0xbed48c7fUL)
> +#define FLM_LRN_DATA_ADJ (0x130ed7UL)
> +#define FLM_LRN_DATA_COLOR (0x33d0a7f2UL)
> +#define FLM_LRN_DATA_DSCP (0x5eab148eUL)
> +#define FLM_LRN_DATA_ENT (0x7fa73e2UL)
> +#define FLM_LRN_DATA_EOR (0xf782e796UL)
> +#define FLM_LRN_DATA_FILL (0x768aba23UL)
> +#define FLM_LRN_DATA_FT (0x4e9221cfUL)
> +#define FLM_LRN_DATA_FT_MBR (0x48f095acUL)
> +#define FLM_LRN_DATA_FT_MISS (0xea062e35UL)
> +#define FLM_LRN_DATA_GFI (0xafa1415dUL)
> +#define FLM_LRN_DATA_ID (0xd4bd2d64UL)
> +#define FLM_LRN_DATA_KID (0x5f92d84bUL)
> +#define FLM_LRN_DATA_MBR_ID1 (0x9931440eUL)
> +#define FLM_LRN_DATA_MBR_ID2 (0x3815b4UL)
> +#define FLM_LRN_DATA_MBR_ID3 (0x773f2522UL)
> +#define FLM_LRN_DATA_MBR_ID4 (0xe95bb081UL)
> +#define FLM_LRN_DATA_NAT_EN (0x9f4035a4UL)
> +#define FLM_LRN_DATA_NAT_IP (0xc9fa47cbUL)
> +#define FLM_LRN_DATA_NAT_PORT (0x5f8f57d0UL)
> +#define FLM_LRN_DATA_NOFI (0x3d36f27bUL)
> +#define FLM_LRN_DATA_OP (0x983d5e9fUL)
> +#define FLM_LRN_DATA_PRIO (0xf7f55b0eUL)
> +#define FLM_LRN_DATA_PROT (0x2bca3564UL)
> +#define FLM_LRN_DATA_QFI (0xb70a9e9fUL)
> +#define FLM_LRN_DATA_QW0 (0xcd0a7417UL)
> +#define FLM_LRN_DATA_QW4 (0xca67b00eUL)
> +#define FLM_LRN_DATA_RATE (0x5c250baeUL)
> +#define FLM_LRN_DATA_RQI (0xb0cfa450UL)
> +#define FLM_LRN_DATA_SCRUB_PROF (0xc3730f6bUL)
> +#define FLM_LRN_DATA_SIZE (0x740910fdUL)
> +#define FLM_LRN_DATA_STAT_PROF (0xded894eaUL)
> +#define FLM_LRN_DATA_SW8 (0xc055284bUL)
> +#define FLM_LRN_DATA_SW9 (0xb75218ddUL)
> +#define FLM_LRN_DATA_TAU (0xea8196fcUL)
> +#define FLM_LRN_DATA_TEID (0xf62ca024UL)
> +#define FLM_LRN_DATA_TTL (0xb95fd828UL)
> +#define FLM_LRN_DATA_VOL_IDX (0xabc86ffbUL)
> +#define FLM_PRIO (0x5ed7bcbeUL)
> +#define FLM_PRIO_FT0 (0x9ef34f69UL)
> +#define FLM_PRIO_FT1 (0xe9f47fffUL)
> +#define FLM_PRIO_FT2 (0x70fd2e45UL)
> +#define FLM_PRIO_FT3 (0x7fa1ed3UL)
> +#define FLM_PRIO_LIMIT0 (0xcce9cfe8UL)
> +#define FLM_PRIO_LIMIT1 (0xbbeeff7eUL)
> +#define FLM_PRIO_LIMIT2 (0x22e7aec4UL)
> +#define FLM_PRIO_LIMIT3 (0x55e09e52UL)
> +#define FLM_PST_CTRL (0x3e2b004bUL)
> +#define FLM_PST_CTRL_ADR (0xfa8565c1UL)
> +#define FLM_PST_CTRL_CNT (0xea8dfc10UL)
> +#define FLM_PST_DATA (0x91fa8252UL)
> +#define FLM_PST_DATA_BP (0x5f53d50fUL)
> +#define FLM_PST_DATA_PP (0x27a7a5dcUL)
> +#define FLM_PST_DATA_TP (0x43cb60d8UL)
> +#define FLM_RCP_CTRL (0x8041d9eeUL)
> +#define FLM_RCP_CTRL_ADR (0xb1a39fefUL)
> +#define FLM_RCP_CTRL_CNT (0xa1ab063eUL)
> +#define FLM_RCP_DATA (0x2f905bf7UL)
> +#define FLM_RCP_DATA_A (0xec41ba43UL)
> +#define FLM_RCP_DATA_AUTO_IPV4_MASK (0xa7818261UL)
> +#define FLM_RCP_DATA_B (0x7548ebf9UL)
> +#define FLM_RCP_DATA_BYT_DYN (0x28334583UL)
> +#define FLM_RCP_DATA_BYT_OFS (0x8a3ac825UL)
> +#define FLM_RCP_DATA_IPN (0x94f5d891UL)
> +#define FLM_RCP_DATA_ITF (0xfe4295a7UL)
> +#define FLM_RCP_DATA_KID (0xeca44cf9UL)
> +#define FLM_RCP_DATA_LOOKUP (0x5d0f2e84UL)
> +#define FLM_RCP_DATA_MASK (0xd97a1393UL)
> +#define FLM_RCP_DATA_OPN (0x9078a423UL)
> +#define FLM_RCP_DATA_QW0_DYN (0x28bd732dUL)
> +#define FLM_RCP_DATA_QW0_OFS (0x8ab4fe8bUL)
> +#define FLM_RCP_DATA_QW0_SEL (0x39adfaa9UL)
> +#define FLM_RCP_DATA_QW4_DYN (0xdd3dd5edUL)
> +#define FLM_RCP_DATA_QW4_OFS (0x7f34584bUL)
> +#define FLM_RCP_DATA_SW8_DYN (0x8f5229c5UL)
> +#define FLM_RCP_DATA_SW8_OFS (0x2d5ba463UL)
> +#define FLM_RCP_DATA_SW8_SEL (0x9e42a041UL)
> +#define FLM_RCP_DATA_SW9_DYN (0xb2320075UL)
> +#define FLM_RCP_DATA_SW9_OFS (0x103b8dd3UL)
> +#define FLM_RCP_DATA_TXPLM (0xbe56af35UL)
> +#define FLM_SCAN (0xee586089UL)
> +#define FLM_SCAN_I (0xe22d4ee5UL)
> +#define FLM_SCRUB (0x690c7a66UL)
> +#define FLM_SCRUB_I (0xc6a9dfe8UL)
> +#define FLM_SCRUB_CTRL (0xc647074aUL)
> +#define FLM_SCRUB_CTRL_ADR (0x3d584aa4UL)
> +#define FLM_SCRUB_CTRL_CNT (0x2d50d375UL)
> +#define FLM_SCRUB_DATA (0x69968553UL)
> +#define FLM_SCRUB_DATA_T (0x2a9c9e90UL)
> +#define FLM_STAT (0xa532c06UL)
> +#define FLM_STAT_I (0x215c23d1UL)
> +#define FLM_STATUS (0x10f57a96UL)
> +#define FLM_STATUS_CALIBDONE (0x47680c22UL)
> +#define FLM_STATUS_CRCERR (0xcd852b33UL)
> +#define FLM_STATUS_CRITICAL (0xe9e1b478UL)
> +#define FLM_STATUS_EFT_BP (0xf60fc391UL)
> +#define FLM_STATUS_EFT_EVICT_BP (0xf4dd216fUL)
> +#define FLM_STATUS_IDLE (0xd02fd0e7UL)
> +#define FLM_STATUS_INITDONE (0xdd6bdbd8UL)
> +#define FLM_STATUS_PANIC (0xf676390fUL)
> +#define FLM_STAT_AUL_DONE (0x747800bbUL)
> +#define FLM_STAT_AUL_DONE_CNT (0x6b744caeUL)
> +#define FLM_STAT_AUL_FAIL (0xe272cb59UL)
> +#define FLM_STAT_AUL_FAIL_CNT (0x697b6247UL)
> +#define FLM_STAT_AUL_IGNORE (0x49aa46f4UL)
> +#define FLM_STAT_AUL_IGNORE_CNT (0x37721e3bUL)
> +#define FLM_STAT_CSH_HIT (0xd0dca28cUL)
> +#define FLM_STAT_CSH_HIT_CNT (0xc7a41ba4UL)
> +#define FLM_STAT_CSH_MISS (0xbc219a9fUL)
> +#define FLM_STAT_CSH_MISS_CNT (0x4a66e57eUL)
> +#define FLM_STAT_CSH_UNH (0x9f625827UL)
> +#define FLM_STAT_CSH_UNH_CNT (0x79b8ac91UL)
> +#define FLM_STAT_CUC_MOVE (0x381862c0UL)
> +#define FLM_STAT_CUC_MOVE_CNT (0x868e1261UL)
> +#define FLM_STAT_CUC_START (0x617a68acUL)
> +#define FLM_STAT_CUC_START_CNT (0xbf953f79UL)
> +#define FLM_STAT_FLOWS (0x3072544fUL)
> +#define FLM_STAT_FLOWS_CNT (0x829b2631UL)
> +#define FLM_STAT_INF_DONE (0x63dff05cUL)
> +#define FLM_STAT_INF_DONE_CNT (0xf78de916UL)
> +#define FLM_STAT_INF_SKIP (0x8b84458aUL)
> +#define FLM_STAT_INF_SKIP_CNT (0xc0b9dd7dUL)
> +#define FLM_STAT_LRN_DONE (0x67128aefUL)
> +#define FLM_STAT_LRN_DONE_CNT (0xd81588feUL)
> +#define FLM_STAT_LRN_FAIL (0xf118410dUL)
> +#define FLM_STAT_LRN_FAIL_CNT (0xda1aa617UL)
> +#define FLM_STAT_LRN_IGNORE (0x9a10a7f0UL)
> +#define FLM_STAT_LRN_IGNORE_CNT (0x11c0f6a7UL)
> +#define FLM_STAT_PCK_DIS (0x55e23053UL)
> +#define FLM_STAT_PCK_DIS_CNT (0x9b13b227UL)
> +#define FLM_STAT_PCK_HIT (0xc29c5c94UL)
> +#define FLM_STAT_PCK_HIT_CNT (0xee930443UL)
> +#define FLM_STAT_PCK_MISS (0xaf5f4237UL)
> +#define FLM_STAT_PCK_MISS_CNT (0x7421a5baUL)
> +#define FLM_STAT_PCK_UNH (0x8d22a63fUL)
> +#define FLM_STAT_PCK_UNH_CNT (0x508fb376UL)
> +#define FLM_STAT_PRB_DONE (0x3bc46ef0UL)
> +#define FLM_STAT_PRB_DONE_CNT (0xcb3bc80dUL)
> +#define FLM_STAT_PRB_IGNORE (0xf02dd3d9UL)
> +#define FLM_STAT_PRB_IGNORE_CNT (0x588d1667UL)
> +#define FLM_STAT_REL_DONE (0xe192aabdUL)
> +#define FLM_STAT_REL_DONE_CNT (0xbe04b769UL)
> +#define FLM_STAT_REL_IGNORE (0x29f33e6eUL)
> +#define FLM_STAT_REL_IGNORE_CNT (0x99a6a156UL)
> +#define FLM_STAT_STA_DONE (0x500f2e87UL)
> +#define FLM_STAT_STA_DONE_CNT (0xbf276bbdUL)
> +#define FLM_STAT_TUL_DONE (0x40233ff4UL)
> +#define FLM_STAT_TUL_DONE_CNT (0xffcfd642UL)
> +#define FLM_STAT_UNL_DONE (0xe950f75eUL)
> +#define FLM_STAT_UNL_DONE_CNT (0xe9bdd9a2UL)
> +#define FLM_STAT_UNL_IGNORE (0x497abbcaUL)
> +#define FLM_STAT_UNL_IGNORE_CNT (0x1ba2b435UL)
> +#define FLM_STA_DATA (0x89c92817UL)
> +#define FLM_STA_DATA_EOR (0x90b004d5UL)
> +#define FLM_STA_DATA_ID (0x3b14a2ffUL)
> +#define FLM_STA_DATA_LDS (0xb92d607UL)
> +#define FLM_STA_DATA_LFS (0x39a4b485UL)
> +#define FLM_STA_DATA_LIS (0xbe3ca84aUL)
> +#define FLM_STA_DATA_PDS (0x1eae8c13UL)
> +#define FLM_STA_DATA_PIS (0xab00f25eUL)
> +#define FLM_STA_DATA_RDS (0x1d2a587dUL)
> +#define FLM_STA_DATA_RIS (0xa8842630UL)
> +#define FLM_STA_DATA_UDS (0x18654ef8UL)
> +#define FLM_STA_DATA_UIS (0xadcb30b5UL)
> +#define FLM_TIMEOUT (0xb729ca7bUL)
> +#define FLM_TIMEOUT_T (0x91a2b284UL)
> +#define FLM_TRSWIN (0xff97af47UL)
> +#define FLM_TRSWIN_S (0x41ed83b1UL)
> +#define FLM_TRTWIN (0x624097feUL)
> +#define FLM_TRTWIN_T (0xc28c26aaUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_FLM= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
> new file mode 100644
> index 0000000000..6ee75c571e
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
> @@ -0,0 +1,126 @@
> +/*
> + * nthw_fpga_reg_defs_gfg.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_GFG_
> +#define _NTHW_FPGA_REG_DEFS_GFG_
> +
> +/* GFG */
> +#define NTHW_MOD_GFG (0xfc423807UL)
> +#define GFG_BURSTSIZE0 (0xd62af404UL)
> +#define GFG_BURSTSIZE0_VAL (0xa2e4d17eUL)
> +#define GFG_BURSTSIZE1 (0xa12dc492UL)
> +#define GFG_BURSTSIZE1_VAL (0x9f84f8ceUL)
> +#define GFG_BURSTSIZE2 (0x38249528UL)
> +#define GFG_BURSTSIZE2_VAL (0xd824821eUL)
> +#define GFG_BURSTSIZE3 (0x4f23a5beUL)
> +#define GFG_BURSTSIZE3_VAL (0xe544abaeUL)
> +#define GFG_BURSTSIZE4 (0xd147301dUL)
> +#define GFG_BURSTSIZE4_VAL (0x576477beUL)
> +#define GFG_BURSTSIZE5 (0xa640008bUL)
> +#define GFG_BURSTSIZE5_VAL (0x6a045e0eUL)
> +#define GFG_BURSTSIZE6 (0x3f495131UL)
> +#define GFG_BURSTSIZE6_VAL (0x2da424deUL)
> +#define GFG_BURSTSIZE7 (0x484e61a7UL)
> +#define GFG_BURSTSIZE7_VAL (0x10c40d6eUL)
> +#define GFG_CTRL0 (0xc3e26c0fUL)
> +#define GFG_CTRL0_ENABLE (0xfe65937UL)
> +#define GFG_CTRL0_MODE (0x81d94c52UL)
> +#define GFG_CTRL0_PRBS_EN (0xb43e6c6UL)
> +#define GFG_CTRL0_SIZE (0xe1d32f93UL)
> +#define GFG_CTRL1 (0xb4e55c99UL)
> +#define GFG_CTRL1_ENABLE (0xc34c59a9UL)
> +#define GFG_CTRL1_MODE (0x4a859ff7UL)
> +#define GFG_CTRL1_PRBS_EN (0x1c38f285UL)
> +#define GFG_CTRL1_SIZE (0x2a8ffc36UL)
> +#define GFG_CTRL2 (0x2dec0d23UL)
> +#define GFG_CTRL2_ENABLE (0x4dc35e4aUL)
> +#define GFG_CTRL2_MODE (0xcc11ed59UL)
> +#define GFG_CTRL2_PRBS_EN (0x25b5ce40UL)
> +#define GFG_CTRL2_SIZE (0xac1b8e98UL)
> +#define GFG_CTRL3 (0x5aeb3db5UL)
> +#define GFG_CTRL3_ENABLE (0x81695ed4UL)
> +#define GFG_CTRL3_MODE (0x74d3efcUL)
> +#define GFG_CTRL3_PRBS_EN (0x32ceda03UL)
> +#define GFG_CTRL3_SIZE (0x67475d3dUL)
> +#define GFG_CTRL4 (0xc48fa816UL)
> +#define GFG_CTRL4_ENABLE (0x8bac57cdUL)
> +#define GFG_CTRL4_MODE (0x1a480e44UL)
> +#define GFG_CTRL4_PRBS_EN (0x56afb7caUL)
> +#define GFG_CTRL4_SIZE (0x7a426d85UL)
> +#define GFG_CTRL5 (0xb3889880UL)
> +#define GFG_CTRL5_ENABLE (0x47065753UL)
> +#define GFG_CTRL5_MODE (0xd114dde1UL)
> +#define GFG_CTRL5_PRBS_EN (0x41d4a389UL)
> +#define GFG_CTRL5_SIZE (0xb11ebe20UL)
> +#define GFG_CTRL6 (0x2a81c93aUL)
> +#define GFG_CTRL6_ENABLE (0xc98950b0UL)
> +#define GFG_CTRL6_MODE (0x5780af4fUL)
> +#define GFG_CTRL6_PRBS_EN (0x78599f4cUL)
> +#define GFG_CTRL6_SIZE (0x378acc8eUL)
> +#define GFG_CTRL7 (0x5d86f9acUL)
> +#define GFG_CTRL7_ENABLE (0x523502eUL)
> +#define GFG_CTRL7_MODE (0x9cdc7ceaUL)
> +#define GFG_CTRL7_PRBS_EN (0x6f228b0fUL)
> +#define GFG_CTRL7_SIZE (0xfcd61f2bUL)
> +#define GFG_RUN0 (0xb72be46cUL)
> +#define GFG_RUN0_RUN (0xa457d3c8UL)
> +#define GFG_RUN1 (0xc02cd4faUL)
> +#define GFG_RUN1_RUN (0x9937fa78UL)
> +#define GFG_RUN2 (0x59258540UL)
> +#define GFG_RUN2_RUN (0xde9780a8UL)
> +#define GFG_RUN3 (0x2e22b5d6UL)
> +#define GFG_RUN3_RUN (0xe3f7a918UL)
> +#define GFG_RUN4 (0xb0462075UL)
> +#define GFG_RUN4_RUN (0x51d77508UL)
> +#define GFG_RUN5 (0xc74110e3UL)
> +#define GFG_RUN5_RUN (0x6cb75cb8UL)
> +#define GFG_RUN6 (0x5e484159UL)
> +#define GFG_RUN6_RUN (0x2b172668UL)
> +#define GFG_RUN7 (0x294f71cfUL)
> +#define GFG_RUN7_RUN (0x16770fd8UL)
> +#define GFG_SIZEMASK0 (0x7015abe3UL)
> +#define GFG_SIZEMASK0_VAL (0xe9c7ed93UL)
> +#define GFG_SIZEMASK1 (0x7129b75UL)
> +#define GFG_SIZEMASK1_VAL (0xd4a7c423UL)
> +#define GFG_SIZEMASK2 (0x9e1bcacfUL)
> +#define GFG_SIZEMASK2_VAL (0x9307bef3UL)
> +#define GFG_SIZEMASK3 (0xe91cfa59UL)
> +#define GFG_SIZEMASK3_VAL (0xae679743UL)
> +#define GFG_SIZEMASK4 (0x77786ffaUL)
> +#define GFG_SIZEMASK4_VAL (0x1c474b53UL)
> +#define GFG_SIZEMASK5 (0x7f5f6cUL)
> +#define GFG_SIZEMASK5_VAL (0x212762e3UL)
> +#define GFG_SIZEMASK6 (0x99760ed6UL)
> +#define GFG_SIZEMASK6_VAL (0x66871833UL)
> +#define GFG_SIZEMASK7 (0xee713e40UL)
> +#define GFG_SIZEMASK7_VAL (0x5be73183UL)
> +#define GFG_STREAMID0 (0xbd4ba9aeUL)
> +#define GFG_STREAMID0_VAL (0x42d077caUL)
> +#define GFG_STREAMID1 (0xca4c9938UL)
> +#define GFG_STREAMID1_VAL (0x7fb05e7aUL)
> +#define GFG_STREAMID2 (0x5345c882UL)
> +#define GFG_STREAMID2_VAL (0x381024aaUL)
> +#define GFG_STREAMID3 (0x2442f814UL)
> +#define GFG_STREAMID3_VAL (0x5700d1aUL)
> +#define GFG_STREAMID4 (0xba266db7UL)
> +#define GFG_STREAMID4_VAL (0xb750d10aUL)
> +#define GFG_STREAMID5 (0xcd215d21UL)
> +#define GFG_STREAMID5_VAL (0x8a30f8baUL)
> +#define GFG_STREAMID6 (0x54280c9bUL)
> +#define GFG_STREAMID6_VAL (0xcd90826aUL)
> +#define GFG_STREAMID7 (0x232f3c0dUL)
> +#define GFG_STREAMID7_VAL (0xf0f0abdaUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_GFG= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
> new file mode 100644
> index 0000000000..be3c12d177
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
> @@ -0,0 +1,68 @@
> +/*
> + * nthw_fpga_reg_defs_gmf.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_GMF_
> +#define _NTHW_FPGA_REG_DEFS_GMF_
> +
> +/* GMF */
> +#define NTHW_MOD_GMF (0x68b1d15aUL)
> +#define GMF_CTRL (0x28d359b4UL)
> +#define GMF_CTRL_ENABLE (0xe41c837cUL)
> +#define GMF_CTRL_FCS_ALWAYS (0x8f36cec1UL)
> +#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (0x5b5669b0UL)
> +#define GMF_CTRL_IFG_ENABLE (0x995f1bfbUL)
> +#define GMF_CTRL_IFG_TX_NOW_ALWAYS (0xb11744c2UL)
> +#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (0xe9e4ee2aUL)
> +#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK
> (0x32dc6426UL)
> +#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (0x21dcad67UL)
> +#define GMF_CTRL_TS_INJECT_ALWAYS (0x353fa4aaUL)
> +#define GMF_CTRL_TS_INJECT_DUAL_STEP (0xc4c0195cUL)
> +#define GMF_DEBUG_LANE_MARKER (0xa51eb8a9UL)
> +#define GMF_DEBUG_LANE_MARKER_COMPENSATION (0x4f44f92aUL)
> +#define GMF_IFG_MAX_ADJUST_SLACK (0xe49f3408UL)
> +#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (0x9a2de1f7UL)
> +#define GMF_IFG_SET_CLOCK_DELTA (0x8a614d6fUL)
> +#define GMF_IFG_SET_CLOCK_DELTA_DELTA (0x1da821d6UL)
> +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (0xaa468304UL)
> +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (0x2c165992UL)
> +#define GMF_IFG_TX_NOW_ON_TS (0xd32fab5eUL)
> +#define GMF_IFG_TX_NOW_ON_TS_TS (0x612771f4UL)
> +#define GMF_SPEED (0x48bec0a1UL)
> +#define GMF_SPEED_IFG_SPEED (0x273c8281UL)
> +#define GMF_STAT (0xa49d7efUL)
> +#define GMF_STAT_CTRL_EMPTY (0x3f6e8adcUL)
> +#define GMF_STAT_DATA_CTRL_EMPTY (0xc18fc6e9UL)
> +#define GMF_STAT_SB_EMPTY (0x99314d52UL)
> +#define GMF_STAT_CTRL (0xfd31633eUL)
> +#define GMF_STAT_CTRL_FILL_LEVEL (0xe8cd56d6UL)
> +#define GMF_STAT_DATA0 (0x51838aabUL)
> +#define GMF_STAT_DATA0_EMPTY (0xcfcad9c0UL)
> +#define GMF_STAT_DATA1 (0x2684ba3dUL)
> +#define GMF_STAT_DATA1_EMPTY (0x69bdd274UL)
> +#define GMF_STAT_DATA_BUFFER (0xa6431f34UL)
> +#define GMF_STAT_DATA_BUFFER_FREE (0x3476e461UL)
> +#define GMF_STAT_DATA_BUFFER_USED (0x1f46b1UL)
> +#define GMF_STAT_MAX_DELAYED_PKT (0x3fb5c76dUL)
> +#define GMF_STAT_MAX_DELAYED_PKT_NS (0x2eb58efbUL)
> +#define GMF_STAT_NEXT_PKT (0x558ee30dUL)
> +#define GMF_STAT_NEXT_PKT_NS (0x26814d33UL)
> +#define GMF_STAT_STICKY (0x5a0f2ef7UL)
> +#define GMF_STAT_STICKY_DATA_UNDERFLOWED (0x9a3dfcb6UL)
> +#define GMF_STAT_STICKY_IFG_ADJUSTED (0xea849a5fUL)
> +#define GMF_TS_INJECT (0x66e57281UL)
> +#define GMF_TS_INJECT_OFFSET (0x8c2c9cb6UL)
> +#define GMF_TS_INJECT_POS (0xdded481UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_GMF= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
> new file mode 100644
> index 0000000000..6574263d50
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h > @@ -0,0 +1,48 @@
> +/*
> + * nthw_fpga_reg_defs_gpio_phy.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_
> +#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_
> +
> +/* GPIO_PHY */
> +#define NTHW_MOD_GPIO_PHY (0xbbe81659UL)
> +#define GPIO_PHY_CFG (0x39548432UL)
> +#define GPIO_PHY_CFG_E_PORT0_RXLOS (0x2dfe5bUL)
> +#define GPIO_PHY_CFG_E_PORT1_RXLOS (0xa65af5efUL)
> +#define GPIO_PHY_CFG_PORT0_INT_B (0xa882887cUL)
> +#define GPIO_PHY_CFG_PORT0_LPMODE (0x65df41beUL)
> +#define GPIO_PHY_CFG_PORT0_MODPRS_B (0x6aef8e94UL)
> +#define GPIO_PHY_CFG_PORT0_PLL_INTR (0xbf1f8c5dUL)
> +#define GPIO_PHY_CFG_PORT0_RESET_B (0x1ef06a6cUL)
> +#define GPIO_PHY_CFG_PORT1_INT_B (0xef583c8UL)
> +#define GPIO_PHY_CFG_PORT1_LPMODE (0xa9754120UL)
> +#define GPIO_PHY_CFG_PORT1_MODPRS_B (0x852de5aaUL)
> +#define GPIO_PHY_CFG_PORT1_PLL_INTR (0x50dde763UL)
> +#define GPIO_PHY_CFG_PORT1_RESET_B (0x98b7e2fUL)
> +#define GPIO_PHY_GPIO (0xf5c5d393UL)
> +#define GPIO_PHY_GPIO_E_PORT0_RXLOS (0xfb05c9faUL)
> +#define GPIO_PHY_GPIO_E_PORT1_RXLOS (0x5d72c24eUL)
> +#define GPIO_PHY_GPIO_PORT0_INT_B (0x6aceab27UL)
> +#define GPIO_PHY_GPIO_PORT0_LPMODE (0x99a485e1UL)
> +#define GPIO_PHY_GPIO_PORT0_MODPRS_B (0xcbc535ddUL)
> +#define GPIO_PHY_GPIO_PORT0_PLL_INTR (0x1e353714UL)
> +#define GPIO_PHY_GPIO_PORT0_RESET_B (0xe5d85dcdUL)
> +#define GPIO_PHY_GPIO_PORT1_INT_B (0xccb9a093UL)
> +#define GPIO_PHY_GPIO_PORT1_LPMODE (0x550e857fUL)
> +#define GPIO_PHY_GPIO_PORT1_MODPRS_B (0x24075ee3UL)
> +#define GPIO_PHY_GPIO_PORT1_PLL_INTR (0xf1f75c2aUL)
> +#define GPIO_PHY_GPIO_PORT1_RESET_B (0xf2a3498eUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_GPI= O_PHY_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h=
> new file mode 100644
> index 0000000000..c90a4d3209
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h=
> @@ -0,0 +1,72 @@
> +/*
> + * nthw_fpga_reg_defs_gpio_phy_ports.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_
> +#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_
> +
> +/* GPIO_PHY_PORTS */
> +#define NTHW_MOD_GPIO_PHY_PORTS (0xea12bddaUL)
> +#define GPIO_PHY_PORTS_CFG (0xe1aa4733UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT0_RXLOS (0x252ff3abUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT0_TXDISABLE (0xc9d467abUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT0_TXFAULT (0xd56642aaUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT1_RXLOS (0x8358f81fUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT1_TXDISABLE (0x85ab86bUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT1_TXFAULT (0xc21d56e9UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT2_RXLOS (0xb2b0e282UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT2_TXDISABLE (0x91b8de6aUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT2_TXFAULT (0xfb906a2cUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT3_RXLOS (0x14c7e936UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT3_TXDISABLE (0x503601aaUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT3_TXFAULT (0xeceb7e6fUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT4_RXLOS (0xd160d7b8UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT4_TXDISABLE (0x790d1429UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT4_TXFAULT (0x888a13a6UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT5_RXLOS (0x7717dc0cUL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT5_TXDISABLE (0xb883cbe9UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT5_TXFAULT (0x9ff107e5UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT6_RXLOS (0x46ffc691UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT6_TXDISABLE (0x2161ade8UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT6_TXFAULT (0xa67c3b20UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT7_RXLOS (0xe088cd25UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT7_TXDISABLE (0xe0ef7228UL)
> +#define GPIO_PHY_PORTS_CFG_E_PORT7_TXFAULT (0xb1072f63UL)
> +#define GPIO_PHY_PORTS_GPIO (0x821a1dc6UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT0_RXLOS (0x469d39ebUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXDISABLE (0xccb0d0d8UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXFAULT (0x5eae45b3UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT1_RXLOS (0xe0ea325fUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXDISABLE (0xd3e0f18UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXFAULT (0x49d551f0UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT2_RXLOS (0xd10228c2UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXDISABLE (0x94dc6919UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXFAULT (0x70586d35UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT3_RXLOS (0x77752376UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXDISABLE (0x5552b6d9UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXFAULT (0x67237976UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT4_RXLOS (0xb2d21df8UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXDISABLE (0x7c69a35aUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXFAULT (0x34214bfUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT5_RXLOS (0x14a5164cUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXDISABLE (0xbde77c9aUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXFAULT (0x143900fcUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT6_RXLOS (0x254d0cd1UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXDISABLE (0x24051a9bUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXFAULT (0x2db43c39UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT7_RXLOS (0x833a0765UL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXDISABLE (0xe58bc55bUL)
> +#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXFAULT (0x3acf287aUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_GPI= O_PHY_PORTS_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
> new file mode 100644
> index 0000000000..f271b0cd46
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h<= br> > @@ -0,0 +1,34 @@
> +/*
> + * nthw_fpga_reg_defs_gpio_sfpp.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_SFPP_
> +#define _NTHW_FPGA_REG_DEFS_GPIO_SFPP_
> +
> +/* GPIO_SFPP */
> +#define NTHW_MOD_GPIO_SFPP (0x628c8692UL)
> +#define GPIO_SFPP_CFG (0x9b959116UL)
> +#define GPIO_SFPP_CFG_ABS (0xc2942338UL)
> +#define GPIO_SFPP_CFG_RS (0x47e98ea9UL)
> +#define GPIO_SFPP_CFG_RXLOS (0x7e3cf082UL)
> +#define GPIO_SFPP_CFG_TXDISABLE (0x8bfef0a8UL)
> +#define GPIO_SFPP_CFG_TXFAULT (0x829d7e8UL)
> +#define GPIO_SFPP_GPIO (0xc964f657UL)
> +#define GPIO_SFPP_GPIO_ABS (0x246621e1UL)
> +#define GPIO_SFPP_GPIO_RS (0xd6b756e6UL)
> +#define GPIO_SFPP_GPIO_RXLOS (0xc0c8090aUL)
> +#define GPIO_SFPP_GPIO_TXDISABLE (0x450f9c11UL)
> +#define GPIO_SFPP_GPIO_TXFAULT (0x3f1231e7UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_GPI= O_SFPP_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
> new file mode 100644
> index 0000000000..19589f7900
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
> @@ -0,0 +1,48 @@
> +/*
> + * nthw_fpga_reg_defs_hfu.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_HFU_
> +#define _NTHW_FPGA_REG_DEFS_HFU_
> +
> +/* HFU */
> +#define NTHW_MOD_HFU (0x4a70e72UL)
> +#define HFU_RCP_CTRL (0xbfa69368UL)
> +#define HFU_RCP_CTRL_ADR (0xa3c53608UL)
> +#define HFU_RCP_CTRL_CNT (0xb3cdafd9UL)
> +#define HFU_RCP_DATA (0x10771171UL)
> +#define HFU_RCP_DATA_LEN_A_ADD_DYN (0xf48e5cadUL)
> +#define HFU_RCP_DATA_LEN_A_ADD_OFS (0x5687d10bUL)
> +#define HFU_RCP_DATA_LEN_A_OL4LEN (0xb06eaffcUL)
> +#define HFU_RCP_DATA_LEN_A_POS_DYN (0x8d207086UL)
> +#define HFU_RCP_DATA_LEN_A_POS_OFS (0x2f29fd20UL)
> +#define HFU_RCP_DATA_LEN_A_SUB_DYN (0x4305f5d4UL)
> +#define HFU_RCP_DATA_LEN_A_WR (0x22d5466UL)
> +#define HFU_RCP_DATA_LEN_B_ADD_DYN (0xcd036068UL)
> +#define HFU_RCP_DATA_LEN_B_ADD_OFS (0x6f0aedceUL)
> +#define HFU_RCP_DATA_LEN_B_POS_DYN (0xb4ad4c43UL)
> +#define HFU_RCP_DATA_LEN_B_POS_OFS (0x16a4c1e5UL)
> +#define HFU_RCP_DATA_LEN_B_SUB_DYN (0x7a88c911UL)
> +#define HFU_RCP_DATA_LEN_B_WR (0x1098fb88UL)
> +#define HFU_RCP_DATA_LEN_C_ADD_DYN (0xda78742bUL)
> +#define HFU_RCP_DATA_LEN_C_ADD_OFS (0x7871f98dUL)
> +#define HFU_RCP_DATA_LEN_C_POS_DYN (0xa3d65800UL)
> +#define HFU_RCP_DATA_LEN_C_POS_OFS (0x1dfd5a6UL)
> +#define HFU_RCP_DATA_LEN_C_SUB_DYN (0x6df3dd52UL)
> +#define HFU_RCP_DATA_LEN_C_WR (0xa8249cedUL)
> +#define HFU_RCP_DATA_TTL_POS_DYN (0x92a70913UL)
> +#define HFU_RCP_DATA_TTL_POS_OFS (0x30ae84b5UL)
> +#define HFU_RCP_DATA_TTL_WR (0x7a1aaf7UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_HFU= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
> new file mode 100644
> index 0000000000..4bd2ca52c9
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
> @@ -0,0 +1,79 @@
> +/*
> + * nthw_fpga_reg_defs_hif.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_HIF_
> +#define _NTHW_FPGA_REG_DEFS_HIF_
> +
> +/* HIF */
> +#define NTHW_MOD_HIF (0x7815363UL)
> +#define HIF_BUILD_TIME (0x1eaf6ab8UL)
> +#define HIF_BUILD_TIME_TIME (0xb2dfbda5UL)
> +#define HIF_CONFIG (0xb64b595cUL)
> +#define HIF_CONFIG_EXT_TAG (0x57e685bUL)
> +#define HIF_CONFIG_MAX_READ (0x7d56ce45UL)
> +#define HIF_CONFIG_MAX_TLP (0xe1c563e4UL)
> +#define HIF_CONTROL (0xedb9ed3dUL)
> +#define HIF_CONTROL_BLESSED (0x680018b7UL)
> +#define HIF_CONTROL_FSR (0x498a2097UL)
> +#define HIF_CONTROL_WRAW (0xc1a7bc42UL)
> +#define HIF_PROD_ID_EX (0xc9c9efb2UL)
> +#define HIF_PROD_ID_EX_LAYOUT (0xc6564c80UL)
> +#define HIF_PROD_ID_EX_LAYOUT_VERSION (0x9803a0e2UL)
> +#define HIF_PROD_ID_EX_RESERVED (0x1189af8aUL)
> +#define HIF_PROD_ID_EXT (0x9ba2612fUL)
> +#define HIF_PROD_ID_EXT_LAYOUT (0xe315afa1UL)
> +#define HIF_PROD_ID_EXT_LAYOUT_VERSION (0x1f7aa616UL)
> +#define HIF_PROD_ID_EXT_RESERVED (0xa4152ce8UL)
> +#define HIF_PROD_ID_LSB (0x8353363aUL)
> +#define HIF_PROD_ID_LSB_GROUP_ID (0xbb9614f7UL)
> +#define HIF_PROD_ID_LSB_REV_ID (0x5458192eUL)
> +#define HIF_PROD_ID_LSB_VER_ID (0x40abcc6fUL)
> +#define HIF_PROD_ID_MSB (0x82915c0dUL)
> +#define HIF_PROD_ID_MSB_BUILD_NO (0x1135f11bUL)
> +#define HIF_PROD_ID_MSB_PATCH_NO (0xcbf446bcUL)
> +#define HIF_PROD_ID_MSB_TYPE_ID (0xb49af41cUL)
> +#define HIF_SAMPLE_TIME (0xad0472aaUL)
> +#define HIF_SAMPLE_TIME_SAMPLE_TIME (0x56bd0a0bUL)
> +#define HIF_STATUS (0x19c1133cUL)
> +#define HIF_STATUS_RD_ERR (0x15e9f376UL)
> +#define HIF_STATUS_TAGS_IN_USE (0x9789b255UL)
> +#define HIF_STATUS_WR_ERR (0xaa8400e7UL)
> +#define HIF_STAT_CTRL (0xd9478d74UL)
> +#define HIF_STAT_CTRL_STAT_ENA (0xf26c834cUL)
> +#define HIF_STAT_CTRL_STAT_REQ (0x1546ff16UL)
> +#define HIF_STAT_REFCLK (0x656cf83fUL)
> +#define HIF_STAT_REFCLK_REFCLK250 (0xb9dd01fcUL)
> +#define HIF_STAT_RX (0x8c483f48UL)
> +#define HIF_STAT_RX_COUNTER (0xd99bc360UL)
> +#define HIF_STAT_TX (0xda1298ceUL)
> +#define HIF_STAT_TX_COUNTER (0xd485b327UL)
> +#define HIF_TEST0 (0xdab033c0UL)
> +#define HIF_TEST0_DATA (0xb7f3cba2UL)
> +#define HIF_TEST1 (0xadb70356UL)
> +#define HIF_TEST1_DATA (0x7caf1807UL)
> +#define HIF_TEST2 (0x34be52ecUL)
> +#define HIF_TEST2_DATA (0xfa3b6aa9UL)
> +#define HIF_TEST3 (0x43b9627aUL)
> +#define HIF_TEST3_DATA (0x3167b90cUL)
> +#define HIF_UUID0 (0xecba7918UL)
> +#define HIF_UUID0_UUID0 (0x84b3f35eUL)
> +#define HIF_UUID1 (0x9bbd498eUL)
> +#define HIF_UUID1_UUID1 (0x55c3c87cUL)
> +#define HIF_UUID2 (0x2b41834UL)
> +#define HIF_UUID2_UUID2 (0xfd22835bUL)
> +#define HIF_UUID3 (0x75b328a2UL)
> +#define HIF_UUID3_UUID3 (0x2c52b879UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_HIF= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
> new file mode 100644
> index 0000000000..9066e20dc9
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
> @@ -0,0 +1,49 @@
> +/*
> + * nthw_fpga_reg_defs_hsh.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_HSH_
> +#define _NTHW_FPGA_REG_DEFS_HSH_
> +
> +/* HSH */
> +#define NTHW_MOD_HSH (0x501484bfUL)
> +#define HSH_RCP_CTRL (0xb257f1b9UL)
> +#define HSH_RCP_CTRL_ADR (0x5685bfbUL)
> +#define HSH_RCP_CTRL_CNT (0x1560c22aUL)
> +#define HSH_RCP_DATA (0x1d8673a0UL)
> +#define HSH_RCP_DATA_AUTO_IPV4_MASK (0xa0d4de3bUL)
> +#define HSH_RCP_DATA_HSH_TYPE (0x14cd0865UL)
> +#define HSH_RCP_DATA_HSH_VALID (0xc89b0bd3UL)
> +#define HSH_RCP_DATA_K (0xccdb0222UL)
> +#define HSH_RCP_DATA_LOAD_DIST_TYPE (0x152a0a87UL)
> +#define HSH_RCP_DATA_MAC_PORT_MASK (0x5160b288UL)
> +#define HSH_RCP_DATA_P_MASK (0x8a555abbUL)
> +#define HSH_RCP_DATA_QW0_OFS (0x276b79cfUL)
> +#define HSH_RCP_DATA_QW0_PE (0x32014a20UL)
> +#define HSH_RCP_DATA_QW4_OFS (0xd2ebdf0fUL)
> +#define HSH_RCP_DATA_QW4_PE (0xbd63dd77UL)
> +#define HSH_RCP_DATA_SEED (0xf8fc2c1cUL)
> +#define HSH_RCP_DATA_SORT (0xed5f3d38UL)
> +#define HSH_RCP_DATA_TNL_P (0x6e56b51eUL)
> +#define HSH_RCP_DATA_TOEPLITZ (0xc1864a45UL)
> +#define HSH_RCP_DATA_W8_OFS (0x68150d02UL)
> +#define HSH_RCP_DATA_W8_PE (0x9387d583UL)
> +#define HSH_RCP_DATA_W8_SORT (0x5c67eca8UL)
> +#define HSH_RCP_DATA_W9_OFS (0x557524b2UL)
> +#define HSH_RCP_DATA_W9_P (0x808204d9UL)
> +#define HSH_RCP_DATA_W9_PE (0x2b3bb2e6UL)
> +#define HSH_RCP_DATA_W9_SORT (0x973b3f0dUL)
> +#define HSH_RCP_DATA_WORD_MASK (0x55c53a1fUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_HSH= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
> new file mode 100644
> index 0000000000..56248d5261
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
> @@ -0,0 +1,38 @@
> +/*
> + * nthw_fpga_reg_defs_i2cm.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_I2CM_
> +#define _NTHW_FPGA_REG_DEFS_I2CM_
> +
> +/* I2CM */
> +#define NTHW_MOD_I2CM (0x93bc7780UL)
> +#define I2CM_CMD_STATUS (0xcb66305bUL)
> +#define I2CM_CMD_STATUS_CMD_STATUS (0x9c9460a9UL)
> +#define I2CM_CTRL (0x7c06d3b0UL)
> +#define I2CM_CTRL_EN (0x57d0a8aaUL)
> +#define I2CM_CTRL_IEN (0x9fdc39ebUL)
> +#define I2CM_DATA (0xd3d751a9UL)
> +#define I2CM_DATA_DATA (0x2ea487faUL)
> +#define I2CM_IO_EXP (0xe8dfa320UL)
> +#define I2CM_IO_EXP_INT_B (0x85e5ff3fUL)
> +#define I2CM_IO_EXP_RST (0x207c9928UL)
> +#define I2CM_PRER_HIGH (0xf1139b49UL)
> +#define I2CM_PRER_HIGH_PRER_HIGH (0xc6ff6431UL)
> +#define I2CM_PRER_LOW (0x84f76481UL)
> +#define I2CM_PRER_LOW_PRER_LOW (0x396755aaUL)
> +#define I2CM_SELECT (0xecd56d8eUL)
> +#define I2CM_SELECT_SELECT (0xb9d992d8UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_I2C= M_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
> new file mode 100644
> index 0000000000..fcf9193b7d
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
> @@ -0,0 +1,41 @@
> +/*
> + * nthw_fpga_reg_defs_ifr.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_IFR_
> +#define _NTHW_FPGA_REG_DEFS_IFR_
> +
> +/* IFR */
> +#define NTHW_MOD_IFR (0x9b01f1e6UL)
> +#define IFR_COUNTERS_CTRL (0x92ba13e6UL)
> +#define IFR_COUNTERS_CTRL_ADR (0xecdeeda8UL)
> +#define IFR_COUNTERS_CTRL_CNT (0xfcd67479UL)
> +#define IFR_COUNTERS_DATA (0x3d6b91ffUL)
> +#define IFR_COUNTERS_DATA_DROP (0x3ee57cc0UL)
> +#define IFR_DF_BUF_CTRL (0xf60805e4UL)
> +#define IFR_DF_BUF_CTRL_AVAILABLE (0x158f09c3UL)
> +#define IFR_DF_BUF_CTRL_MTU_PROFILE (0x7cb4bc5aUL)
> +#define IFR_DF_BUF_DATA (0x59d987fdUL)
> +#define IFR_DF_BUF_DATA_FIFO_DAT (0xdbfdf650UL)
> +#define IFR_RCP_CTRL (0xc6dfc47eUL)
> +#define IFR_RCP_CTRL_ADR (0x68600d59UL)
> +#define IFR_RCP_CTRL_CNT (0x78689488UL)
> +#define IFR_RCP_DATA (0x690e4667UL)
> +#define IFR_RCP_DATA_IPV4_DF_DROP (0xbfd1ca18UL)
> +#define IFR_RCP_DATA_IPV4_EN (0xb48ee13aUL)
> +#define IFR_RCP_DATA_IPV6_DROP (0x4fbf34a2UL)
> +#define IFR_RCP_DATA_IPV6_EN (0x1e8729b1UL)
> +#define IFR_RCP_DATA_MTU (0xa436ee13UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_IFR= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
> new file mode 100644
> index 0000000000..45c7516a48
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
> @@ -0,0 +1,28 @@
> +/*
> + * nthw_fpga_reg_defs_igam.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_IGAM_
> +#define _NTHW_FPGA_REG_DEFS_IGAM_
> +
> +/* IGAM */
> +#define NTHW_MOD_IGAM (0xf3b0bfb9UL)
> +#define IGAM_BASE (0xcdbfd276UL)
> +#define IGAM_BASE_BUSY (0x2a018901UL)
> +#define IGAM_BASE_CMD (0x61c2922dUL)
> +#define IGAM_BASE_PTR (0x1076934dUL)
> +#define IGAM_DATA (0xa0f8df74UL)
> +#define IGAM_DATA_DATA (0x6544d6f2UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_IGA= M_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
> new file mode 100644
> index 0000000000..42a60cff12
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
> @@ -0,0 +1,96 @@
> +/*
> + * nthw_fpga_reg_defs_iic.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_IIC_
> +#define _NTHW_FPGA_REG_DEFS_IIC_
> +
> +/* IIC */
> +#define NTHW_MOD_IIC (0x7629cddbUL)
> +#define IIC_ADR (0x94832a56UL)
> +#define IIC_ADR_SLV_ADR (0xe34a95b4UL)
> +#define IIC_CR (0x2e99752eUL)
> +#define IIC_CR_EN (0x38b0a8b8UL)
> +#define IIC_CR_GC_EN (0x6a93c608UL)
> +#define IIC_CR_MSMS (0xd3370cefUL)
> +#define IIC_CR_RST (0x9d83289fUL)
> +#define IIC_CR_RSTA (0xb3f49376UL)
> +#define IIC_CR_TX (0x9fbd3ef9UL)
> +#define IIC_CR_TXAK (0x4daa2c41UL)
> +#define IIC_CR_TXFIFO_RESET (0x9d442d45UL)
> +#define IIC_DGIE (0xca86a888UL)
> +#define IIC_DGIE_GIE (0xda9f5b68UL)
> +#define IIC_GPO (0xdda6ed68UL)
> +#define IIC_GPO_GPO_VAL (0x6c51285eUL)
> +#define IIC_IER (0x838b4aafUL)
> +#define IIC_IER_INT0 (0x27d5f60eUL)
> +#define IIC_IER_INT1 (0x50d2c698UL)
> +#define IIC_IER_INT2 (0xc9db9722UL)
> +#define IIC_IER_INT3 (0xbedca7b4UL)
> +#define IIC_IER_INT4 (0x20b83217UL)
> +#define IIC_IER_INT5 (0x57bf0281UL)
> +#define IIC_IER_INT6 (0xceb6533bUL)
> +#define IIC_IER_INT7 (0xb9b163adUL)
> +#define IIC_ISR (0x9f13ff78UL)
> +#define IIC_ISR_INT0 (0x23db5ffaUL)
> +#define IIC_ISR_INT1 (0x54dc6f6cUL)
> +#define IIC_ISR_INT2 (0xcdd53ed6UL)
> +#define IIC_ISR_INT3 (0xbad20e40UL)
> +#define IIC_ISR_INT4 (0x24b69be3UL)
> +#define IIC_ISR_INT5 (0x53b1ab75UL)
> +#define IIC_ISR_INT6 (0xcab8facfUL)
> +#define IIC_ISR_INT7 (0xbdbfca59UL)
> +#define IIC_RX_FIFO (0x46f255afUL)
> +#define IIC_RX_FIFO_RXDATA (0x90c24f9dUL)
> +#define IIC_RX_FIFO_OCY (0xc6457d11UL)
> +#define IIC_RX_FIFO_OCY_OCY_VAL (0xee6b4716UL)
> +#define IIC_RX_FIFO_PIRQ (0x4201f0b4UL)
> +#define IIC_RX_FIFO_PIRQ_CMP_VAL (0xc5121291UL)
> +#define IIC_SOFTR (0xfb3f55bfUL)
> +#define IIC_SOFTR_RKEY (0x8c9a6beeUL)
> +#define IIC_SR (0x645b677fUL)
> +#define IIC_SR_AAS (0x66a5d25dUL)
> +#define IIC_SR_ABGC (0x4831e30UL)
> +#define IIC_SR_BB (0x1ea7e5d6UL)
> +#define IIC_SR_RXFIFO_EMPTY (0xe419563UL)
> +#define IIC_SR_RXFIFO_FULL (0x60ecb95aUL)
> +#define IIC_SR_SRW (0x1f8520c8UL)
> +#define IIC_SR_TXFIFO_EMPTY (0xe17c3083UL)
> +#define IIC_SR_TXFIFO_FULL (0x88597319UL)
> +#define IIC_TBUF (0xe32a311bUL)
> +#define IIC_TBUF_TBUF_VAL (0xd48a5ee6UL)
> +#define IIC_TEN_ADR (0xb5d88814UL)
> +#define IIC_TEN_ADR_MSB_SLV_ADR (0x1bf3647bUL)
> +#define IIC_THDDAT (0x9dc42de9UL)
> +#define IIC_THDDAT_THDDAT_VAL (0xa4fe6780UL)
> +#define IIC_THDSTA (0xdec59ae3UL)
> +#define IIC_THDSTA_THDSTA_VAL (0xc3705793UL)
> +#define IIC_THIGH (0x43194ec3UL)
> +#define IIC_THIGH_THIGH_VAL (0x320d9d1bUL)
> +#define IIC_TLOW (0x3329c638UL)
> +#define IIC_TLOW_TLOW_VAL (0x167c1ff3UL)
> +#define IIC_TSUDAT (0x6251bb80UL)
> +#define IIC_TSUDAT_TSUDAT_VAL (0x7b1fdb1dUL)
> +#define IIC_TSUSTA (0x21500c8aUL)
> +#define IIC_TSUSTA_TSUSTA_VAL (0x1c91eb0eUL)
> +#define IIC_TSUSTO (0xc6e8218dUL)
> +#define IIC_TSUSTO_TSUSTO_VAL (0x4a908671UL)
> +#define IIC_TX_FIFO (0x25226095UL)
> +#define IIC_TX_FIFO_START (0xc24fb6c4UL)
> +#define IIC_TX_FIFO_STOP (0xe7ae5f6cUL)
> +#define IIC_TX_FIFO_TXDATA (0xbe59e736UL)
> +#define IIC_TX_FIFO_OCY (0x2ef0b752UL)
> +#define IIC_TX_FIFO_OCY_OCY_VAL (0x73b74c05UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_IIC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
> new file mode 100644
> index 0000000000..a4fffb11ab
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
> @@ -0,0 +1,29 @@
> +/*
> + * nthw_fpga_reg_defs_ins.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_INS_
> +#define _NTHW_FPGA_REG_DEFS_INS_
> +
> +/* INS */
> +#define NTHW_MOD_INS (0x24df4b78UL)
> +#define INS_RCP_CTRL (0x93de4e05UL)
> +#define INS_RCP_CTRL_ADR (0x3ae620a8UL)
> +#define INS_RCP_CTRL_CNT (0x2aeeb979UL)
> +#define INS_RCP_DATA (0x3c0fcc1cUL)
> +#define INS_RCP_DATA_DYN (0xc6aa4fccUL)
> +#define INS_RCP_DATA_LEN (0x2ece4329UL)
> +#define INS_RCP_DATA_OFS (0x64a3c26aUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_INS= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
> new file mode 100644
> index 0000000000..dec8fccdbb
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
> @@ -0,0 +1,44 @@
> +/*
> + * nthw_fpga_reg_defs_ioa.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_IOA_
> +#define _NTHW_FPGA_REG_DEFS_IOA_
> +
> +/* IOA */
> +#define NTHW_MOD_IOA (0xce7d0b71UL)
> +#define IOA_RECIPE_CTRL (0x3fd57501UL)
> +#define IOA_RECIPE_CTRL_ADR (0xa12e8b86UL)
> +#define IOA_RECIPE_CTRL_CNT (0xb1261257UL)
> +#define IOA_RECIPE_DATA (0x9004f718UL)
> +#define IOA_RECIPE_DATA_QUEUE_ID (0x7b82dc9eUL)
> +#define IOA_RECIPE_DATA_QUEUE_OVERRIDE_EN (0x65468a0bUL)
> +#define IOA_RECIPE_DATA_TUNNEL_POP (0xaa73a3b3UL)
> +#define IOA_RECIPE_DATA_VLAN_DEI (0xf27320c4UL)
> +#define IOA_RECIPE_DATA_VLAN_PCP (0xdb6d242eUL)
> +#define IOA_RECIPE_DATA_VLAN_POP (0x77d86b22UL)
> +#define IOA_RECIPE_DATA_VLAN_PUSH (0x458ecac5UL)
> +#define IOA_RECIPE_DATA_VLAN_TPID_SEL (0xe1660623UL)
> +#define IOA_RECIPE_DATA_VLAN_VID (0x3fd5646bUL)
> +#define IOA_ROA_EPP_CTRL (0xab29dcacUL)
> +#define IOA_ROA_EPP_CTRL_ADR (0x87edd55dUL)
> +#define IOA_ROA_EPP_CTRL_CNT (0x97e54c8cUL)
> +#define IOA_ROA_EPP_DATA (0x4f85eb5UL)
> +#define IOA_ROA_EPP_DATA_PUSH_TUNNEL (0xc5d915c6UL)
> +#define IOA_ROA_EPP_DATA_TX_PORT (0xb127a8d0UL)
> +#define IOA_VLAN_TPID_SPECIAL (0x7812827cUL)
> +#define IOA_VLAN_TPID_SPECIAL_CUSTTPID0 (0x4333af30UL)
> +#define IOA_VLAN_TPID_SPECIAL_CUSTTPID1 (0x34349fa6UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_IOA= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
> new file mode 100644
> index 0000000000..8dc7f26d71
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
> @@ -0,0 +1,84 @@
> +/*
> + * nthw_fpga_reg_defs_ipf.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_IPF_
> +#define _NTHW_FPGA_REG_DEFS_IPF_
> +
> +/* IPF */
> +#define NTHW_MOD_IPF (0x9d43904cUL)
> +#define IPF_CTRL (0x3b50b688UL)
> +#define IPF_CTRL_ALL_UNM (0x8b16703UL)
> +#define IPF_CTRL_ALL_UNM_INNER (0x16068451UL)
> +#define IPF_CTRL_DEL_UNM (0x7d86196cUL)
> +#define IPF_CTRL_ENABLE (0xd827d73eUL)
> +#define IPF_CTRL_FST_UNM (0x6f063580UL)
> +#define IPF_CTRL_PASSIVE (0x441c1633UL)
> +#define IPF_CTRL_PERSIST (0xf52aa922UL)
> +#define IPF_DEBUG (0x4418698UL)
> +#define IPF_DEBUG_FTF_N (0x2cda6a1fUL)
> +#define IPF_DEBUG_LIMIT_N (0x8588c40eUL)
> +#define IPF_EXPIRE (0xa1d1a3e0UL)
> +#define IPF_EXPIRE_PERSIST (0x8d985989UL)
> +#define IPF_EXPIRE_T (0x37792e51UL)
> +#define IPF_FTF_DEBUG (0x2e34232dUL)
> +#define IPF_FTF_DEBUG_N (0x59f772edUL)
> +#define IPF_RCP_CTRL (0xaed9eb64UL)
> +#define IPF_RCP_CTRL_ADR (0x71e6f593UL)
> +#define IPF_RCP_CTRL_CNT (0x61ee6c42UL)
> +#define IPF_RCP_DATA (0x108697dUL)
> +#define IPF_RCP_DATA_ALL_UNM (0xe9fd243cUL)
> +#define IPF_RCP_DATA_COL_INH (0x9da0e920UL)
> +#define IPF_RCP_DATA_DEL_UNM (0x9cca5a53UL)
> +#define IPF_RCP_DATA_DISC_INH (0x8914e9a0UL)
> +#define IPF_RCP_DATA_DUP_INH (0x5f5a8cd0UL)
> +#define IPF_RCP_DATA_ENABLE (0x9afcf075UL)
> +#define IPF_RCP_DATA_FST_UNM (0x8e4a76bfUL)
> +#define IPF_RCP_DATA_GROUP_ID (0xffc993cdUL)
> +#define IPF_RCP_DATA_HASH_CENC (0x812cf8c7UL)
> +#define IPF_RCP_DATA_HSH_INH (0x1e33d9faUL)
> +#define IPF_RCP_DATA_PORT_GROUP_ID (0xd786e10bUL)
> +#define IPF_RCP_DATA_QUEUE_INH (0x6cafcc65UL)
> +#define IPF_RCP_DATA_UNMQ_HI (0xb6bb8520UL)
> +#define IPF_RCP_DATA_UNMQ_LO (0x3bb4e511UL)
> +#define IPF_RCP_DATA_UNM_FLAG_CENC (0xbb06fcddUL)
> +#define IPF_SIZE_DEBUG (0xa3c27df1UL)
> +#define IPF_SIZE_DEBUG_N (0xf8a909fbUL)
> +#define IPF_STAT_MAX1 (0xbb09703fUL)
> +#define IPF_STAT_MAX1_N (0xd361974dUL)
> +#define IPF_STAT_MAX2 (0x22002185UL)
> +#define IPF_STAT_MAX2_N (0xd1272914UL)
> +#define IPF_STAT_MAX3 (0x55071113UL)
> +#define IPF_STAT_MAX3_N (0xd0e54323UL)
> +#define IPF_STAT_MAX4 (0xcb6384b0UL)
> +#define IPF_STAT_MAX4_N (0xd5aa55a6UL)
> +#define IPF_TIMEOUT (0x9b16c106UL)
> +#define IPF_TIMEOUT_T (0x9ce14088UL)
> +#define IPF_UNMQ_CTRL (0x9c6c2c32UL)
> +#define IPF_UNMQ_CTRL_ADR (0x5a052e55UL)
> +#define IPF_UNMQ_CTRL_CNT (0x4a0db784UL)
> +#define IPF_UNMQ_DATA (0x33bdae2bUL)
> +#define IPF_UNMQ_DATA_CENC (0xe444d471UL)
> +#define IPF_UNMQ_DATA_EN (0x60b4924bUL)
> +#define IPF_UNMQ_DATA_ID (0x2cd43459UL)
> +#define IPF_UNM_FEED (0x5be1a729UL)
> +#define IPF_UNM_FEED_ADDR (0x109a9424UL)
> +#define IPF_UNM_FEED_CNT (0xab58226eUL)
> +#define IPF_UNM_FEED_FEED (0x614042baUL)
> +#define IPF_UNM_FEED_FEED_VALID (0xba08d9c3UL)
> +#define IPF_UNM_FEED_RES1 (0x82ccb216UL)
> +#define IPF_UNM_FEED_RES2 (0x1bc5e3acUL)
> +#define IPF_UNM_FEED_RES3 (0x6cc2d33aUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_IPF= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h<= br> > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
> new file mode 100644
> index 0000000000..ec9a928eda
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
> @@ -0,0 +1,125 @@
> +/*
> + * nthw_fpga_reg_defs_km.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_KM_
> +#define _NTHW_FPGA_REG_DEFS_KM_
> +
> +/* KM */
> +#define NTHW_MOD_KM (0xcfbd9dbeUL)
> +#define KM_CAM_CTRL (0x601dcc08UL)
> +#define KM_CAM_CTRL_ADR (0xee5e10b0UL)
> +#define KM_CAM_CTRL_CNT (0xfe568961UL)
> +#define KM_CAM_DATA (0xcfcc4e11UL)
> +#define KM_CAM_DATA_FT0 (0x138589ccUL)
> +#define KM_CAM_DATA_FT1 (0x6482b95aUL)
> +#define KM_CAM_DATA_FT2 (0xfd8be8e0UL)
> +#define KM_CAM_DATA_FT3 (0x8a8cd876UL)
> +#define KM_CAM_DATA_FT4 (0x14e84dd5UL)
> +#define KM_CAM_DATA_FT5 (0x63ef7d43UL)
> +#define KM_CAM_DATA_W0 (0xff7d6c5fUL)
> +#define KM_CAM_DATA_W1 (0x887a5cc9UL)
> +#define KM_CAM_DATA_W2 (0x11730d73UL)
> +#define KM_CAM_DATA_W3 (0x66743de5UL)
> +#define KM_CAM_DATA_W4 (0xf810a846UL)
> +#define KM_CAM_DATA_W5 (0x8f1798d0UL)
> +#define KM_RCP_CTRL (0xf8dbfdd1UL)
> +#define KM_RCP_CTRL_ADR (0xf3df02baUL)
> +#define KM_RCP_CTRL_CNT (0xe3d79b6bUL)
> +#define KM_RCP_DATA (0x570a7fc8UL)
> +#define KM_RCP_DATA_BANK_A (0x7fd7bd1UL)
> +#define KM_RCP_DATA_BANK_B (0x9ef42a6bUL)
> +#define KM_RCP_DATA_DUAL (0x428e6b23UL)
> +#define KM_RCP_DATA_DW0_B_DYN (0x342bde5aUL)
> +#define KM_RCP_DATA_DW0_B_OFS (0x962253fcUL)
> +#define KM_RCP_DATA_DW10_DYN (0x54eccf30UL)
> +#define KM_RCP_DATA_DW10_OFS (0xf6e54296UL)
> +#define KM_RCP_DATA_DW10_SEL_A (0x6237e887UL)
> +#define KM_RCP_DATA_DW10_SEL_B (0xfb3eb93dUL)
> +#define KM_RCP_DATA_DW2_B_DYN (0xa3b4cf73UL)
> +#define KM_RCP_DATA_DW2_B_OFS (0x1bd42d5UL)
> +#define KM_RCP_DATA_DW8_B_DYN (0x7c4903dUL)
> +#define KM_RCP_DATA_DW8_B_OFS (0xa5cd1d9bUL)
> +#define KM_RCP_DATA_DW8_DYN (0x3f6b49f0UL)
> +#define KM_RCP_DATA_DW8_OFS (0x9d62c456UL)
> +#define KM_RCP_DATA_DW8_SEL_A (0xad16725bUL)
> +#define KM_RCP_DATA_DW8_SEL_B (0x341f23e1UL)
> +#define KM_RCP_DATA_EL_A (0x4335d7dbUL)
> +#define KM_RCP_DATA_EL_B (0xda3c8661UL)
> +#define KM_RCP_DATA_FLOW_SET (0x6b56d647UL)
> +#define KM_RCP_DATA_FTM_A (0xdb75ed61UL)
> +#define KM_RCP_DATA_FTM_B (0x427cbcdbUL)
> +#define KM_RCP_DATA_INFO_A (0x2dd79cf0UL)
> +#define KM_RCP_DATA_INFO_B (0xb4decd4aUL)
> +#define KM_RCP_DATA_KEYWAY_A (0xd0e5dc89UL)
> +#define KM_RCP_DATA_KEYWAY_B (0x49ec8d33UL)
> +#define KM_RCP_DATA_KL_A (0xa3eaa0e8UL)
> +#define KM_RCP_DATA_KL_B (0x3ae3f152UL)
> +#define KM_RCP_DATA_MASK_A (0x54d84646UL)
> +#define KM_RCP_DATA_MASK_B (0xcdd117fcUL)
> +#define KM_RCP_DATA_PAIRED (0x7847653UL)
> +#define KM_RCP_DATA_QW0_B_DYN (0xd27cd964UL)
> +#define KM_RCP_DATA_QW0_B_OFS (0x707554c2UL)
> +#define KM_RCP_DATA_QW0_DYN (0x3afdb158UL)
> +#define KM_RCP_DATA_QW0_OFS (0x98f43cfeUL)
> +#define KM_RCP_DATA_QW0_SEL_A (0x78ae3b02UL)
> +#define KM_RCP_DATA_QW0_SEL_B (0xe1a76ab8UL)
> +#define KM_RCP_DATA_QW4_B_DYN (0x2633fd77UL)
> +#define KM_RCP_DATA_QW4_B_OFS (0x843a70d1UL)
> +#define KM_RCP_DATA_QW4_DYN (0xcf7d1798UL)
> +#define KM_RCP_DATA_QW4_OFS (0x6d749a3eUL)
> +#define KM_RCP_DATA_QW4_SEL_A (0x8ce11f11UL)
> +#define KM_RCP_DATA_QW4_SEL_B (0x15e84eabUL)
> +#define KM_RCP_DATA_SW4_B_DYN (0x8c5d5f1UL)
> +#define KM_RCP_DATA_SW4_B_OFS (0xaacc5857UL)
> +#define KM_RCP_DATA_SW5_B_DYN (0xaeb2de45UL)
> +#define KM_RCP_DATA_SW5_B_OFS (0xcbb53e3UL)
> +#define KM_RCP_DATA_SW8_B_DYN (0xcf65bf85UL)
> +#define KM_RCP_DATA_SW8_B_OFS (0x6d6c3223UL)
> +#define KM_RCP_DATA_SW8_DYN (0x9d12ebb0UL)
> +#define KM_RCP_DATA_SW8_OFS (0x3f1b6616UL)
> +#define KM_RCP_DATA_SW8_SEL_A (0x65b75de3UL)
> +#define KM_RCP_DATA_SW8_SEL_B (0xfcbe0c59UL)
> +#define KM_RCP_DATA_SW9_B_DYN (0x6912b431UL)
> +#define KM_RCP_DATA_SW9_B_OFS (0xcb1b3997UL)
> +#define KM_RCP_DATA_SW9_DYN (0xa072c200UL)
> +#define KM_RCP_DATA_SW9_OFS (0x27b4fa6UL)
> +#define KM_RCP_DATA_SW9_SEL_A (0xc3c05657UL)
> +#define KM_RCP_DATA_SW9_SEL_B (0x5ac907edUL)
> +#define KM_RCP_DATA_SWX_CCH (0x5821d596UL)
> +#define KM_RCP_DATA_SWX_OVS_SB (0x808773bdUL)
> +#define KM_RCP_DATA_SWX_SEL_A (0xee011106UL)
> +#define KM_RCP_DATA_SWX_SEL_B (0x770840bcUL)
> +#define KM_RCP_DATA_SYNERGY_MODE (0x35a76c4aUL)
> +#define KM_STATUS (0x2f1f9d13UL)
> +#define KM_STATUS_TCQ_RDY (0x653553c4UL)
> +#define KM_TCAM_CTRL (0x18fbc021UL)
> +#define KM_TCAM_CTRL_ADR (0x6c84a404UL)
> +#define KM_TCAM_CTRL_CNT (0x7c8c3dd5UL)
> +#define KM_TCAM_DATA (0xb72a4238UL)
> +#define KM_TCAM_DATA_T (0xa995a553UL)
> +#define KM_TCI_CTRL (0x1a6da705UL)
> +#define KM_TCI_CTRL_ADR (0xc7590d78UL)
> +#define KM_TCI_CTRL_CNT (0xd75194a9UL)
> +#define KM_TCI_DATA (0xb5bc251cUL)
> +#define KM_TCI_DATA_COLOR (0x324017ecUL)
> +#define KM_TCI_DATA_FT (0x38afba77UL)
> +#define KM_TCQ_CTRL (0xf5e827f3UL)
> +#define KM_TCQ_CTRL_ADR (0xf320cc64UL)
> +#define KM_TCQ_CTRL_CNT (0xe32855b5UL)
> +#define KM_TCQ_DATA (0x5a39a5eaUL)
> +#define KM_TCQ_DATA_BANK_MASK (0x97cf4b5aUL)
> +#define KM_TCQ_DATA_QUAL (0x4422cc93UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_KM_= */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
> new file mode 100644
> index 0000000000..6c2014e468
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
> @@ -0,0 +1,177 @@
> +/*
> + * nthw_fpga_reg_defs_mac.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_
> +#define _NTHW_FPGA_REG_DEFS_MAC_
> +
> +/* MAC */
> +#define NTHW_MOD_MAC (0xb9f9ef0fUL)
> +#define MAC_CONF_SERDES_BITFRAG (0xb22a0224UL)
> +#define MAC_CONF_SERDES_BITFRAG_BITFRAG (0x4980ae1bUL)
> +#define MAC_CONF_SERDES_DELAY (0xb106e3baUL)
> +#define MAC_CONF_SERDES_DELAY_DELAY (0x3a5a3634UL)
> +#define MAC_CONF_SERDES_REORDER (0x7b67c6e7UL)
> +#define MAC_CONF_SERDES_REORDER_REORDER (0x1b75028cUL)
> +#define MAC_FAULTY_BLK (0x221eb456UL)
> +#define MAC_FAULTY_BLK_DATA (0x96b88c4fUL)
> +#define MAC_HOST_STAT_BYTE_FILL (0xbb1fc15cUL)
> +#define MAC_HOST_STAT_BYTE_FILL_CNT (0x91d6eb19UL)
> +#define MAC_INT (0x9100902fUL)
> +#define MAC_INT_EN (0x93a8ee79UL)
> +#define MAC_INT_MAX_PACE (0x65054b07UL)
> +#define MAC_LINK_SUMMARY (0x7f2f60ceUL)
> +#define MAC_LINK_SUMMARY_ABS (0x2c3fcbfaUL)
> +#define MAC_LINK_SUMMARY_GBOX_INTERR (0x35d304b0UL)
> +#define MAC_LINK_SUMMARY_GLB_ALARMN (0x8eac9ca9UL)
> +#define MAC_LINK_SUMMARY_LH_ABS (0x24f77279UL)
> +#define MAC_LINK_SUMMARY_LH_GLB_ALARMN (0x1646a58eUL)
> +#define MAC_LINK_SUMMARY_LH_LOCAL_FAULT (0x36543c21UL)
> +#define MAC_LINK_SUMMARY_LH_REMOTE_FAULT (0x97481576UL)
> +#define MAC_LINK_SUMMARY_LH_RX_LOS (0x837691acUL)
> +#define MAC_LINK_SUMMARY_LINK_DOWN_CNT (0x1879082dUL)
> +#define MAC_LINK_SUMMARY_LL_PHY_LINK_STATE (0x64cc82a2UL)
> +#define MAC_LINK_SUMMARY_LOCAL_FAULT (0x93c66373UL)
> +#define MAC_LINK_SUMMARY_NT_PHY_LINK_STATE (0x25c4b3b4UL)
> +#define MAC_LINK_SUMMARY_REMOTE_FAULT (0x1288b7f1UL)
> +#define MAC_LINK_SUMMARY_RX_LOS (0xc0bd6b0eUL)
> +#define MAC_MAC_STAT_BYTE (0x7c8bb288UL)
> +#define MAC_MAC_STAT_BYTE_CNT (0x7e7a0bd3UL)
> +#define MAC_MAC_STAT_CRC (0x39d27996UL)
> +#define MAC_MAC_STAT_CRC_CNT (0x3e8901dcUL)
> +#define MAC_MAC_STAT_CV (0xd9cde09fUL)
> +#define MAC_MAC_STAT_CV_CNT (0xdc1321cfUL)
> +#define MAC_MAC_STAT_FRAME (0xc71e1060UL)
> +#define MAC_MAC_STAT_FRAME_CNT (0xe7c8ff51UL)
> +#define MAC_MAC_STAT_MICRO_DROP (0xe4d098cbUL)
> +#define MAC_MAC_STAT_MICRO_DROP_CNT (0x659aa0dfUL)
> +#define MAC_MAC_STAT_RATE_DROP (0x403c4fbbUL)
> +#define MAC_MAC_STAT_RATE_DROP_CNT (0xa513f8e7UL)
> +#define MAC_MAC_STAT_TRUNC (0x45f29d8UL)
> +#define MAC_MAC_STAT_TRUNC_CNT (0xffbbaa75UL)
> +#define MAC_MDS_CEN_VAL (0xa9a494fdUL)
> +#define MAC_MDS_CEN_VAL_VAL (0x74e79a1bUL)
> +#define MAC_MDS_CONF (0xd4f79721UL)
> +#define MAC_MDS_CONF_CENTER_REC_ENA (0x61ec9442UL)
> +#define MAC_MDS_CONF_CLR_STAT (0xdc56da95UL)
> +#define MAC_MDS_CONF_ENA_TS_MOD (0xf071678dUL)
> +#define MAC_MDS_CONF_REC_ENA (0x9c1d77c5UL)
> +#define MAC_MDS_CONF_TIME_MODE (0x4f2a4dcaUL)
> +#define MAC_MDS_DATA (0x6df7edeaUL)
> +#define MAC_MDS_DATA_DATA (0x24589197UL)
> +#define MAC_MDS_FRAMES (0x40ca5335UL)
> +#define MAC_MDS_FRAMES_CNT (0xff4f25c0UL)
> +#define MAC_MDS_MAX (0x230406d6UL)
> +#define MAC_MDS_MAX_MAX (0x54809081UL)
> +#define MAC_MDS_MIN (0x1f09398fUL)
> +#define MAC_MDS_MIN_MIN (0x6b7e4f97UL)
> +#define MAC_MDS_STAT (0xe0bce1a8UL)
> +#define MAC_MDS_STAT_CLR_BUSY (0x4a5ac60dUL)
> +#define MAC_MDS_STAT_HIT_MAX (0xe5a34512UL)
> +#define MAC_MDS_STAT_HIT_MIN (0xd9ae7a4bUL)
> +#define MAC_MDS_VAL_REC (0x8ec946abUL)
> +#define MAC_MDS_VAL_REC_VALUE (0xe4e373beUL)
> +#define MAC_MDS_VAL_REC_FRAME (0x8c12c923UL)
> +#define MAC_MDS_VAL_REC_FRAME_VALUE (0xd76728beUL)
> +#define MAC_NT_PORT_CTRL (0x8cd09e7cUL)
> +#define MAC_NT_PORT_CTRL_LED_MODE (0x8486e464UL)
> +#define MAC_RAM_MDS_ADDR (0xad17b5f2UL)
> +#define MAC_RAM_MDS_ADDR_ADR (0x439fe32bUL)
> +#define MAC_RAM_MDS_ADDR_CLR_RAM (0x824a2a22UL)
> +#define MAC_RAM_MDS_ADDR_RD_DONE (0x4d858fc4UL)
> +#define MAC_RAM_MDS_ADDR_RD_ENA (0xb0e2aae4UL)
> +#define MAC_RAW_ADDR (0xfeacc28aUL)
> +#define MAC_RAW_ADDR_ADR (0x49f962b0UL)
> +#define MAC_RAW_ADDR_RDENA (0x57a8bee0UL)
> +#define MAC_RAW_ADDR_RD_DONE (0x1441bde9UL)
> +#define MAC_RAW_CTRL (0xae1421c5UL)
> +#define MAC_RAW_CTRL_OVERWR_LM (0x4b06da1cUL)
> +#define MAC_RAW_CTRL_RESTART (0xc0d2b66fUL)
> +#define MAC_RAW_CTRL_TG_ACT (0x40471be4UL)
> +#define MAC_RAW_CTRL_TG_ENA (0x9f3d299eUL)
> +#define MAC_RAW_CTRL_WRAP (0x11e8b136UL)
> +#define MAC_RAW_DATA (0x1c5a3dcUL)
> +#define MAC_RAW_DATA_RAW_DATA (0xcb2757bcUL)
> +#define MAC_RAW_REPETITION (0xbbec07c6UL)
> +#define MAC_RAW_REPETITION_CNT (0xe998b255UL)
> +#define MAC_RX_CONFIG (0x69191a34UL)
> +#define MAC_RX_CONFIG_DESCRAMB (0xcd5890eUL)
> +#define MAC_RX_CONFIG_HOST_CLR_CNT (0xb1ea5438UL)
> +#define MAC_RX_CONFIG_MAC_CLR_CNT (0x5181c6edUL)
> +#define MAC_RX_CONFIG_MIN_RX_FRAME (0xcf749efeUL)
> +#define MAC_RX_CONFIG_NT_DEBOUNCE_LATENCY (0x39a4b7f3UL)
> +#define MAC_RX_CONFIG_NT_FORCE_LINK_DOWN (0x361dbc83UL)
> +#define MAC_RX_CONFIG_NT_LINKUP_LATENCY (0xe25cf44aUL)
> +#define MAC_RX_CONFIG_RST_BLK_ERR (0x476bf210UL)
> +#define MAC_RX_CONFIG_RX_MAC_EN (0xbcb6ab91UL)
> +#define MAC_RX_CONFIG_TS_EOP (0xc648dd62UL)
> +#define MAC_RX_CONFIG_TXRX_LOOP (0x66156fdfUL)
> +#define MAC_RX_CONFIG2 (0x3b0853a2UL)
> +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_INT (0x15c7f251UL)
> +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (0xadc9cd69UL)
> +#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_RST (0xfad8d2dcUL)
> +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_INT (0x76a6fa30UL)
> +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_LINK (0x971ffdafUL)
> +#define MAC_RX_CONFIG2_NT_RXLOS_MASK_RST (0x99b9dabdUL)
> +#define MAC_RX_STATUS (0xc6935054UL)
> +#define MAC_RX_STATUS_CORE_MODE (0xb8548429UL)
> +#define MAC_RX_STATUS_LOCAL_FAULT (0x4d495f63UL)
> +#define MAC_RX_STATUS_REMOTE_FAULT (0xfe128a9UL)
> +#define MAC_RX_STATUS_RXTX_OVERFLOW (0xc63536a2UL)
> +#define MAC_RX_STATUS_VERSION (0x9bf530b7UL)
> +#define MAC_TFG_ADDR (0xfeb2f718UL)
> +#define MAC_TFG_ADDR_ADR (0xa851533bUL)
> +#define MAC_TFG_ADDR_RDENA (0xde011ef2UL)
> +#define MAC_TFG_ADDR_RD_DONE (0xba63e77bUL)
> +#define MAC_TFG_CTRL (0xae0a1457UL)
> +#define MAC_TFG_CTRL_ID_ENA (0x94e59ae3UL)
> +#define MAC_TFG_CTRL_ID_POS (0x64aabb71UL)
> +#define MAC_TFG_CTRL_RESTART (0x6ef0ecfdUL)
> +#define MAC_TFG_CTRL_TG_ACT (0xb377c30cUL)
> +#define MAC_TFG_CTRL_TG_ENA (0x6c0df176UL)
> +#define MAC_TFG_CTRL_TIME_MODE (0xc7d30a61UL)
> +#define MAC_TFG_CTRL_WRAP (0x6b6343afUL)
> +#define MAC_TFG_DATA (0x1db964eUL)
> +#define MAC_TFG_DATA_GAP (0x1eb74eaUL)
> +#define MAC_TFG_DATA_ID (0xd1864536UL)
> +#define MAC_TFG_DATA_LENGTH (0xdb3bb77fUL)
> +#define MAC_TFG_FRAME_HDR (0xd36f87edUL)
> +#define MAC_TFG_FRAME_HDR_HDR (0x33800156UL)
> +#define MAC_TFG_REPETITION (0x3245a7d4UL)
> +#define MAC_TFG_REPETITION_CNT (0x21514c05UL)
> +#define MAC_TX_CONFIG (0x1a0363beUL)
> +#define MAC_TX_CONFIG_CLR_STICKY (0x170875aUL)
> +#define MAC_TX_CONFIG_CRC_ERR_INS (0xf0ac9462UL)
> +#define MAC_TX_CONFIG_HOST_TX_ENA (0x5593f749UL)
> +#define MAC_TX_CONFIG_MAC_LOOP (0x34b86cc7UL)
> +#define MAC_TX_CONFIG_PCS_BIP_ERR (0xed089516UL)
> +#define MAC_TX_CONFIG_PCS_DIS_BIP_INS (0xce7f1bc7UL)
> +#define MAC_TX_CONFIG_PCS_IDLE (0x3a34f374UL)
> +#define MAC_TX_CONFIG_PCS_IDLE_DIS (0x3899c1f1UL)
> +#define MAC_TX_CONFIG_PCS_LOCAL_FAULT (0xdfeb9ecdUL)
> +#define MAC_TX_CONFIG_PCS_LOCAL_FAULT_DIS (0xce2c57b5UL)
> +#define MAC_TX_CONFIG_PCS_REMOTE_FAULT (0x3e1d0487UL)
> +#define MAC_TX_CONFIG_PCS_REMOTE_FAULT_DIS (0x5fea461fUL)
> +#define MAC_TX_CONFIG_PCS_SCRAMB_ENA (0xaa28e162UL)
> +#define MAC_TX_CONFIG_PCS_SCRAMB_ERR (0xc8e1fde1UL)
> +#define MAC_TX_CONFIG_TIME_OFFSET_TX (0x78fff470UL)
> +#define MAC_TX_CONFIG_TS_EOP (0x95d9b486UL)
> +#define MAC_TX_STATUS (0xb58929deUL)
> +#define MAC_TX_STATUS_PCS_ERR (0x1c890ea7UL)
> +#define MAC_TX_STATUS_TX_MAC_ST (0x5ac922d9UL)
> +#define MAC_TX_STATUS_UNDER_FLOW (0x49718623UL)
> +#define MAC_UPD_RX_COUNTERS (0x82256265UL)
> +#define MAC_UPD_RX_COUNTERS_TRIGGER (0x29f90550UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
> new file mode 100644
> index 0000000000..3ad544798c
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h > @@ -0,0 +1,298 @@
> +/*
> + * nthw_fpga_reg_defs_mac_pcs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_
> +#define _NTHW_FPGA_REG_DEFS_MAC_PCS_
> +
> +/* MAC_PCS */
> +#define NTHW_MOD_MAC_PCS (0x7abe24c7UL)
> +#define MAC_PCS_BAD_CODE (0x10d9fce5UL)
> +#define MAC_PCS_BAD_CODE_CODE_ERR (0xb08ecc3fUL)
> +#define MAC_PCS_BIP_ERR (0x7aead929UL)
> +#define MAC_PCS_BIP_ERR_BIP_ERR (0x7e06ff82UL)
> +#define MAC_PCS_BLOCK_LOCK (0xa44a8a0bUL)
> +#define MAC_PCS_BLOCK_LOCK_LOCK (0x6adfd96bUL)
> +#define MAC_PCS_BLOCK_LOCK_CHG (0xf0603b66UL)
> +#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (0x9ef4519dUL)
> +#define MAC_PCS_CLKRX_FRQ (0x999882b5UL)
> +#define MAC_PCS_CLKRX_FRQ_RX_FREQ (0x8b935059UL)
> +#define MAC_PCS_CLKTX_FRQ (0x4fc161a8UL)
> +#define MAC_PCS_CLKTX_FRQ_TX_FREQ (0x10812ed5UL)
> +#define MAC_PCS_DEBOUNCE_CTRL (0x37a3bb69UL)
> +#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY
> (0xf5845748UL)
> +#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN
> (0x1a8a9237UL)
> +#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (0xaceccbf4UL)
> +#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (0x7f66469eUL)
> +#define MAC_PCS_DRP_CONFIG (0x1281f4d8UL)
> +#define MAC_PCS_DRP_CONFIG_DRP_ADR (0x398caa76UL)
> +#define MAC_PCS_DRP_CONFIG_DRP_DI (0x83b54c6fUL)
> +#define MAC_PCS_DRP_CONFIG_DRP_EN (0x4cae88dUL)
> +#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (0xc24d1deaUL)
> +#define MAC_PCS_DRP_CONFIG_DRP_WREN (0x926388aeUL)
> +#define MAC_PCS_DRP_CTRL (0x6df0725eUL)
> +#define MAC_PCS_DRP_CTRL_ADR (0x5a9962c8UL)
> +#define MAC_PCS_DRP_CTRL_DATA (0x2173d834UL)
> +#define MAC_PCS_DRP_CTRL_DBG_BUSY (0x26dd3668UL)
> +#define MAC_PCS_DRP_CTRL_DONE (0x9cadcbfcUL)
> +#define MAC_PCS_DRP_CTRL_MOD_ADR (0x4352354dUL)
> +#define MAC_PCS_DRP_CTRL_WREN (0xbed903edUL)
> +#define MAC_PCS_DRP_DATA (0xc221f047UL)
> +#define MAC_PCS_DRP_DATA_DRP_DO (0xbeb48b96UL)
> +#define MAC_PCS_DRP_DATA_DRP_RDY (0x2238822eUL)
> +#define MAC_PCS_FEC_CTRL (0x8eea756UL)
> +#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (0xd0c0525eUL)
> +#define MAC_PCS_FEC_CW_CNT (0x59e0c4deUL)
> +#define MAC_PCS_FEC_CW_CNT_CW_CNT (0xd0b8ee0UL)
> +#define MAC_PCS_FEC_ERR_CNT_0 (0xee88619cUL)
> +#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (0x4fdf126bUL)
> +#define MAC_PCS_FEC_ERR_CNT_1 (0x998f510aUL)
> +#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (0x58a40628UL)
> +#define MAC_PCS_FEC_ERR_CNT_2 (0x8600b0UL)
> +#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (0x61293aedUL)
> +#define MAC_PCS_FEC_ERR_CNT_3 (0x77813026UL)
> +#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (0x76522eaeUL)
> +#define MAC_PCS_FEC_LANE_DLY_0 (0xc18f945eUL)
> +#define MAC_PCS_FEC_LANE_DLY_0_DLY (0xd9f1d54bUL)
> +#define MAC_PCS_FEC_LANE_DLY_1 (0xb688a4c8UL)
> +#define MAC_PCS_FEC_LANE_DLY_1_DLY (0xe491fcfbUL)
> +#define MAC_PCS_FEC_LANE_DLY_2 (0x2f81f572UL)
> +#define MAC_PCS_FEC_LANE_DLY_2_DLY (0xa331862bUL)
> +#define MAC_PCS_FEC_LANE_DLY_3 (0x5886c5e4UL)
> +#define MAC_PCS_FEC_LANE_DLY_3_DLY (0x9e51af9bUL)
> +#define MAC_PCS_FEC_LANE_MAP (0x21d4bd54UL)
> +#define MAC_PCS_FEC_LANE_MAP_MAPPING (0x87d12932UL)
> +#define MAC_PCS_FEC_STAT (0x2a74290dUL)
> +#define MAC_PCS_FEC_STAT_AM_LOCK (0x289b2822UL)
> +#define MAC_PCS_FEC_STAT_AM_LOCK_0 (0xc824a589UL)
> +#define MAC_PCS_FEC_STAT_AM_LOCK_1 (0xbf23951fUL)
> +#define MAC_PCS_FEC_STAT_AM_LOCK_2 (0x262ac4a5UL)
> +#define MAC_PCS_FEC_STAT_AM_LOCK_3 (0x512df433UL)
> +#define MAC_PCS_FEC_STAT_BLOCK_LOCK (0x6a7d0f5fUL)
> +#define MAC_PCS_FEC_STAT_BYPASS (0x2e754185UL)
> +#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (0xfd302594UL)
> +#define MAC_PCS_FEC_STAT_HI_SER (0xc3501768UL)
> +#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (0xa8193db8UL)
> +#define MAC_PCS_FEC_STAT_VALID (0x90dd6fe1UL)
> +#define MAC_PCS_FEC_UCW_CNT (0xd1354660UL)
> +#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (0xf90f900UL)
> +#define MAC_PCS_FRAMING_ERR (0x73b6341dUL)
> +#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (0xd4bfdbf4UL)
> +#define MAC_PCS_GTY_CTL (0x325263edUL)
> +#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (0x423e0e64UL)
> +#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (0x35393ef2UL)
> +#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (0xac306f48UL)
> +#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (0xdb375fdeUL)
> +#define MAC_PCS_GTY_CTL_RX (0x1f131df2UL)
> +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (0x3c2aeb81UL)
> +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (0x4b2ddb17UL)
> +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (0xd2248aadUL)
> +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (0xa523ba3bUL)
> +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (0x78b8f7dbUL)
> +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (0xfbfc74dUL)
> +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (0x96b696f7UL)
> +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (0xe1b1a661UL)
> +#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (0xce64b22bUL)
> +#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (0xb96382bdUL)
> +#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (0x206ad307UL)
> +#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (0x576de391UL)
> +#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (0x80681033UL)
> +#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (0xf76f20a5UL)
> +#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (0x6e66711fUL)
> +#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (0x19614189UL)
> +#define MAC_PCS_GTY_CTL_RX_RATE_0 (0x6c6c737dUL)
> +#define MAC_PCS_GTY_CTL_RX_RATE_1 (0x1b6b43ebUL)
> +#define MAC_PCS_GTY_CTL_RX_RATE_2 (0x82621251UL)
> +#define MAC_PCS_GTY_CTL_RX_RATE_3 (0xf56522c7UL)
> +#define MAC_PCS_GTY_CTL_TX (0x4949ba74UL)
> +#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (0xd2423364UL)
> +#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (0xa54503f2UL)
> +#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (0x3c4c5248UL)
> +#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (0x4b4b62deUL)
> +#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (0x208dcfeeUL)
> +#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (0x578aff78UL)
> +#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (0xce83aec2UL)
> +#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (0xb9849e54UL)
> +#define MAC_PCS_GTY_DIFF_CTL (0x8756c12fUL)
> +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (0xf08ceefdUL)
> +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (0x878bde6bUL)
> +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (0x1e828fd1UL)
> +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (0x6985bf47UL)
> +#define MAC_PCS_GTY_LOOP (0x4dd7ddbUL)
> +#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (0xd55e5438UL)
> +#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (0xa25964aeUL)
> +#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (0x3b503514UL)
> +#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (0x4c570582UL)
> +#define MAC_PCS_GTY_POST_CURSOR (0x4699c607UL)
> +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (0x23ff66e9UL)
> +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (0x54f8567fUL)
> +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (0xcdf107c5UL)
> +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (0xbaf63753UL)
> +#define MAC_PCS_GTY_PRBS_SEL (0x6610ec4eUL)
> +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (0xb535fd56UL)
> +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (0xc232cdc0UL)
> +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (0x5b3b9c7aUL)
> +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (0x2c3cacecUL)
> +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (0x15d0228bUL)
> +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (0x62d7121dUL)
> +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (0xfbde43a7UL)
> +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (0x8cd97331UL)
> +#define MAC_PCS_GTY_PRE_CURSOR (0x989e0463UL)
> +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (0x264242bdUL)
> +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (0x5145722bUL)
> +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (0xc84c2391UL)
> +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (0xbf4b1307UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT (0xf37901e8UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (0xab8b9404UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (0xdc8ca492UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (0x4585f528UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (0x3282c5beUL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0
> (0x476782c4UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1
> (0x3060b252UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2
> (0xa969e3e8UL)
> +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3
> (0xde6ed37eUL)
> +#define MAC_PCS_GTY_SCAN_CTL (0x782ddd2aUL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (0xc2791c66UL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (0xb57e2cf0UL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (0x2c777d4aUL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (0x5b704ddcUL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (0xebe5938aUL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (0x9ce2a31cUL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (0x5ebf2a6UL)
> +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (0x72ecc230UL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (0x3243ecaeUL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (0x4544dc38UL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (0xdc4d8d82UL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (0xab4abd14UL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (0xf77381daUL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (0x8074b14cUL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (0x197de0f6UL)
> +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (0x6e7ad060UL)
> +#define MAC_PCS_GTY_SCAN_STAT (0x8070b7b9UL)
> +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (0xe5ddd3f9UL)
> +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (0x92dae36fUL)
> +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (0xbd3b2d5UL)
> +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (0x7cd48243UL)
> +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (0xb0217badUL)
> +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (0xc7264b3bUL)
> +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (0x5e2f1a81UL)
> +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (0x29282a17UL)
> +#define MAC_PCS_GTY_STAT (0x853a9f14UL)
> +#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (0x71cda8d6UL)
> +#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (0x6ca9840UL)
> +#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (0x9fc3c9faUL)
> +#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (0xe8c4f96cUL)
> +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (0xf766f49eUL)
> +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (0x8061c408UL)
> +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (0x196895b2UL)
> +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (0x6e6fa524UL)
> +#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (0xd128770bUL)
> +#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (0xa62f479dUL)
> +#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (0x3f261627UL)
> +#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (0x482126b1UL)
> +#define MAC_PCS_LANE_ALIGNER_FILL (0x7f7c92b4UL)
> +#define MAC_PCS_LANE_ALIGNER_FILL_FILL (0x5d03a992UL)
> +#define MAC_PCS_LINK_SUMMARY (0x7506c2cfUL)
> +#define MAC_PCS_LINK_SUMMARY_ABS (0xeaec5364UL)
> +#define MAC_PCS_LINK_SUMMARY_LH_ABS (0x75386439UL)
> +#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (0xfe0a1d22UL)
> +#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (0xe891aedUL)
> +#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (0x91098b1fUL)
> +#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (0x66c65523UL)
> +#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (0x87148e11UL)
> +#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (0x3d95c18UL)
> +#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (0x27ce6435UL)
> +#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (0xb1206568UL)
> +#define MAC_PCS_LINK_SUMMARY_RESERVED (0x254bc0e3UL)
> +#define MAC_PCS_MAC_PCS_CONFIG (0x1534e5c0UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (0xe964d0f5UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (0x3301c934UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (0xf01103aUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (0x65a6baccUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (0xf932af1bUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (0x1d11ab6UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (0x401bb0beUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (0x25816398UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (0x8d13708fUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (0xbcff1ba5UL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (0xc4dd154eUL)
> +#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (0xdbc87be9UL)
> +#define MAC_PCS_MAX_PKT_LEN (0x396b0d64UL)
> +#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (0x6d95b01fUL)
> +#define MAC_PCS_MF_ERR (0xb0be669dUL)
> +#define MAC_PCS_MF_ERR_MF_ERR (0x6c7b7561UL)
> +#define MAC_PCS_MF_LEN_ERR (0x559f33efUL)
> +#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (0x196e21f6UL)
> +#define MAC_PCS_MF_REPEAT_ERR (0xc7dedbb3UL)
> +#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (0xb5be34c7UL)
> +#define MAC_PCS_PHYMAC_MISC (0x4d213de4UL)
> +#define MAC_PCS_PHYMAC_MISC_TS_EOP (0xc9232087UL)
> +#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (0x761f1c74UL)
> +#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (0xb50087a5UL)
> +#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (0xbe5ce3b1UL)
> +#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (0x106d1efUL)
> +#define MAC_PCS_PHY_STAT (0x533a519cUL)
> +#define MAC_PCS_PHY_STAT_ALARM (0x57360efaUL)
> +#define MAC_PCS_PHY_STAT_MOD_PRS (0x5d9d2135UL)
> +#define MAC_PCS_PHY_STAT_RX_LOS (0xf9354fecUL)
> +#define MAC_PCS_STAT_PCS_RX (0xb11d1a0cUL)
> +#define MAC_PCS_STAT_PCS_RX_ALIGNED (0xc04d3946UL)
> +#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (0x82e5aacbUL)
> +#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (0xe2ebace5UL)
> +#define MAC_PCS_STAT_PCS_RX_HI_BER (0x44ed301UL)
> +#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (0xd302122UL)
> +#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (0x2fd7a554UL)
> +#define MAC_PCS_STAT_PCS_RX_MISALIGNED (0x4f8958c8UL)
> +#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (0xce46c6b2UL)
> +#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (0xb73e135cUL)
> +#define MAC_PCS_STAT_PCS_RX_STATUS (0x6087afc3UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH (0x12a96a4UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (0xffeb7af8UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (0x43af96a9UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (0x9a4f180dUL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (0x170bb0a7UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT
> (0x97082914UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (0xee9d9936UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (0x64a891f6UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT
> (0x547ece84UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (0x14435914UL)
> +#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (0x73c2cc65UL)
> +#define MAC_PCS_STAT_PCS_TX (0xe747bd8aUL)
> +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (0xd715eee2UL)
> +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (0x125aedaaUL)
> +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (0x892ad851UL)
> +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED
> (0xf39f6854UL)
> +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (0x6075c4dfUL)
> +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED
> (0xcd4c168aUL)
> +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (0x4483a41fUL)
> +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (0xcbd66e98UL)
> +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (0xb65e59a1UL)
> +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (0x9157fdd8UL)
> +#define MAC_PCS_SYNCED (0x76ad78aaUL)
> +#define MAC_PCS_SYNCED_SYNC (0xbff0beadUL)
> +#define MAC_PCS_SYNCED_ERR (0x136856e9UL)
> +#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (0x16c52dc7UL)
> +#define MAC_PCS_TEST_ERR (0xbf52be89UL)
> +#define MAC_PCS_TEST_ERR_CODE_ERR (0x33a662cUL)
> +#define MAC_PCS_TIMESTAMP_COMP (0x3054d1fcUL)
> +#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (0xa6496d75UL)
> +#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (0x70108e68UL)
> +#define MAC_PCS_VL_DEMUXED (0xe1a41659UL)
> +#define MAC_PCS_VL_DEMUXED_LOCK (0xf1e85d36UL)
> +#define MAC_PCS_VL_DEMUXED_CHG (0xa326d6a6UL)
> +#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (0x9327587fUL)
> +#define MAC_PCS_VL_NUMBER (0x149d9e3UL)
> +#define MAC_PCS_VL_NUMBER_VL_NUMBER (0x3b87c706UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _PCS_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > new file mode 100644
> index 0000000000..92878fb01f
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h > @@ -0,0 +1,1092 @@
> +/*
> + * nthw_fpga_reg_defs_mac_pcs_xxv.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_
> +#define _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_
> +
> +/* MAC_PCS_XXV */
> +#define NTHW_MOD_MAC_PCS_XXV (0x3ea7bfeaUL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0 (0xe8535535UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ASMDIR (0xc90a5f78UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_BYPASS (0x66bcb293UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ENABLE (0x7a14fcd5UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_PAUSE (0xb0859554UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_RESTART (0xe270c120UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1 (0x9f5465a3UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ASMDIR (0x5a05fe6UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_BYPASS (0xaa16b20dUL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ENABLE (0xb6befc4bUL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_PAUSE (0x16f29ee0UL)
> +#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_RESTART (0xf50bd563UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0 (0x577adc44UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0_COMPLETE (0xc61358ebUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ANEG_ABLE (0x61fcc32aUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ASM (0x9aa1191UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_PAUSE (0x61b6e89aUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_RF (0x1f056f1eUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1 (0x207decd2UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1_COMPLETE (0x29d133d5UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ANEG_ABLE (0xfcf3225cUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ASM (0xc500110fUL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_PAUSE (0x8e7483a4UL)
> +#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_RF (0xb97264aaUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0 (0xd2af0b3bUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR (0xe523e7bcUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR1 (0x41ee33f7UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR_S (0xf8862066UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR (0xb2bec4abUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR1 (0xc26a2b13UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR_S (0x5f62821fUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1 (0xa5a83badUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR (0x291b88c4UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR1 (0x1ffcf296UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR_S (0xc26d6369UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR (0x412a26e0UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR1 (0x239727e9UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR_S (0x2eb6411UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2 (0x3ca16a17UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR (0x5e855a34UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR1 (0xa2369e58UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR_S (0xbe0c46b2UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR (0x36b4f410UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR1 (0x9e5d4b27UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR_S (0x7e8a41caUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3 (0x4ba65a81UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR (0xc520165bUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR1 (0x7fa047ddUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR_S (0x2303a7c4UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR (0xad11b87fUL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR1 (0x43cb92a2UL)
> +#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR_S (0xe385a0bcUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0 (0x4c943ef2UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_ASMDIR (0x3bbfbb7dUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_BYPASS (0x94095696UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_ENABLE (0x88a118d0UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST (0x76aa937UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST_10G
> (0x1a5e1df6UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_ABILITY (0x5d6cbd68UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_REQUEST (0x5334dccbUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_HIDE_FEC74 (0xf0c50196UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_NONCE_SEED (0x8f9feb1eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_PAUSE (0x6761de07UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_PSEUDO (0xfdcd997fUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_REMOTE_FAULT (0xa56faacbUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_RESTART (0x92e8804bUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_RS_FEC_REQUEST
> (0x5bcb427dUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_FEC_OVERWRITE
> (0x28a23fa1UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_SPEED_OVERWRITE
> (0x864c3454UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1 (0x3b930e64UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_ASMDIR (0xf715bbe3UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_BYPASS (0x58a35608UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_ENABLE (0x440b184eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST (0xbe9172dfUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST_10G
> (0xcdbc9daeUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_ABILITY (0xe4976680UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_REQUEST (0xeacf0723UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_HIDE_FEC74 (0x6b604df9UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_NONCE_SEED (0x143aa771UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_PAUSE (0xc116d5b3UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_PSEUDO (0x316799e1UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_REMOTE_FAULT (0x38604bbdUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_RESTART (0x85939408UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_RS_FEC_REQUEST
> (0xf5a3d3ecUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_FEC_OVERWRITE
> (0xc7f08940UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_SPEED_OVERWRITE
> (0xe32b0f12UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2 (0xa29a5fdeUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_ASMDIR (0x799abc00UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_BYPASS (0xd62c51ebUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_ENABLE (0xca841fadUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST (0xafec18a6UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST_10G
> (0x6eea1b07UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_ABILITY (0xf5ea0cf9UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_REQUEST (0xfbb26d5aUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_HIDE_FEC74 (0x1cfe9f09UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_NONCE_SEED (0x63a47581UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_PAUSE (0xf0fecf2eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_PSEUDO (0xbfe89e02UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_REMOTE_FAULT (0x44016e66UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_RESTART (0xbc1ea8cdUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_RS_FEC_REQUEST
> (0xdc6b671eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_FEC_OVERWRITE
> (0x2d765422UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_SPEED_OVERWRITE
> (0x4c8242d8UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3 (0xd59d6f48UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_ASMDIR (0xb530bc9eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_BYPASS (0x1a865175UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_ENABLE (0x62e1f33UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST
> (0x1617c34eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST_10G
> (0xb9089b5fUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_ABILITY (0x4c11d711UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_REQUEST
> (0x4249b6b2UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_HIDE_FEC74 (0x875bd366UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_NONCE_SEED (0xf80139eeUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_PAUSE (0x5689c49aUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_PSEUDO (0x73429e9cUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_REMOTE_FAULT (0xd90e8f10UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_RESTART (0xab65bc8eUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_RS_FEC_REQUEST
> (0x7203f68fUL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_FEC_OVERWRITE
> (0xc224e2c3UL)
> +#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_SPEED_OVERWRITE
> (0x29e5799eUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0 (0x44ac1d35UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_END (0x85d17994UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_STARTED (0xd51a0134UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0_CDR_HOLD (0xdfa847b5UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_END (0xa921af33UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_STARTED (0xaac6e454UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1 (0x33ab2da3UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_END (0x6a1312aaUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_STARTED (0x4815e042UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1_CDR_HOLD (0x306a2c8bUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_END (0x658bafadUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_STARTED (0x3163a83bUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2 (0xaaa27c19UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_END (0x8124a9a9UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_STARTED (0x3474c599UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2_CDR_HOLD (0xdb5d9788UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_END (0xeb04a84eUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_STARTED (0x46fd7acbUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3 (0xdda54c8fUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_END (0x6ee6c297UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_STARTED (0xa97b24efUL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3_CDR_HOLD (0x349ffcb6UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_END (0x27aea8d0UL)
> +#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_STARTED (0xdd5836a4UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_0 (0x9cd3a7adUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR (0x833d2c0eUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR1 (0x64e7ff9cUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR_S (0x22c3917aUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_1 (0xebd4973bUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR (0x9446384dUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR1 (0x8b2594a2UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR_S (0xe34d4ebaUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_2 (0x72ddc681UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR (0xadcb0488UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR1 (0x60122fa1UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR_S (0x7aaf28bbUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_3 (0x5daf617UL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR (0xbab010cbUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR1 (0x8fd0449fUL)
> +#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR_S (0xbb21f77bUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0 (0x679ed455UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR
> (0xc77ef9eaUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR_S
> (0xee68c58aUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1 (0x1099e4c3UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR
> (0x7e852202UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR_S
> (0x69ce0ec9UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2 (0x8990b579UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR
> (0x6ff8487bUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR_S
> (0x3a54554dUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3 (0xfe9785efUL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR
> (0xd6039393UL)
> +#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR_S
> (0xbdf29e0eUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0 (0x29fb18a1UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_ABILITY
> (0x15810dbeUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_REQUEST
> (0x1bd96c1dUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_ABILITY
> (0x41df7842UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_REQUEST
> (0x4f8719e1UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_25GBASE_CR1
> (0x23d251c1UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_EX_ABILITY_VALID
> (0xc632a6a7UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1 (0x5efc2837UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_ABILITY
> (0x9227c6fdUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_REQUEST
> (0x9c7fa75eUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_ABILITY
> (0xc679b301UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_REQUEST
> (0xc821d2a2UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_25GBASE_CR1
> (0x8dbac050UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_EX_ABILITY_VALID
> (0x59e82539UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2 (0xc7f5798dUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_ABILITY
> (0xc1bd9d79UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_REQUEST
> (0xcfe5fcdaUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_ABILITY
> (0x95e3e885UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_REQUEST
> (0x9bbb8926UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_25GBASE_CR1
> (0xa47274a2UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_EX_ABILITY_VALID
> (0x22f6a7daUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3 (0xb0f2491bUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_ABILITY
> (0x461b563aUL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_REQUEST
> (0x48433799UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_ABILITY
> (0x124523c6UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_REQUEST
> (0x1c1d4265UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_25GBASE_CR1
> (0xa1ae533UL)
> +#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_EX_ABILITY_VALID
> (0xbd2c2444UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0 (0xc256fa45UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ABILITY_VALID (0x414cfb0cUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ANEG_ABLE (0xe0623a0aUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ASM (0xf0872f9dUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_FEC74_REQ (0x3881d9daUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_PAUSE (0xc624310UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RF (0x8be40c82UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RS_FEC_REQ (0x9807cff4UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1 (0xb551cad3UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ABILITY_VALID
> (0xae1e4dedUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ANEG_ABLE (0x7d6ddb7cUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ASM (0x3c2d2f03UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_FEC74_REQ (0xa58e38acUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_PAUSE (0xe3a0282eUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RF (0x2d930736UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RS_FEC_REQ (0x21fc141cUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2 (0x2c589b69UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ABILITY_VALID
> (0x4498908fUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ANEG_ABLE (0x10cfea7UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ASM (0xb2a228e0UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_FEC74_REQ (0xd9ef1d77UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_PAUSE (0x897932dUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RF (0x1c7b1dabUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RS_FEC_REQ (0x30817e65UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3 (0x5b5fabffUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ABILITY_VALID
> (0xabca266eUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ANEG_ABLE (0x9c031fd1UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ASM (0x7e08287eUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_FEC74_REQ (0x44e0fc01UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_PAUSE (0xe755f813UL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RF (0xba0c161fUL)
> +#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RS_FEC_REQ (0x897aa58dUL)
> +#define MAC_PCS_XXV_ANEG_STA_0 (0x3ed7a2b9UL)
> +#define MAC_PCS_XXV_ANEG_STA_0_COMPLETE (0x11f713b8UL)
> +#define MAC_PCS_XXV_ANEG_STA_0_FEC74_EN (0x974edcf2UL)
> +#define MAC_PCS_XXV_ANEG_STA_0_PAR_D_FAULT (0xabe31863UL)
> +#define MAC_PCS_XXV_ANEG_STA_0_RS_FEC_EN (0x178283ccUL)
> +#define MAC_PCS_XXV_ANEG_STA_0_RX_PAUSE_EN (0xf5adbafaUL)
> +#define MAC_PCS_XXV_ANEG_STA_0_TX_PAUSE_EN (0x1d1870b9UL)
> +#define MAC_PCS_XXV_ANEG_STA_1 (0x49d0922fUL)
> +#define MAC_PCS_XXV_ANEG_STA_1_COMPLETE (0xfe357886UL)
> +#define MAC_PCS_XXV_ANEG_STA_1_FEC74_EN (0x788cb7ccUL)
> +#define MAC_PCS_XXV_ANEG_STA_1_PAR_D_FAULT (0x7675c1e6UL)
> +#define MAC_PCS_XXV_ANEG_STA_1_RS_FEC_EN (0xd60c5c0cUL)
> +#define MAC_PCS_XXV_ANEG_STA_1_RX_PAUSE_EN (0x283b637fUL)
> +#define MAC_PCS_XXV_ANEG_STA_1_TX_PAUSE_EN (0xc08ea93cUL)
> +#define MAC_PCS_XXV_ANEG_STA_2 (0xd0d9c395UL)
> +#define MAC_PCS_XXV_ANEG_STA_2_COMPLETE (0x1502c385UL)
> +#define MAC_PCS_XXV_ANEG_STA_2_FEC74_EN (0x93bb0ccfUL)
> +#define MAC_PCS_XXV_ANEG_STA_2_PAR_D_FAULT (0xcbbfad28UL)
> +#define MAC_PCS_XXV_ANEG_STA_2_RS_FEC_EN (0x4fee3a0dUL)
> +#define MAC_PCS_XXV_ANEG_STA_2_RX_PAUSE_EN (0x95f10fb1UL)
> +#define MAC_PCS_XXV_ANEG_STA_2_TX_PAUSE_EN (0x7d44c5f2UL)
> +#define MAC_PCS_XXV_ANEG_STA_3 (0xa7def303UL)
> +#define MAC_PCS_XXV_ANEG_STA_3_COMPLETE (0xfac0a8bbUL)
> +#define MAC_PCS_XXV_ANEG_STA_3_FEC74_EN (0x7c7967f1UL)
> +#define MAC_PCS_XXV_ANEG_STA_3_PAR_D_FAULT (0x162974adUL)
> +#define MAC_PCS_XXV_ANEG_STA_3_RS_FEC_EN (0x8e60e5cdUL)
> +#define MAC_PCS_XXV_ANEG_STA_3_RX_PAUSE_EN (0x4867d634UL)
> +#define MAC_PCS_XXV_ANEG_STA_3_TX_PAUSE_EN (0xa0d21c77UL)
> +#define MAC_PCS_XXV_CLK_REF_ACTIVITY (0xad9a1b80UL)
> +#define MAC_PCS_XXV_CLK_REF_ACTIVITY_COUNT (0x3216c992UL)
> +#define MAC_PCS_XXV_CORE_CONF_0 (0xc665a258UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_ENHANCED_TS (0x10792af0UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_INLINE_MODE (0xb75bd54aUL)
> +#define MAC_PCS_XXV_CORE_CONF_0_LINE_LOOPBACK (0xe27b24f2UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_RX_ENABLE (0x58298567UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_RX_FORCE_RESYNC
> (0x391c7c3bUL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TS_AT_EOP (0x34e1ac8fUL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_ENABLE (0x2b33fcedUL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_IGN_FCS (0x65b14385UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_INS_FCS (0xdace417eUL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_IDLE (0xbb7c23d4UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_LFI (0x3c99f330UL)
> +#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_RFI (0x2a217d4aUL)
> +#define MAC_PCS_XXV_CORE_CONF_1 (0xb16292ceUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_ENHANCED_TS (0xcdeff375UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_INLINE_MODE (0x6acd0ccfUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_LINE_LOOPBACK (0x5b80ff1aUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_RX_ENABLE (0x99a75aa7UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_RX_FORCE_RESYNC
> (0xbebab778UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TS_AT_EOP (0xf56f734fUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_ENABLE (0xeabd232dUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_IGN_FCS (0xfe140feaUL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_INS_FCS (0x416b0d11UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_IDLE (0x2673c2a2UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_LFI (0xe10f2ab5UL)
> +#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_RFI (0xf7b7a4cfUL)
> +#define MAC_PCS_XXV_CORE_CONF_2 (0x286bc374UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_ENHANCED_TS (0x70259fbbUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_INLINE_MODE (0xd7076001UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_LINE_LOOPBACK (0x4afd9563UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_RX_ENABLE (0x453ca6UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_RX_FORCE_RESYNC (0xed20ecfcUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TS_AT_EOP (0x6c8d154eUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_ENABLE (0x735f452cUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_IGN_FCS (0x898add1aUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_INS_FCS (0x36f5dfe1UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_IDLE (0x5a12e779UL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_LFI (0x5cc5467bUL)
> +#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_RFI (0x4a7dc801UL)
> +#define MAC_PCS_XXV_CORE_CONF_3 (0x5f6cf3e2UL)
> +#define MAC_PCS_XXV_CORE_CONF_3_ENHANCED_TS (0xadb3463eUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_INLINE_MODE (0xa91b984UL)
> +#define MAC_PCS_XXV_CORE_CONF_3_LINE_LOOPBACK (0xf3064e8bUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_RX_ENABLE (0xc1cbe366UL)
> +#define MAC_PCS_XXV_CORE_CONF_3_RX_FORCE_RESYNC
> (0x6a8627bfUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TS_AT_EOP (0xad03ca8eUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_ENABLE (0xb2d19aecUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_IGN_FCS (0x122f9175UL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_INS_FCS (0xad50938eUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_IDLE (0xc71d060fUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_LFI (0x81539ffeUL)
> +#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_RFI (0x97eb1184UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0 (0xcd1b26beUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_DEBOUNCE_LATENCY
> (0x32bcbfc6UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_FORCE_LINK_DOWN
> (0xf5caa84cUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_LINKUP_LATENCY
> (0x39c69ab7UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_PORT_CTRL
> (0xbba352c4UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1 (0xba1c1628UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_DEBOUNCE_LATENCY
> (0xad663c58UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_FORCE_LINK_DOWN
> (0x90ad930aUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_LINKUP_LATENCY
> (0xee241aefUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_PORT_CTRL
> (0x26acb3b2UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2 (0x23154792UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_DEBOUNCE_LATENCY
> (0xd678bebbUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_FORCE_LINK_DOWN
> (0x3f04dec0UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_LINKUP_LATENCY
> (0x4d729c46UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_PORT_CTRL
> (0x5acd9669UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3 (0x54127704UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_DEBOUNCE_LATENCY
> (0x49a23d25UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_FORCE_LINK_DOWN
> (0x5a63e586UL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_LINKUP_LATENCY
> (0x9a901c1eUL)
> +#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_PORT_CTRL
> (0xc7c2771fUL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_0 (0x98d5cef3UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_0_FEC74_CCW_CNT
> (0x98570079UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_1 (0xefd2fe65UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_1_FEC74_CCW_CNT
> (0x21acdb91UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_2 (0x76dbafdfUL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_2_FEC74_CCW_CNT
> (0x30d1b1e8UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_3 (0x1dc9f49UL)
> +#define MAC_PCS_XXV_FEC74_CCW_CNT_3_FEC74_CCW_CNT
> (0x892a6a00UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_0 (0xd8988d69UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_0_FEC74_ERRORS_TO_PCS
> (0xbad20553UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_0_RX_FEC74_ENABLE
> (0x95657559UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_0_TX_FEC74_ENABLE
> (0xb79fa1abUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_1 (0xaf9fbdffUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_1_FEC74_ERRORS_TO_PCS
> (0x250886cdUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_1_RX_FEC74_ENABLE
> (0x12c3be1aUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_1_TX_FEC74_ENABLE
> (0x30396ae8UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_2 (0x3696ec45UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_2_FEC74_ERRORS_TO_PCS
> (0x5e16042eUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_2_RX_FEC74_ENABLE
> (0x4159e59eUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_2_TX_FEC74_ENABLE
> (0x63a3316cUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_3 (0x4191dcd3UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_3_FEC74_ERRORS_TO_PCS
> (0xc1cc87b0UL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_3_RX_FEC74_ENABLE
> (0xc6ff2eddUL)
> +#define MAC_PCS_XXV_FEC74_CONFIG_3_TX_FEC74_ENABLE
> (0xe405fa2fUL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_0 (0x470ff508UL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_0_FEC74_UCW_CNT
> (0x70e15dbbUL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_1 (0x3008c59eUL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_1_FEC74_UCW_CNT
> (0xc91a8653UL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_2 (0xa9019424UL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_2_FEC74_UCW_CNT
> (0xd867ec2aUL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_3 (0xde06a4b2UL)
> +#define MAC_PCS_XXV_FEC74_UCW_CNT_3_FEC74_UCW_CNT
> (0x619c37c2UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0 (0xb45ac330UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0_CDR_HOLD (0x9494702eUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0_EQUA_RST (0xac159264UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0_LPM_EN (0x8f3f6136UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0_POLARITY (0x589f67ddUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_0_RATE (0x54b5525dUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1 (0xc35df3a6UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1_CDR_HOLD (0x7b561b10UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1_EQUA_RST (0x43d7f95aUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1_LPM_EN (0x439561a8UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1_POLARITY (0xb75d0ce3UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_1_RATE (0x9fe981f8UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2 (0x5a54a21cUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2_CDR_HOLD (0x9061a013UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2_EQUA_RST (0xa8e04259UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2_LPM_EN (0xcd1a664bUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2_POLARITY (0x5c6ab7e0UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_2_RATE (0x197df356UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3 (0x2d53928aUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3_CDR_HOLD (0x7fa3cb2dUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3_EQUA_RST (0x47222967UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3_LPM_EN (0x1b066d5UL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3_POLARITY (0xb3a8dcdeUL)
> +#define MAC_PCS_XXV_GTY_CTL_RX_3_RATE (0xd22120f3UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_0 (0x91319cecUL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_0_INHIBIT (0x2743e45UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_0_POLARITY (0xf87ab800UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_1 (0xe636ac7aUL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_1_INHIBIT (0x150f2a06UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_1_POLARITY (0x17b8d33eUL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_2 (0x7f3ffdc0UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_2_INHIBIT (0x2c8216c3UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_2_POLARITY (0xfc8f683dUL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_3 (0x838cd56UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_3_INHIBIT (0x3bf90280UL)
> +#define MAC_PCS_XXV_GTY_CTL_TX_3_POLARITY (0x134d0303UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_0 (0x7a99aa99UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL (0xcdf499beUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL_ADJUSTED
> (0x833ddf3dUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_1 (0xd9e9a0fUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL (0x1062403bUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL_ADJUSTED
> (0x9415bbfdUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_2 (0x9497cbb5UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL (0xada82cf5UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL_ADJUSTED
> (0xad6d16bdUL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_3 (0xe390fb23UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL (0x703ef570UL)
> +#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL_ADJUSTED
> (0xba45727dUL)
> +#define MAC_PCS_XXV_GTY_LOOP_0 (0xcfacffb3UL)
> +#define MAC_PCS_XXV_GTY_LOOP_0_GT_LOOP (0x5c74ecacUL)
> +#define MAC_PCS_XXV_GTY_LOOP_1 (0xb8abcf25UL)
> +#define MAC_PCS_XXV_GTY_LOOP_1_GT_LOOP (0x4b0ff8efUL)
> +#define MAC_PCS_XXV_GTY_LOOP_2 (0x21a29e9fUL)
> +#define MAC_PCS_XXV_GTY_LOOP_2_GT_LOOP (0x7282c42aUL)
> +#define MAC_PCS_XXV_GTY_LOOP_3 (0x56a5ae09UL)
> +#define MAC_PCS_XXV_GTY_LOOP_3_GT_LOOP (0x65f9d069UL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_0 (0xd79b7f80UL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_0_TX_MAIN_CTL (0xded513f4UL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_1 (0xa09c4f16UL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_1_TX_MAIN_CTL (0x343ca71UL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_2 (0x39951eacUL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_2_TX_MAIN_CTL (0xbe89a6bfUL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_3 (0x4e922e3aUL)
> +#define MAC_PCS_XXV_GTY_MAIN_CTL_3_TX_MAIN_CTL (0x631f7f3aUL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_0 (0xaa04cb19UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR
> (0x7b6f0b43UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR_ADJUSTED
> (0xa87d9ad2UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_1 (0xdd03fb8fUL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR
> (0xa6f9d2c6UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR_ADJUSTED
> (0xbf55fe12UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_2 (0x440aaa35UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR
> (0x1b33be08UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR_ADJUSTED
> (0x862d5352UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_3 (0x330d9aa3UL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR
> (0xc6a5678dUL)
> +#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR_ADJUSTED
> (0x91053792UL)
> +#define MAC_PCS_XXV_GTY_PRBS_0 (0xd3e408e4UL)
> +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR (0x4fd820bdUL)
> +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR_INS (0x292ed7d3UL)
> +#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_RST (0xa6c9013cUL)
> +#define MAC_PCS_XXV_GTY_PRBS_0_RX_PRBS_SEL (0x9c43c790UL)
> +#define MAC_PCS_XXV_GTY_PRBS_0_TX_PRBS_SEL (0x74f60dd3UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1 (0xa4e33872UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR (0xa01a4b83UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR_INS (0xb42136a5UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_RST (0x490b6a02UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1_RX_PRBS_SEL (0x41d51e15UL)
> +#define MAC_PCS_XXV_GTY_PRBS_1_TX_PRBS_SEL (0xa960d456UL)
> +#define MAC_PCS_XXV_GTY_PRBS_2 (0x3dea69c8UL)
> +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR (0x4b2df080UL)
> +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR_INS (0xc840137eUL)
> +#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_RST (0xa23cd101UL)
> +#define MAC_PCS_XXV_GTY_PRBS_2_RX_PRBS_SEL (0xfc1f72dbUL)
> +#define MAC_PCS_XXV_GTY_PRBS_2_TX_PRBS_SEL (0x14aab898UL)
> +#define MAC_PCS_XXV_GTY_PRBS_3 (0x4aed595eUL)
> +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR (0xa4ef9bbeUL)
> +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR_INS (0x554ff208UL)
> +#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_RST (0x4dfeba3fUL)
> +#define MAC_PCS_XXV_GTY_PRBS_3_RX_PRBS_SEL (0x2189ab5eUL)
> +#define MAC_PCS_XXV_GTY_PRBS_3_TX_PRBS_SEL (0xc93c611dUL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_0 (0xe674af07UL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_0_COUNT (0x9e8b170cUL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_1 (0x91739f91UL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_1_COUNT (0x38fc1cb8UL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_2 (0x87ace2bUL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_2_COUNT (0x9140625UL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_3 (0x7f7dfebdUL)
> +#define MAC_PCS_XXV_GTY_PRBS_CNT_3_COUNT (0xaf630d91UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0 (0xa5879edeUL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR (0x2f0d4bd2UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR_ADJUSTED
> (0xd738196fUL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1 (0xd280ae48UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR (0xb4a807bdUL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR_ADJUSTED
> (0x48e29af1UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2 (0x4b89fff2UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR (0xc336d54dUL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR_ADJUSTED
> (0x33fc1812UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3 (0x3c8ecf64UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR (0x58939922UL)
> +#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR_ADJUSTED
> (0xac269b8cUL)
> +#define MAC_PCS_XXV_GTY_STATUS_0 (0x922d078cUL)
> +#define MAC_PCS_XXV_GTY_STATUS_0_GT_POWERGOOD (0x46fffefcUL)
> +#define MAC_PCS_XXV_GTY_STATUS_0_GT_RXBUFSTATUS (0x71961330UL)
> +#define MAC_PCS_XXV_GTY_STATUS_0_GT_STARTOFSEQ (0x302abe66UL)
> +#define MAC_PCS_XXV_GTY_STATUS_0_GT_TXBUFSTATUS (0x9923d973UL)
> +#define MAC_PCS_XXV_GTY_STATUS_1 (0xe52a371aUL)
> +#define MAC_PCS_XXV_GTY_STATUS_1_GT_POWERGOOD (0xdbf01f8aUL)
> +#define MAC_PCS_XXV_GTY_STATUS_1_GT_RXBUFSTATUS (0xdffe82a1UL)
> +#define MAC_PCS_XXV_GTY_STATUS_1_GT_STARTOFSEQ (0x89d1658eUL)
> +#define MAC_PCS_XXV_GTY_STATUS_1_GT_TXBUFSTATUS (0x374b48e2UL)
> +#define MAC_PCS_XXV_GTY_STATUS_2 (0x7c2366a0UL)
> +#define MAC_PCS_XXV_GTY_STATUS_2_GT_POWERGOOD (0xa7913a51UL)
> +#define MAC_PCS_XXV_GTY_STATUS_2_GT_RXBUFSTATUS (0xf6363653UL)
> +#define MAC_PCS_XXV_GTY_STATUS_2_GT_STARTOFSEQ (0x98ac0ff7UL)
> +#define MAC_PCS_XXV_GTY_STATUS_2_GT_TXBUFSTATUS (0x1e83fc10UL)
> +#define MAC_PCS_XXV_GTY_STATUS_3 (0xb245636UL)
> +#define MAC_PCS_XXV_GTY_STATUS_3_GT_POWERGOOD (0x3a9edb27UL)
> +#define MAC_PCS_XXV_GTY_STATUS_3_GT_RXBUFSTATUS (0x585ea7c2UL)
> +#define MAC_PCS_XXV_GTY_STATUS_3_GT_STARTOFSEQ (0x2157d41fUL)
> +#define MAC_PCS_XXV_GTY_STATUS_3_GT_TXBUFSTATUS (0xb0eb6d81UL)
> +#define MAC_PCS_XXV_LATENCY_0 (0x1ebce893UL)
> +#define MAC_PCS_XXV_LATENCY_0_RX_LATENCY_MEAS (0x16e7962UL)
> +#define MAC_PCS_XXV_LATENCY_1 (0x69bbd805UL)
> +#define MAC_PCS_XXV_LATENCY_1_RX_LATENCY_MEAS (0x86c8b221UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0 (0x64b5dd89UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_MAIN
> (0x3a6efcd0UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_POST
> (0xdfcc5d39UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_PRE
> (0xa8605393UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_MAIN
> (0xa36cbdfbUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_POST
> (0x46ce1c12UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_PRE (0xa370c290UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INIT (0xc3ba915bUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_PRESET (0xb0c65848UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1 (0x13b2ed1fUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_MAIN
> (0xd5ac97eeUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_POST
> (0x300e3607UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_PRE
> (0xbf1b47d0UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_MAIN
> (0x4caed6c5UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_POST
> (0xa90c772cUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_PRE
> (0xb40bd6d3UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INIT (0x8e642feUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_PRESET (0x7c6c58d6UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2 (0x8abbbca5UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_MAIN
> (0x3e9b2cedUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_POST
> (0xdb398d04UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_PRE
> (0x86967b15UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_MAIN
> (0xa7996dc6UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_POST
> (0x423bcc2fUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_PRE (0x8d86ea16UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INIT (0x8e723050UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_PRESET (0xf2e35f35UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3 (0xfdbc8c33UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_MAIN
> (0xd15947d3UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_POST
> (0x34fbe63aUL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_PRE (0x91ed6f56UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_MAIN
> (0x485b06f8UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_POST
> (0xadf9a711UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_PRE (0x9afdfe55UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INIT (0x452ee3f5UL)
> +#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_PRESET (0x3e495fabUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_0 (0xf103387fUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_MAIN_STA (0x87c6ab44UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_POST_STA (0xb85a5a3dUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_0_PRE_STA (0x44fa3d7eUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_1 (0x860408e9UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_MAIN_STA (0x6804c07aUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_POST_STA (0x57983103UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_1_PRE_STA (0x5381293dUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_2 (0x1f0d5953UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_MAIN_STA (0x83337b79UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_POST_STA (0xbcaf8a00UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_2_PRE_STA (0x6a0c15f8UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_3 (0x680a69c5UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_MAIN_STA (0x6cf11047UL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_POST_STA (0x536de13eUL)
> +#define MAC_PCS_XXV_LE_LT_STA_SEND_3_PRE_STA (0x7d7701bbUL)
> +#define MAC_PCS_XXV_LINK_SPEED_0 (0xfcf10505UL)
> +#define MAC_PCS_XXV_LINK_SPEED_0_10G (0xfb473664UL)
> +#define MAC_PCS_XXV_LINK_SPEED_0_SPEED (0xa81deb0bUL)
> +#define MAC_PCS_XXV_LINK_SPEED_0_TOGGLE (0xdd2f38f7UL)
> +#define MAC_PCS_XXV_LINK_SPEED_1 (0x8bf63593UL)
> +#define MAC_PCS_XXV_LINK_SPEED_1_10G (0xc6271fd4UL)
> +#define MAC_PCS_XXV_LINK_SPEED_1_SPEED (0xe6ae0bfUL)
> +#define MAC_PCS_XXV_LINK_SPEED_1_TOGGLE (0x11853869UL)
> +#define MAC_PCS_XXV_LINK_SPEED_2 (0x12ff6429UL)
> +#define MAC_PCS_XXV_LINK_SPEED_2_10G (0x81876504UL)
> +#define MAC_PCS_XXV_LINK_SPEED_2_SPEED (0x3f82fa22UL)
> +#define MAC_PCS_XXV_LINK_SPEED_2_TOGGLE (0x9f0a3f8aUL)
> +#define MAC_PCS_XXV_LINK_SPEED_3 (0x65f854bfUL)
> +#define MAC_PCS_XXV_LINK_SPEED_3_10G (0xbce74cb4UL)
> +#define MAC_PCS_XXV_LINK_SPEED_3_SPEED (0x99f5f196UL)
> +#define MAC_PCS_XXV_LINK_SPEED_3_TOGGLE (0x53a03f14UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0 (0xbdeefa9fUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_ABS (0x881db88UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_COMPLETE
> (0x5fc67735UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_CONSORTIUM_MISMATCH
> (0x61d4136fUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_INTERNAL_LOCAL_FAULT
> (0x16fc1a7aUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_ABS (0x159942b9UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_INTERNAL_LOCAL_FAULT
> (0x95aab8f5UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_LOCAL_FAULT
> (0x4a2e2158UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT
> (0x56dc5f65UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_REMOTE_FAULT
> (0xbeeda6f3UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_FEC74_LOCK_ERROR
> (0xcf25e9b5UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE
> (0x8d8fa991UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_PCS_VALID_CTRL_CODE
> (0x2846c322UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_RSFEC_HI_SER
> (0xbb5aafe6UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_LOCAL_FAULT
> (0x8f3e56b4UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_UNDERRUN
> (0xb1c337c4UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LINK_DOWN_CNT
> (0xbe8bc6e3UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_PHY_LINK_STATE
> (0x7050253fUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK
> (0x639554a2UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_FEC74_LOCK
> (0x73211ce0UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_RSFEC_LANE_ALIGNMENT
> (0xd0bd97c6UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_0_LL_TX_RSFEC_LANE_ALIGNMENT
> (0x3d77e5bcUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_LT_DONE (0xd2620565UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_NIM_INTERR (0x28ee3c81UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_0_NT_PHY_LINK_STATE
> (0x31581429UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1 (0xcae9ca09UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_ABS (0x35e1f238UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_COMPLETE
> (0xe63dacddUL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_CONSORTIUM_MISMATCH
> (0x86c9b5f8UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_INTERNAL_LOCAL_FAULT
> (0x1d47ebaUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_ABS (0xd9334227UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_INTERNAL_LOCAL_FAULT
> (0x302128fbUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_LOCAL_FAULT
> (0xe446b0c9UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT
> (0xf357cf6bUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_REMOTE_FAULT
> (0x394b6db0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_FEC74_LOCK_ERROR
> (0x4e008c92UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE
> (0xe303b2d0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_PCS_VALID_CTRL_CODE
> (0x46cad863UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_RSFEC_HI_SER
> (0xde3d94a0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_LOCAL_FAULT
> (0x58dcd6ecUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_UNDERRUN
> (0x1faba655UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LINK_DOWN_CNT
> (0x7701d0bUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_PHY_LINK_STATE
> (0xa7b2a567UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK
> (0x8cc7e243UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_FEC74_LOCK
> (0x9c73aa01UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_RSFEC_LANE_ALIGNMENT
> (0xd1086adbUL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_1_LL_TX_RSFEC_LANE_ALIGNMENT
> (0x3cc218a1UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_LT_DONE (0xc5191126UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_NIM_INTERR (0xb34b70eeUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_1_NT_PHY_LINK_STATE
> (0xe6ba9471UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2 (0x53e09bb3UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_ABS (0x724188e8UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_COMPLETE
> (0xf740c6a4UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_CONSORTIUM_MISMATCH
> (0x749e5800UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_INTERNAL_LOCAL_FAULT
> (0x38acd3faUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_ABS (0x57bc45c4UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_INTERNAL_LOCAL_FAULT
> (0x5cc9ea8UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_LOCAL_FAULT
> (0xcd8e043bUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RECEIVED_LOCAL_FAULT
> (0xc6ba7938UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_REMOTE_FAULT
> (0x6ad13634UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_FEC74_LOCK_ERROR
> (0x161e25baUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_HIGH_BIT_ERROR_RATE
> (0x50979f13UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_PCS_VALID_CTRL_CODE
> (0xf55ef5a0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_RSFEC_HI_SER
> (0x7194d96aUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_LOCAL_FAULT
> (0xfb8a5045UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_UNDERRUN
> (0x366312a7UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LINK_DOWN_CNT
> (0x160d7772UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_PHY_LINK_STATE
> (0x4e423ceUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_BLOCK_LOCK
> (0x66413f21UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_FEC74_LOCK
> (0x76f57763UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_RSFEC_LANE_ALIGNMENT
> (0xd3d66dfcUL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_2_LL_TX_RSFEC_LANE_ALIGNMENT
> (0x3e1c1f86UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_LT_DONE (0xfc942de3UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_NIM_INTERR (0xc4d5a21eUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_2_NT_PHY_LINK_STATE
> (0x45ec12d8UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3 (0x24e7ab25UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_ABS (0x4f21a158UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_COMPLETE
> (0x4ebb1d4cUL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_CONSORTIUM_MISMATCH
> (0x9383fe97UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_INTERNAL_LOCAL_FAULT
> (0x2f84b73aUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_ABS (0x9b16455aUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_INTERNAL_LOCAL_FAULT
> (0xa0470ea6UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_LOCAL_FAULT
> (0x63e695aaUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RECEIVED_LOCAL_FAULT
> (0x6331e936UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_REMOTE_FAULT
> (0xed77fd77UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_FEC74_LOCK_ERROR
> (0x973b409dUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_HIGH_BIT_ERROR_RATE
> (0x3e1b8452UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_PCS_VALID_CTRL_CODE
> (0x9bd2eee1UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_RSFEC_HI_SER
> (0x14f3e22cUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_LOCAL_FAULT
> (0x2c68d01dUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_UNDERRUN
> (0x980b8336UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LINK_DOWN_CNT
> (0xaff6ac9aUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_PHY_LINK_STATE
> (0xd306a396UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_BLOCK_LOCK
> (0x891389c0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_FEC74_LOCK
> (0x99a7c182UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_RSFEC_LANE_ALIGNMENT
> (0xd26390e1UL)
> +#define
> MAC_PCS_XXV_LINK_SUMMARY_3_LL_TX_RSFEC_LANE_ALIGNMENT
> (0x3fa9e29bUL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_LT_DONE (0xebef39a0UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_NIM_INTERR (0x5f70ee71UL)
> +#define MAC_PCS_XXV_LINK_SUMMARY_3_NT_PHY_LINK_STATE
> (0x920e9280UL)
> +#define MAC_PCS_XXV_LT_CONF_0 (0x26c9751bUL)
> +#define MAC_PCS_XXV_LT_CONF_0_ENABLE (0xef1e1da6UL)
> +#define MAC_PCS_XXV_LT_CONF_0_RESTART (0x2be9eb47UL)
> +#define MAC_PCS_XXV_LT_CONF_0_SEED (0xfdf46f00UL)
> +#define MAC_PCS_XXV_LT_CONF_1 (0x51ce458dUL)
> +#define MAC_PCS_XXV_LT_CONF_1_ENABLE (0x23b41d38UL)
> +#define MAC_PCS_XXV_LT_CONF_1_RESTART (0x3c92ff04UL)
> +#define MAC_PCS_XXV_LT_CONF_1_SEED (0x36a8bca5UL)
> +#define MAC_PCS_XXV_LT_CONF_2 (0xc8c71437UL)
> +#define MAC_PCS_XXV_LT_CONF_2_ENABLE (0xad3b1adbUL)
> +#define MAC_PCS_XXV_LT_CONF_2_RESTART (0x51fc3c1UL)
> +#define MAC_PCS_XXV_LT_CONF_2_SEED (0xb03cce0bUL)
> +#define MAC_PCS_XXV_LT_CONF_3 (0xbfc024a1UL)
> +#define MAC_PCS_XXV_LT_CONF_3_ENABLE (0x61911a45UL)
> +#define MAC_PCS_XXV_LT_CONF_3_RESTART (0x1264d782UL)
> +#define MAC_PCS_XXV_LT_CONF_3_SEED (0x7b601daeUL)
> +#define MAC_PCS_XXV_LT_STA_0 (0xb58612d6UL)
> +#define MAC_PCS_XXV_LT_STA_0_DONE (0x3f809c59UL)
> +#define MAC_PCS_XXV_LT_STA_0_FAIL (0xa98a57bbUL)
> +#define MAC_PCS_XXV_LT_STA_0_LOCK (0xa822e7fcUL)
> +#define MAC_PCS_XXV_LT_STA_0_TRAIN (0x3494fa27UL)
> +#define MAC_PCS_XXV_LT_STA_1 (0xc2812240UL)
> +#define MAC_PCS_XXV_LT_STA_1_DONE (0xf4dc4ffcUL)
> +#define MAC_PCS_XXV_LT_STA_1_FAIL (0x62d6841eUL)
> +#define MAC_PCS_XXV_LT_STA_1_LOCK (0x637e3459UL)
> +#define MAC_PCS_XXV_LT_STA_1_TRAIN (0x92e3f193UL)
> +#define MAC_PCS_XXV_LT_STA_2 (0x5b8873faUL)
> +#define MAC_PCS_XXV_LT_STA_2_DONE (0x72483d52UL)
> +#define MAC_PCS_XXV_LT_STA_2_FAIL (0xe442f6b0UL)
> +#define MAC_PCS_XXV_LT_STA_2_LOCK (0xe5ea46f7UL)
> +#define MAC_PCS_XXV_LT_STA_2_TRAIN (0xa30beb0eUL)
> +#define MAC_PCS_XXV_LT_STA_3 (0x2c8f436cUL)
> +#define MAC_PCS_XXV_LT_STA_3_DONE (0xb914eef7UL)
> +#define MAC_PCS_XXV_LT_STA_3_FAIL (0x2f1e2515UL)
> +#define MAC_PCS_XXV_LT_STA_3_LOCK (0x2eb69552UL)
> +#define MAC_PCS_XXV_LT_STA_3_TRAIN (0x57ce0baUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_0 (0x397037c0UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_ATTRIB (0x38d464dcUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_NEXT (0x75b189c5UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_0_PREV (0xcd7c11acUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_1 (0x4e770756UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_ATTRIB (0xf47e6442UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_NEXT (0xbeed5a60UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_1_PREV (0x620c209UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_2 (0xd77e56ecUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_ATTRIB (0x7af163a1UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_NEXT (0x387928ceUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_2_PREV (0x80b4b0a7UL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_3 (0xa079667aUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_ATTRIB (0xb65b633fUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_NEXT (0xf325fb6bUL)
> +#define MAC_PCS_XXV_LT_TABLE_READBACK_3_PREV (0x4be86302UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0 (0xa935a75dUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_ATTRIB (0x86fe53feUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_NEXT (0xe6774ef1UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_PREV (0x5ebad698UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_SEL (0x155c6463UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_TABLE_ADDR
> (0xa7ff653fUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_UPDATE
> (0xc44806baUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1 (0xde3297cbUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_ATTRIB
> (0x4a545360UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_NEXT (0x2d2b9d54UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_PREV (0x95e6053dUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_SEL (0x283c4dd3UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_TABLE_ADDR
> (0x3c5a2950UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_UPDATE
> (0x8e20624UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2 (0x473bc671UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_ATTRIB
> (0xc4db5483UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_NEXT (0xabbfeffaUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_PREV (0x13727793UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_SEL (0x6f9c3703UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_TABLE_ADDR
> (0x4bc4fba0UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_UPDATE
> (0x866d01c7UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3 (0x303cf6e7UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_ATTRIB (0x871541dUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_NEXT (0x60e33c5fUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_PREV (0xd82ea436UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_SEL (0x52fc1eb3UL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_TABLE_ADDR
> (0xd061b7cfUL)
> +#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_UPDATE
> (0x4ac70159UL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0 (0xca36b2f7UL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0_RX_MAX_LENGTH
> (0xad9bad5fUL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1 (0xbd318261UL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1_RX_MAX_LENGTH
> (0x146076b7UL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2 (0x2438d3dbUL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2_RX_MAX_LENGTH
> (0x51d1cceUL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3 (0x533fe34dUL)
> +#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3_RX_MAX_LENGTH
> (0xbce6c726UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0 (0x5a45a21dUL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_MIN_RX_FRAME
> (0x781d8621UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_RX_MIN_LENGTH
> (0x4fca8931UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1 (0x2d42928bUL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_MIN_RX_FRAME
> (0xe5126757UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_RX_MIN_LENGTH
> (0xf63152d9UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2 (0xb44bc331UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_MIN_RX_FRAME
> (0x9973428cUL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_RX_MIN_LENGTH
> (0xe74c38a0UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3 (0xc34cf3a7UL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_MIN_RX_FRAME
> (0x47ca3faUL)
> +#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_RX_MIN_LENGTH
> (0x5eb7e348UL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_0 (0x5b190150UL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_0_MAX_LEN (0xeaa0f0bUL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_1 (0x2c1e31c6UL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_1_MAX_LEN (0x19d11b48UL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_2 (0xb517607cUL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_2_MAX_LEN (0x205c278dUL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_3 (0xc21050eaUL)
> +#define MAC_PCS_XXV_MAX_PKT_LEN_3_MAX_LEN (0x372733ceUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0 (0xbee01144UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_MAIN (0x553fe7f6UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_POST (0xb09d461fUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_PRE (0x490c9445UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ENABLE (0x1dc34d8aUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_INIT (0xff042d41UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_PRESET (0xc23c618aUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_RX_READY (0x5f37a378UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1 (0xc9e721d2UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_MAIN (0xbafd8cc8UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_POST (0x5f5f2d21UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_PRE (0x5e778006UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ENABLE (0xd1694d14UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_INIT (0x3458fee4UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_PRESET (0xe966114UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_RX_READY (0xb0f5c846UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2 (0x50ee7068UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_MAIN (0x51ca37cbUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_POST (0xb4689622UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_PRE (0x67fabcc3UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ENABLE (0x5fe64af7UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_INIT (0xb2cc8c4aUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_PRESET (0x801966f7UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_RX_READY (0x5bc27345UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3 (0x27e940feUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_MAIN (0xbe085cf5UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_POST (0x5baafd1cUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_PRE (0x7081a880UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ENABLE (0x934c4a69UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_INIT (0x79905fefUL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_PRESET (0x4cb36669UL)
> +#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_RX_READY (0xb400187bUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0 (0xf12740e1UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_MAIN_STA
> (0xc1d6a542UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_POST_STA (0xfe4a543bUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_PRE_STA (0x3d4a42d1UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1 (0x86207077UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_MAIN_STA
> (0x2e14ce7cUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_POST_STA (0x11883f05UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_PRE_STA (0x2a315692UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2 (0x1f2921cdUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_MAIN_STA
> (0xc523757fUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_POST_STA (0xfabf8406UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_PRE_STA (0x13bc6a57UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3 (0x682e115bUL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_MAIN_STA
> (0x2ae11e41UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_POST_STA (0x157def38UL)
> +#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_PRE_STA (0x4c77e14UL)
> +#define MAC_PCS_XXV_RST_0 (0xbc41405eUL)
> +#define MAC_PCS_XXV_RST_0_MAC_PCS (0xb425c579UL)
> +#define MAC_PCS_XXV_RST_1 (0xcb4670c8UL)
> +#define MAC_PCS_XXV_RST_1_MAC_PCS (0xa35ed13aUL)
> +#define MAC_PCS_XXV_RST_2 (0x524f2172UL)
> +#define MAC_PCS_XXV_RST_2_MAC_PCS (0x9ad3edffUL)
> +#define MAC_PCS_XXV_RST_3 (0x254811e4UL)
> +#define MAC_PCS_XXV_RST_3_MAC_PCS (0x8da8f9bcUL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0 (0x1fc33ac9UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0_RS_FEC_CCW_CNT
> (0x63c40291UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1 (0x68c40a5fUL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1_RS_FEC_CCW_CNT
> (0xcdac9300UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2 (0xf1cd5be5UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2_RS_FEC_CCW_CNT
> (0xe46427f2UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3 (0x86ca6b73UL)
> +#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3_RS_FEC_CCW_CNT
> (0x4a0cb663UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0 (0x7de9885UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0_CONSORTIUM (0xaf731a5bUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_CORRECTION
> (0x574a1223UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_ENABLE (0xc8d960dUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_IEEE_ERROR_INDICATION
> (0xe5a25113UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_INDICATION
> (0x2487d64cUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1 (0x70d9a813UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1_CONSORTIUM (0x34d65634UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_CORRECTION
> (0x80a8927bUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_ENABLE (0xb5764de5UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_IEEE_ERROR_INDICATION
> (0xd9c2b21bUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_INDICATION
> (0xf3655614UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2 (0xe9d0f9a9UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2_CONSORTIUM (0x434884c4UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_CORRECTION
> (0x23fe14d2UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_ENABLE (0xa40b279cUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_IEEE_ERROR_INDICATION
> (0x9d639703UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_INDICATION
> (0x5033d0bdUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3 (0x9ed7c93fUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3_CONSORTIUM (0xd8edc8abUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_CORRECTION
> (0xf41c948aUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_ENABLE (0x1df0fc74UL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_IEEE_ERROR_INDICATION
> (0xa103740bUL)
> +#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_INDICATION
> (0x87d150e5UL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0 (0x8ef05d51UL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0_RS_FEC_ERR_CNT
> (0x61cba0edUL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1 (0xf9f76dc7UL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1_RS_FEC_ERR_CNT
> (0xcfa3317cUL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2 (0x60fe3c7dUL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2_RS_FEC_ERR_CNT
> (0xe66b858eUL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3 (0x17f90cebUL)
> +#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3_RS_FEC_ERR_CNT
> (0x4803141fUL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0 (0xc0190132UL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0_RS_FEC_UCW_CNT
> (0xa89c8608UL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1 (0xb71e31a4UL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1_RS_FEC_UCW_CNT
> (0x6f41799UL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2 (0x2e17601eUL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2_RS_FEC_UCW_CNT
> (0x2f3ca36bUL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3 (0x59105088UL)
> +#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3_RS_FEC_UCW_CNT
> (0x815432faUL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_0 (0x53d3df14UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_0_COUNT (0xf1329ab1UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_1 (0x24d4ef82UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_1_COUNT (0x57459105UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_2 (0xbdddbe38UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_2_COUNT (0x66ad8b98UL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_3 (0xcada8eaeUL)
> +#define MAC_PCS_XXV_RX_BAD_FCS_3_COUNT (0xc0da802cUL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_0 (0x88c256ceUL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_0_COUNT (0x97189d30UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_1 (0xffc56658UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_1_COUNT (0x316f9684UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_2 (0x66cc37e2UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_2_COUNT (0x878c19UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_3 (0x11cb0774UL)
> +#define MAC_PCS_XXV_RX_FRAMING_ERROR_3_COUNT (0xa6f087adUL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_0 (0xdb9d71adUL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_0_COUNT (0x970d9ccdUL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_1 (0xac9a413bUL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_1_COUNT (0x317a9779UL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_2 (0x35931081UL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_2_COUNT (0x928de4UL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_3 (0x42942017UL)
> +#define MAC_PCS_XXV_RX_GOOD_BYTES_3_COUNT (0xa6e58650UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_0 (0xa1a32858UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_0_COUNT (0xaec3dbc9UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_1 (0xd6a418ceUL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_1_COUNT (0x8b4d07dUL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_2 (0x4fad4974UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_2_COUNT (0x395ccae0UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_3 (0x38aa79e2UL)
> +#define MAC_PCS_XXV_RX_GOOD_PACKETS_3_COUNT (0x9f2bc154UL)
> +#define MAC_PCS_XXV_RX_LATENCY_0 (0x636577a2UL)
> +#define MAC_PCS_XXV_RX_LATENCY_0_LATENCY (0x5bc360b1UL)
> +#define MAC_PCS_XXV_RX_LATENCY_1 (0x14624734UL)
> +#define MAC_PCS_XXV_RX_LATENCY_1_LATENCY (0x4cb874f2UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_0 (0x566d6603UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_0_COUNT (0x95039b5UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_1 (0x216a5695UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_1_COUNT (0xaf273201UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_2 (0xb863072fUL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_2_COUNT (0x9ecf289cUL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_3 (0xcf6437b9UL)
> +#define MAC_PCS_XXV_RX_TOTAL_BYTES_3_COUNT (0x38b82328UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0 (0x12f4b108UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0_COUNT (0xef99e10dUL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1 (0x65f3819eUL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1_COUNT (0x49eeeab9UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2 (0xfcfad024UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2_COUNT (0x7806f024UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3 (0x8bfde0b2UL)
> +#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3_COUNT (0xde71fb90UL)
> +#define MAC_PCS_XXV_SUB_RST_0 (0xcea66ca4UL)
> +#define MAC_PCS_XXV_SUB_RST_0_AN_LT (0xe868535cUL)
> +#define MAC_PCS_XXV_SUB_RST_0_QPLL (0xf8a38742UL)
> +#define MAC_PCS_XXV_SUB_RST_0_RX_BUF (0x56ef70f8UL)
> +#define MAC_PCS_XXV_SUB_RST_0_RX_GT_DATA (0x233f5adcUL)
> +#define MAC_PCS_XXV_SUB_RST_0_RX_MAC_PCS (0x1d82003eUL)
> +#define MAC_PCS_XXV_SUB_RST_0_RX_PCS (0x380856daUL)
> +#define MAC_PCS_XXV_SUB_RST_0_RX_PMA (0x55320a1cUL)
> +#define MAC_PCS_XXV_SUB_RST_0_SPEED_CTRL (0xa1c62fb2UL)
> +#define MAC_PCS_XXV_SUB_RST_0_TX_GT_DATA (0x2e212a9bUL)
> +#define MAC_PCS_XXV_SUB_RST_0_TX_MAC_PCS (0x109c7079UL)
> +#define MAC_PCS_XXV_SUB_RST_0_TX_PCS (0xee51b5c7UL)
> +#define MAC_PCS_XXV_SUB_RST_0_TX_PMA (0x836be901UL)
> +#define MAC_PCS_XXV_SUB_RST_1 (0xb9a15c32UL)
> +#define MAC_PCS_XXV_SUB_RST_1_AN_LT (0x4e1f58e8UL)
> +#define MAC_PCS_XXV_SUB_RST_1_QPLL (0x33ff54e7UL)
> +#define MAC_PCS_XXV_SUB_RST_1_RX_BUF (0x9a457066UL)
> +#define MAC_PCS_XXV_SUB_RST_1_RX_GT_DATA (0xb89a16b3UL)
> +#define MAC_PCS_XXV_SUB_RST_1_RX_MAC_PCS (0x86274c51UL)
> +#define MAC_PCS_XXV_SUB_RST_1_RX_PCS (0xf4a25644UL)
> +#define MAC_PCS_XXV_SUB_RST_1_RX_PMA (0x99980a82UL)
> +#define MAC_PCS_XXV_SUB_RST_1_SPEED_CTRL (0x3a6363ddUL)
> +#define MAC_PCS_XXV_SUB_RST_1_TX_GT_DATA (0xb58466f4UL)
> +#define MAC_PCS_XXV_SUB_RST_1_TX_MAC_PCS (0x8b393c16UL)
> +#define MAC_PCS_XXV_SUB_RST_1_TX_PCS (0x22fbb559UL)
> +#define MAC_PCS_XXV_SUB_RST_1_TX_PMA (0x4fc1e99fUL)
> +#define MAC_PCS_XXV_SUB_RST_2 (0x20a80d88UL)
> +#define MAC_PCS_XXV_SUB_RST_2_AN_LT (0x7ff74275UL)
> +#define MAC_PCS_XXV_SUB_RST_2_QPLL (0xb56b2649UL)
> +#define MAC_PCS_XXV_SUB_RST_2_RX_BUF (0x14ca7785UL)
> +#define MAC_PCS_XXV_SUB_RST_2_RX_GT_DATA (0xcf04c443UL)
> +#define MAC_PCS_XXV_SUB_RST_2_RX_MAC_PCS (0xf1b99ea1UL)
> +#define MAC_PCS_XXV_SUB_RST_2_RX_PCS (0x7a2d51a7UL)
> +#define MAC_PCS_XXV_SUB_RST_2_RX_PMA (0x17170d61UL)
> +#define MAC_PCS_XXV_SUB_RST_2_SPEED_CTRL (0x4dfdb12dUL)
> +#define MAC_PCS_XXV_SUB_RST_2_TX_GT_DATA (0xc21ab404UL)
> +#define MAC_PCS_XXV_SUB_RST_2_TX_MAC_PCS (0xfca7eee6UL)
> +#define MAC_PCS_XXV_SUB_RST_2_TX_PCS (0xac74b2baUL)
> +#define MAC_PCS_XXV_SUB_RST_2_TX_PMA (0xc14eee7cUL)
> +#define MAC_PCS_XXV_SUB_RST_3 (0x57af3d1eUL)
> +#define MAC_PCS_XXV_SUB_RST_3_AN_LT (0xd98049c1UL)
> +#define MAC_PCS_XXV_SUB_RST_3_QPLL (0x7e37f5ecUL)
> +#define MAC_PCS_XXV_SUB_RST_3_RX_BUF (0xd860771bUL)
> +#define MAC_PCS_XXV_SUB_RST_3_RX_GT_DATA (0x54a1882cUL)
> +#define MAC_PCS_XXV_SUB_RST_3_RX_MAC_PCS (0x6a1cd2ceUL)
> +#define MAC_PCS_XXV_SUB_RST_3_RX_PCS (0xb6875139UL)
> +#define MAC_PCS_XXV_SUB_RST_3_RX_PMA (0xdbbd0dffUL)
> +#define MAC_PCS_XXV_SUB_RST_3_SPEED_CTRL (0xd658fd42UL)
> +#define MAC_PCS_XXV_SUB_RST_3_TX_GT_DATA (0x59bff86bUL)
> +#define MAC_PCS_XXV_SUB_RST_3_TX_MAC_PCS (0x6702a289UL)
> +#define MAC_PCS_XXV_SUB_RST_3_TX_PCS (0x60deb224UL)
> +#define MAC_PCS_XXV_SUB_RST_3_TX_PMA (0xde4eee2UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_0 (0x31f1d051UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_0_QPLL_LOCK (0x2c39cf3dUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_RX_RST
> (0xa1223741UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_TX_RST (0x777bd45cUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_1 (0x46f6e0c7UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_1_QPLL_LOCK (0xedb710fdUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_RX_RST (0x7cb4eec4UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_TX_RST (0xaaed0dd9UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_2 (0xdfffb17dUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_2_QPLL_LOCK (0x745576fcUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_RX_RST (0xc17e820aUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_TX_RST
> (0x17276117UL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_3 (0xa8f881ebUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_3_QPLL_LOCK (0xb5dba93cUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_RX_RST (0x1ce85b8fUL)
> +#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_TX_RST (0xcab1b892UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_0 (0xa5e7869aUL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_0_RX_DLY (0x825d4fb7UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_0_TX_DLY (0x5404acaaUL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_1 (0xd2e0b60cUL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_1_RX_DLY (0x4ef74f29UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_1_TX_DLY (0x98aeac34UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_2 (0x4be9e7b6UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_2_RX_DLY (0xc07848caUL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_2_TX_DLY (0x1621abd7UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_3 (0x3ceed720UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_3_RX_DLY (0xcd24854UL)
> +#define MAC_PCS_XXV_TIMESTAMP_COMP_3_TX_DLY (0xda8bab49UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_0 (0xbcee7af4UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_0_COUNT (0xff4e2634UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_1 (0xcbe94a62UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_1_COUNT (0x59392d80UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_2 (0x52e01bd8UL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_2_COUNT (0x68d1371dUL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_3 (0x25e72b4eUL)
> +#define MAC_PCS_XXV_TX_BAD_FCS_3_COUNT (0xcea63ca9UL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_0 (0x64717f86UL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_0_COUNT (0x17fd90f4UL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_1 (0x13764f10UL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_1_COUNT (0xb18a9b40UL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_2 (0x8a7f1eaaUL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_2_COUNT (0x806281ddUL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_3 (0xfd782e3cUL)
> +#define MAC_PCS_XXV_TX_FRAME_ERROR_3_COUNT (0x26158a69UL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_0 (0xf967a55fUL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_0_COUNT (0x6130990bUL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_1 (0x8e6095c9UL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_1_COUNT (0xc74792bfUL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_2 (0x1769c473UL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_2_COUNT (0xf6af8822UL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_3 (0x606ef4e5UL)
> +#define MAC_PCS_XXV_TX_GOOD_BYTES_3_COUNT (0x50d88396UL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_0 (0x6979f50UL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_0_COUNT (0x4309a9b3UL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_1 (0x7190afc6UL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_1_COUNT (0xe57ea207UL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_2 (0xe899fe7cUL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_2_COUNT (0xd496b89aUL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_3 (0x9f9eceeaUL)
> +#define MAC_PCS_XXV_TX_GOOD_PACKETS_3_COUNT (0x72e1b32eUL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_0 (0x5fc0fe7UL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_0_COUNT (0x7ba16335UL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_1 (0x72fb3f71UL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_1_COUNT (0xddd66881UL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_2 (0xebf26ecbUL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_2_COUNT (0xec3e721cUL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_3 (0x9cf55e5dUL)
> +#define MAC_PCS_XXV_TX_TOTAL_BYTES_3_COUNT (0x4a4979a8UL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0 (0x1c880d8dUL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0_COUNT (0x5fa4b35dUL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1 (0x6b8f3d1bUL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1_COUNT (0xf9d3b8e9UL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2 (0xf2866ca1UL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2_COUNT (0xc83ba274UL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3 (0x85815c37UL)
> +#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3_COUNT (0x6e4ca9c0UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _PCS_XXV_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_r= x.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
> new file mode 100644
> index 0000000000..e8dcf06144
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
> @@ -0,0 +1,90 @@
> +/*
> + * nthw_fpga_reg_defs_mac_rx.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_RX_
> +#define _NTHW_FPGA_REG_DEFS_MAC_RX_
> +
> +/* MAC_RX */
> +#define NTHW_MOD_MAC_RX (0x6347b490UL)
> +#define MAC_RX_BAD_FCS (0xca07f618UL)
> +#define MAC_RX_BAD_FCS_COUNT (0x11d5ba0eUL)
> +#define MAC_RX_BAD_PREAMBLE (0x8a9e1895UL)
> +#define MAC_RX_BAD_PREAMBLE_COUNT (0x94cde758UL)
> +#define MAC_RX_BAD_SFD (0x2e4ee601UL)
> +#define MAC_RX_BAD_SFD_COUNT (0x1d1b1114UL)
> +#define MAC_RX_BROADCAST (0xc601a955UL)
> +#define MAC_RX_BROADCAST_COUNT (0x34215d1eUL)
> +#define MAC_RX_FRAGMENT (0x5363b736UL)
> +#define MAC_RX_FRAGMENT_COUNT (0xf664c9aUL)
> +#define MAC_RX_INRANGEERR (0x8c827f5aUL)
> +#define MAC_RX_INRANGEERR_COUNT (0x412374f1UL)
> +#define MAC_RX_JABBER (0x2e057c27UL)
> +#define MAC_RX_JABBER_COUNT (0x1b4d17b2UL)
> +#define MAC_RX_MULTICAST (0x891e2299UL)
> +#define MAC_RX_MULTICAST_COUNT (0xe7818f66UL)
> +#define MAC_RX_OVERSIZE (0x7630fc85UL)
> +#define MAC_RX_OVERSIZE_COUNT (0x5b25605eUL)
> +#define MAC_RX_PACKET_1024_1518_BYTES (0xe525d34dUL)
> +#define MAC_RX_PACKET_1024_1518_BYTES_COUNT (0x7d9de556UL)
> +#define MAC_RX_PACKET_128_255_BYTES (0xcd8a378bUL)
> +#define MAC_RX_PACKET_128_255_BYTES_COUNT (0x442e67ebUL)
> +#define MAC_RX_PACKET_1519_1522_BYTES (0x681c88adUL)
> +#define MAC_RX_PACKET_1519_1522_BYTES_COUNT (0x40d43ff6UL)
> +#define MAC_RX_PACKET_1523_1548_BYTES (0x5dfe5acbUL)
> +#define MAC_RX_PACKET_1523_1548_BYTES_COUNT (0x339a5140UL)
> +#define MAC_RX_PACKET_1549_2047_BYTES (0x40c4e3d2UL)
> +#define MAC_RX_PACKET_1549_2047_BYTES_COUNT (0x81fc4090UL)
> +#define MAC_RX_PACKET_2048_4095_BYTES (0x4f3bdf16UL)
> +#define MAC_RX_PACKET_2048_4095_BYTES_COUNT (0xba0d0879UL)
> +#define MAC_RX_PACKET_256_511_BYTES (0x42cadeecUL)
> +#define MAC_RX_PACKET_256_511_BYTES_COUNT (0x566f927UL)
> +#define MAC_RX_PACKET_4096_8191_BYTES (0x3ad4685aUL)
> +#define MAC_RX_PACKET_4096_8191_BYTES_COUNT (0xbc56edbfUL)
> +#define MAC_RX_PACKET_512_1023_BYTES (0xa88bf6b7UL)
> +#define MAC_RX_PACKET_512_1023_BYTES_COUNT (0x15430ff8UL)
> +#define MAC_RX_PACKET_64_BYTES (0x35e6dcadUL)
> +#define MAC_RX_PACKET_64_BYTES_COUNT (0xf81dddUL)
> +#define MAC_RX_PACKET_65_127_BYTES (0x262f6a19UL)
> +#define MAC_RX_PACKET_65_127_BYTES_COUNT (0xb010dafUL)
> +#define MAC_RX_PACKET_8192_9215_BYTES (0x10cd73eaUL)
> +#define MAC_RX_PACKET_8192_9215_BYTES_COUNT (0xa967837aUL)
> +#define MAC_RX_PACKET_BAD_FCS (0x4cb8b34cUL)
> +#define MAC_RX_PACKET_BAD_FCS_COUNT (0xb6701e28UL)
> +#define MAC_RX_PACKET_LARGE (0xc11f49c8UL)
> +#define MAC_RX_PACKET_LARGE_COUNT (0x884a975UL)
> +#define MAC_RX_PACKET_SMALL (0xed318a65UL)
> +#define MAC_RX_PACKET_SMALL_COUNT (0x72095ec7UL)
> +#define MAC_RX_STOMPED_FCS (0xedbc183eUL)
> +#define MAC_RX_STOMPED_FCS_COUNT (0xa0b5bc65UL)
> +#define MAC_RX_TOOLONG (0x61da6643UL)
> +#define MAC_RX_TOOLONG_COUNT (0xa789b6efUL)
> +#define MAC_RX_TOTAL_BYTES (0x831313e2UL)
> +#define MAC_RX_TOTAL_BYTES_COUNT (0xe5d8be59UL)
> +#define MAC_RX_TOTAL_GOOD_BYTES (0x912c2d1cUL)
> +#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (0x63bb5f3eUL)
> +#define MAC_RX_TOTAL_GOOD_PACKETS (0xfbb4f497UL)
> +#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (0xae9d21b0UL)
> +#define MAC_RX_TOTAL_PACKETS (0xb0ea3730UL)
> +#define MAC_RX_TOTAL_PACKETS_COUNT (0x532c885dUL)
> +#define MAC_RX_TRUNCATED (0x28c83348UL)
> +#define MAC_RX_TRUNCATED_COUNT (0xb8e62fccUL)
> +#define MAC_RX_UNDERSIZE (0xb6fa4bdbUL)
> +#define MAC_RX_UNDERSIZE_COUNT (0x471945ffUL)
> +#define MAC_RX_UNICAST (0xaa9e5b6cUL)
> +#define MAC_RX_UNICAST_COUNT (0x814ecbf0UL)
> +#define MAC_RX_VLAN (0x2f200d8dUL)
> +#define MAC_RX_VLAN_COUNT (0xf156d97eUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _RX_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
> new file mode 100644
> index 0000000000..0b36ffbea1
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h > @@ -0,0 +1,42 @@
> +/*
> + * nthw_fpga_reg_defs_mac_tfg.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_TFG_
> +#define _NTHW_FPGA_REG_DEFS_MAC_TFG_
> +
> +/* MAC_TFG */
> +#define NTHW_MOD_MAC_TFG (0x1a1aac23UL)
> +#define MAC_TFG_TFG_ADDR (0x90a59c6bUL)
> +#define MAC_TFG_TFG_ADDR_ADR (0x3ad0b041UL)
> +#define MAC_TFG_TFG_ADDR_RDENA (0x32d2aecdUL)
> +#define MAC_TFG_TFG_ADDR_RD_DONE (0x29dc9218UL)
> +#define MAC_TFG_TFG_CTRL (0xc01d7f24UL)
> +#define MAC_TFG_TFG_CTRL_ID_ENA (0x226f646eUL)
> +#define MAC_TFG_TFG_CTRL_ID_POS (0xd22045fcUL)
> +#define MAC_TFG_TFG_CTRL_RESTART (0xfd4f999eUL)
> +#define MAC_TFG_TFG_CTRL_TG_ACT (0x5fd3d81UL)
> +#define MAC_TFG_TFG_CTRL_TG_ENA (0xda870ffbUL)
> +#define MAC_TFG_TFG_CTRL_TIME_MODE (0xa96c2409UL)
> +#define MAC_TFG_TFG_CTRL_WRAP (0xdb215a6eUL)
> +#define MAC_TFG_TFG_DATA (0x6fccfd3dUL)
> +#define MAC_TFG_TFG_DATA_GAP (0x936a9790UL)
> +#define MAC_TFG_TFG_DATA_ID (0x82eba4faUL)
> +#define MAC_TFG_TFG_DATA_LENGTH (0x6db149f2UL)
> +#define MAC_TFG_TFG_FRAME_HDR (0x632d9e2cUL)
> +#define MAC_TFG_TFG_FRAME_HDR_HDR (0xe7a88ec1UL)
> +#define MAC_TFG_TFG_REPETITION (0xde9617ebUL)
> +#define MAC_TFG_TFG_REPETITION_CNT (0x4fee626dUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _TFG_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_t= x.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
> new file mode 100644
> index 0000000000..d05556bce4
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
> @@ -0,0 +1,70 @@
> +/*
> + * nthw_fpga_reg_defs_mac_tx.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MAC_TX_
> +#define _NTHW_FPGA_REG_DEFS_MAC_TX_
> +
> +/* MAC_TX */
> +#define NTHW_MOD_MAC_TX (0x351d1316UL)
> +#define MAC_TX_BAD_FCS (0xc719865fUL)
> +#define MAC_TX_BAD_FCS_COUNT (0x4244d3eaUL)
> +#define MAC_TX_BROADCAST (0x293c0cb5UL)
> +#define MAC_TX_BROADCAST_COUNT (0x3a5de19bUL)
> +#define MAC_TX_FRAME_ERRORS (0xaa9219a8UL)
> +#define MAC_TX_FRAME_ERRORS_COUNT (0x63d223c3UL)
> +#define MAC_TX_MULTICAST (0x66238779UL)
> +#define MAC_TX_MULTICAST_COUNT (0xe9fd33e3UL)
> +#define MAC_TX_PACKET_1024_1518_BYTES (0x8efebfebUL)
> +#define MAC_TX_PACKET_1024_1518_BYTES_COUNT (0x5bcd97b0UL)
> +#define MAC_TX_PACKET_128_255_BYTES (0x204045f1UL)
> +#define MAC_TX_PACKET_128_255_BYTES_COUNT (0xd54fb772UL)
> +#define MAC_TX_PACKET_1519_1522_BYTES (0x3c7e40bUL)
> +#define MAC_TX_PACKET_1519_1522_BYTES_COUNT (0x66844d10UL)
> +#define MAC_TX_PACKET_1523_1548_BYTES (0x3625366dUL)
> +#define MAC_TX_PACKET_1523_1548_BYTES_COUNT (0x15ca23a6UL)
> +#define MAC_TX_PACKET_1549_2047_BYTES (0x2b1f8f74UL)
> +#define MAC_TX_PACKET_1549_2047_BYTES_COUNT (0xa7ac3276UL)
> +#define MAC_TX_PACKET_2048_4095_BYTES (0x24e0b3b0UL)
> +#define MAC_TX_PACKET_2048_4095_BYTES_COUNT (0x9c5d7a9fUL)
> +#define MAC_TX_PACKET_256_511_BYTES (0xaf00ac96UL)
> +#define MAC_TX_PACKET_256_511_BYTES_COUNT (0x940729beUL)
> +#define MAC_TX_PACKET_4096_8191_BYTES (0x510f04fcUL)
> +#define MAC_TX_PACKET_4096_8191_BYTES_COUNT (0x9a069f59UL)
> +#define MAC_TX_PACKET_512_1023_BYTES (0x18b6a4e7UL)
> +#define MAC_TX_PACKET_512_1023_BYTES_COUNT (0x9c0145c8UL)
> +#define MAC_TX_PACKET_64_BYTES (0x3b9a6028UL)
> +#define MAC_TX_PACKET_64_BYTES_COUNT (0xb0c54f8dUL)
> +#define MAC_TX_PACKET_65_127_BYTES (0x54de3099UL)
> +#define MAC_TX_PACKET_65_127_BYTES_COUNT (0xebd03e1UL)
> +#define MAC_TX_PACKET_8192_9215_BYTES (0x7b161f4cUL)
> +#define MAC_TX_PACKET_8192_9215_BYTES_COUNT (0x8f37f19cUL)
> +#define MAC_TX_PACKET_LARGE (0xe3e59d3aUL)
> +#define MAC_TX_PACKET_LARGE_COUNT (0xfeb9acb3UL)
> +#define MAC_TX_PACKET_SMALL (0xcfcb5e97UL)
> +#define MAC_TX_PACKET_SMALL_COUNT (0x84345b01UL)
> +#define MAC_TX_TOTAL_BYTES (0x7bd15854UL)
> +#define MAC_TX_TOTAL_BYTES_COUNT (0x61fb238cUL)
> +#define MAC_TX_TOTAL_GOOD_BYTES (0xcf0260fUL)
> +#define MAC_TX_TOTAL_GOOD_BYTES_COUNT (0x8603398UL)
> +#define MAC_TX_TOTAL_GOOD_PACKETS (0xd89f151UL)
> +#define MAC_TX_TOTAL_GOOD_PACKETS_COUNT (0x12c47c77UL)
> +#define MAC_TX_TOTAL_PACKETS (0xe37b5ed4UL)
> +#define MAC_TX_TOTAL_PACKETS_COUNT (0x21ddd2ddUL)
> +#define MAC_TX_UNICAST (0xa7802b2bUL)
> +#define MAC_TX_UNICAST_COUNT (0xd2dfa214UL)
> +#define MAC_TX_VLAN (0x4cf038b7UL)
> +#define MAC_TX_VLAN_COUNT (0x51b306a3UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MAC= _TX_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
> new file mode 100644
> index 0000000000..fdc74e56bd
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
> @@ -0,0 +1,42 @@
> +/*
> + * nthw_fpga_reg_defs_msk.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_MSK_
> +#define _NTHW_FPGA_REG_DEFS_MSK_
> +
> +/* MSK */
> +#define NTHW_MOD_MSK (0xcfd617eeUL)
> +#define MSK_RCP_CTRL (0xc1c33daaUL)
> +#define MSK_RCP_CTRL_ADR (0x350a336UL)
> +#define MSK_RCP_CTRL_CNT (0x13583ae7UL)
> +#define MSK_RCP_DATA (0x6e12bfb3UL)
> +#define MSK_RCP_DATA_MASK_DYN0 (0x9d269a43UL)
> +#define MSK_RCP_DATA_MASK_DYN1 (0xea21aad5UL)
> +#define MSK_RCP_DATA_MASK_DYN2 (0x7328fb6fUL)
> +#define MSK_RCP_DATA_MASK_DYN3 (0x42fcbf9UL)
> +#define MSK_RCP_DATA_MASK_EN0 (0x487b2e09UL)
> +#define MSK_RCP_DATA_MASK_EN1 (0x3f7c1e9fUL)
> +#define MSK_RCP_DATA_MASK_EN2 (0xa6754f25UL)
> +#define MSK_RCP_DATA_MASK_EN3 (0xd1727fb3UL)
> +#define MSK_RCP_DATA_MASK_LEN0 (0x4daee8b8UL)
> +#define MSK_RCP_DATA_MASK_LEN1 (0x3aa9d82eUL)
> +#define MSK_RCP_DATA_MASK_LEN2 (0xa3a08994UL)
> +#define MSK_RCP_DATA_MASK_LEN3 (0xd4a7b902UL)
> +#define MSK_RCP_DATA_MASK_OFS0 (0xa2319513UL)
> +#define MSK_RCP_DATA_MASK_OFS1 (0xd536a585UL)
> +#define MSK_RCP_DATA_MASK_OFS2 (0x4c3ff43fUL)
> +#define MSK_RCP_DATA_MASK_OFS3 (0x3b38c4a9UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_MSK= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
> new file mode 100644
> index 0000000000..c21a1b20c3
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h<= br> > @@ -0,0 +1,37 @@
> +/*
> + * nthw_fpga_reg_defs_pci_rd_tg.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
> +#define _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
> +
> +/* PCI_RD_TG */
> +#define NTHW_MOD_PCI_RD_TG (0x9ad9eed2UL)
> +#define PCI_RD_TG_TG_CTRL (0x5a899dc8UL)
> +#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (0x66c70bffUL)
> +#define PCI_RD_TG_TG_RDADDR (0x39e1af65UL)
> +#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (0xf6b0ecd1UL)
> +#define PCI_RD_TG_TG_RDDATA0 (0x4bcd36f9UL)
> +#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (0xa4479fe8UL)
> +#define PCI_RD_TG_TG_RDDATA1 (0x3cca066fUL)
> +#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (0x6b3563dfUL)
> +#define PCI_RD_TG_TG_RDDATA2 (0xa5c357d5UL)
> +#define PCI_RD_TG_TG_RDDATA2_REQ_HID (0x5dab4bc3UL)
> +#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (0x85dd8d92UL)
> +#define PCI_RD_TG_TG_RDDATA2_WAIT (0x85ba70b2UL)
> +#define PCI_RD_TG_TG_RDDATA2_WRAP (0x546e238aUL)
> +#define PCI_RD_TG_TG_RD_RUN (0xd6542f54UL)
> +#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (0xcdc6e166UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCI= _RD_TG_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_t= a.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
> new file mode 100644
> index 0000000000..43dacda70a
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
> @@ -0,0 +1,32 @@
> +/*
> + * nthw_fpga_reg_defs_pci_ta.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCI_TA_
> +#define _NTHW_FPGA_REG_DEFS_PCI_TA_
> +
> +/* PCI_TA */
> +#define NTHW_MOD_PCI_TA (0xfb431997UL)
> +#define PCI_TA_CONTROL (0xa707df59UL)
> +#define PCI_TA_CONTROL_ENABLE (0x87cdcc9aUL)
> +#define PCI_TA_LENGTH_ERROR (0x8648b862UL)
> +#define PCI_TA_LENGTH_ERROR_AMOUNT (0x8774bd63UL)
> +#define PCI_TA_PACKET_BAD (0xaaa256d4UL)
> +#define PCI_TA_PACKET_BAD_AMOUNT (0x601f72f3UL)
> +#define PCI_TA_PACKET_GOOD (0xfc13da6cUL)
> +#define PCI_TA_PACKET_GOOD_AMOUNT (0xd936d64dUL)
> +#define PCI_TA_PAYLOAD_ERROR (0x69d7a09bUL)
> +#define PCI_TA_PAYLOAD_ERROR_AMOUNT (0x445da330UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCI= _TA_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
> new file mode 100644
> index 0000000000..491152bb97
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h<= br> > @@ -0,0 +1,40 @@
> +/*
> + * nthw_fpga_reg_defs_pci_wr_tg.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
> +#define _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
> +
> +/* PCI_WR_TG */
> +#define NTHW_MOD_PCI_WR_TG (0x274b69e1UL)
> +#define PCI_WR_TG_TG_CTRL (0xa48366c7UL)
> +#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (0x9983a3e8UL)
> +#define PCI_WR_TG_TG_SEQ (0x8b3e0bd6UL)
> +#define PCI_WR_TG_TG_SEQ_SEQUENCE (0xebf1c760UL)
> +#define PCI_WR_TG_TG_WRADDR (0x2b7b95a5UL)
> +#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (0x5fdc2aceUL)
> +#define PCI_WR_TG_TG_WRDATA0 (0xd0bb6e73UL)
> +#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (0x97cb1c89UL)
> +#define PCI_WR_TG_TG_WRDATA1 (0xa7bc5ee5UL)
> +#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (0x51b3be92UL)
> +#define PCI_WR_TG_TG_WRDATA2 (0x3eb50f5fUL)
> +#define PCI_WR_TG_TG_WRDATA2_INC_MODE (0x5be5577UL)
> +#define PCI_WR_TG_TG_WRDATA2_REQ_HID (0xf4c78ddcUL)
> +#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (0x87ceca1UL)
> +#define PCI_WR_TG_TG_WRDATA2_WAIT (0xb29cb8ffUL)
> +#define PCI_WR_TG_TG_WRDATA2_WRAP (0x6348ebc7UL)
> +#define PCI_WR_TG_TG_WR_RUN (0xc4ce1594UL)
> +#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (0xe83c0a22UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCI= _WR_TG_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3= .h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
> new file mode 100644
> index 0000000000..4b8bf53cd9
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
> @@ -0,0 +1,281 @@
> +/*
> + * nthw_fpga_reg_defs_pcie3.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_
> +#define _NTHW_FPGA_REG_DEFS_PCIE3_
> +
> +/* PCIE3 */
> +#define NTHW_MOD_PCIE3 (0xfbc48c18UL)
> +#define PCIE3_BUILD_SEED (0x7a6457c5UL)
> +#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL)
> +#define PCIE3_BUILD_TIME (0x51772c86UL)
> +#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL)
> +#define PCIE3_CONFIG (0xe7ef0d51UL)
> +#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL)
> +#define PCIE3_CONFIG_MAX_READ (0x2943f801UL)
> +#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL)
> +#define PCIE3_CONTROL (0x935935d4UL)
> +#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL)
> +#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL)
> +#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL)
> +#define PCIE3_CORESPEED (0x5cbe0925UL)
> +#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL)
> +#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL)
> +#define PCIE3_DRP_COMMON (0xffd331a2UL)
> +#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL)
> +#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL)
> +#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL)
> +#define PCIE3_DRP_COMMON_WR (0xbe76449eUL)
> +#define PCIE3_DRP_DATE (0xeaae0e97UL)
> +#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL)
> +#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL)
> +#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL)
> +#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL)
> +#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL)
> +#define PCIE3_INT_CLR (0xcde216faUL)
> +#define PCIE3_INT_CLR_AVR (0x1982c8eUL)
> +#define PCIE3_INT_CLR_FHM (0x5d9e0821UL)
> +#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL)
> +#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL)
> +#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL)
> +#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL)
> +#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL)
> +#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL)
> +#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL)
> +#define PCIE3_INT_CLR_INT_15 (0xbda934afUL)
> +#define PCIE3_INT_CLR_INT_16 (0x24a06515UL)
> +#define PCIE3_INT_CLR_INT_17 (0x53a75583UL)
> +#define PCIE3_INT_CLR_INT_18 (0xc3184812UL)
> +#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL)
> +#define PCIE3_INT_CLR_INT_2 (0x82a59259UL)
> +#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL)
> +#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL)
> +#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL)
> +#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL)
> +#define PCIE3_INT_CLR_INT_24 (0xe18357faUL)
> +#define PCIE3_INT_CLR_INT_25 (0x9684676cUL)
> +#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL)
> +#define PCIE3_INT_CLR_INT_27 (0x788a0640UL)
> +#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL)
> +#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL)
> +#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL)
> +#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL)
> +#define PCIE3_INT_CLR_INT_31 (0x88f29234UL)
> +#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL)
> +#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL)
> +#define PCIE3_INT_CLR_INT_6 (0x85c85640UL)
> +#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL)
> +#define PCIE3_INT_CLR_INT_8 (0x62707b47UL)
> +#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL)
> +#define PCIE3_INT_CLR_PORT (0x4f57e46eUL)
> +#define PCIE3_INT_CLR_PPS (0x3d2172d9UL)
> +#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL)
> +#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL)
> +#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL)
> +#define PCIE3_INT_CLR_STA (0xa8b278ccUL)
> +#define PCIE3_INT_CLR_TIMER (0x696afaafUL)
> +#define PCIE3_INT_FORC (0x55ea48d8UL)
> +#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL)
> +#define PCIE3_INT_FORC_FHM (0x78afd50UL)
> +#define PCIE3_INT_FORC_INT_0 (0x9758e745UL)
> +#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL)
> +#define PCIE3_INT_FORC_INT_10 (0xebe10398UL)
> +#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL)
> +#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL)
> +#define PCIE3_INT_FORC_INT_13 (0x72e85222UL)
> +#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL)
> +#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL)
> +#define PCIE3_INT_FORC_INT_16 (0x282a6adUL)
> +#define PCIE3_INT_FORC_INT_17 (0x7585963bUL)
> +#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL)
> +#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL)
> +#define PCIE3_INT_FORC_INT_2 (0x79568669UL)
> +#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL)
> +#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL)
> +#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL)
> +#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL)
> +#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL)
> +#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL)
> +#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL)
> +#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL)
> +#define PCIE3_INT_FORC_INT_28 (0xce17d869UL)
> +#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL)
> +#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL)
> +#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL)
> +#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL)
> +#define PCIE3_INT_FORC_INT_4 (0x9035235cUL)
> +#define PCIE3_INT_FORC_INT_5 (0xe73213caUL)
> +#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL)
> +#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL)
> +#define PCIE3_INT_FORC_INT_8 (0x99836f77UL)
> +#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL)
> +#define PCIE3_INT_FORC_PORT (0x680fb131UL)
> +#define PCIE3_INT_FORC_PPS (0x673587a8UL)
> +#define PCIE3_INT_FORC_QSPI (0x94bf821bUL)
> +#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL)
> +#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL)
> +#define PCIE3_INT_FORC_STA (0xf2a68dbdUL)
> +#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL)
> +#define PCIE3_INT_MASK (0x9fb55ba0UL)
> +#define PCIE3_INT_MASK_AVR (0xadf52690UL)
> +#define PCIE3_INT_MASK_FHM (0xf1f3023fUL)
> +#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL)
> +#define PCIE3_INT_MASK_IIC1 (0xf2696667UL)
> +#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL)
> +#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL)
> +#define PCIE3_INT_MASK_IIC4 (0x820392e8UL)
> +#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL)
> +#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL)
> +#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL)
> +#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL)
> +#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL)
> +#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL)
> +#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL)
> +#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL)
> +#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL)
> +#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL)
> +#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL)
> +#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL)
> +#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL)
> +#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL)
> +#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL)
> +#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL)
> +#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL)
> +#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL)
> +#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL)
> +#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL)
> +#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL)
> +#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL)
> +#define PCIE3_INT_MASK_INT_28 (0x37616068UL)
> +#define PCIE3_INT_MASK_INT_29 (0x406650feUL)
> +#define PCIE3_INT_MASK_INT_3 (0xc136d863UL)
> +#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL)
> +#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL)
> +#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL)
> +#define PCIE3_INT_MASK_INT_5 (0x28557d56UL)
> +#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL)
> +#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL)
> +#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL)
> +#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL)
> +#define PCIE3_INT_MASK_PORT (0xb5f4b407UL)
> +#define PCIE3_INT_MASK_PPS (0x914c78c7UL)
> +#define PCIE3_INT_MASK_QSPI (0x4944872dUL)
> +#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL)
> +#define PCIE3_INT_MASK_SPIS (0x8769a19dUL)
> +#define PCIE3_INT_MASK_STA (0x4df72d2UL)
> +#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL)
> +#define PCIE3_LAT_CTRL (0x5c509767UL)
> +#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL)
> +#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL)
> +#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL)
> +#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL)
> +#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL)
> +#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL)
> +#define PCIE3_LAT_MAX (0x316931d1UL)
> +#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL)
> +#define PCIE3_LAT_RAMADR (0x745612a7UL)
> +#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL)
> +#define PCIE3_LAT_RAMDATA (0xfc506b8dUL)
> +#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL)
> +#define PCIE3_LINK_STATUS (0xab303a44UL)
> +#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL)
> +#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL)
> +#define PCIE3_MARKADR_LSB (0xbf66115UL)
> +#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL)
> +#define PCIE3_MARKADR_MSB (0xa340b22UL)
> +#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL)
> +#define PCIE3_PB_INTERVAL (0x6d0029bfUL)
> +#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL)
> +#define PCIE3_PB_MAX_RD (0x14d4cfd0UL)
> +#define PCIE3_PB_MAX_RD_PB (0xafae2778UL)
> +#define PCIE3_PB_MAX_WR (0x9d778ec4UL)
> +#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL)
> +#define PCIE3_PCIE_CTRL (0x6a657a79UL)
> +#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL)
> +#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL)
> +#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL)
> +#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL)
> +#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL)
> +#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL)
> +#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL)
> +#define PCIE3_PCI_TEST0 (0x9035b95dUL)
> +#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL)
> +#define PCIE3_PCI_TEST1 (0xe73289cbUL)
> +#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL)
> +#define PCIE3_PCI_TEST2 (0x7e3bd871UL)
> +#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL)
> +#define PCIE3_PCI_TEST3 (0x93ce8e7UL)
> +#define PCIE3_PCI_TEST3_DATA (0x777d7216UL)
> +#define PCIE3_PROD_ID_EX (0x8611a98cUL)
> +#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL)
> +#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL)
> +#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL)
> +#define PCIE3_PROD_ID_LSB (0x427df3d7UL)
> +#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL)
> +#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL)
> +#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL)
> +#define PCIE3_PROD_ID_MSB (0x43bf99e0UL)
> +#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL)
> +#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL)
> +#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL)
> +#define PCIE3_RESET_CTRL (0xcc9a6c8bUL)
> +#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL)
> +#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL)
> +#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL)
> +#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL)
> +#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL)
> +#define PCIE3_SAMPLE_TIME (0x6c2ab747UL)
> +#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL)
> +#define PCIE3_STATUS (0x48654731UL)
> +#define PCIE3_STATUS_RD_ERR (0x153789c6UL)
> +#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL)
> +#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL)
> +#define PCIE3_STATUS0 (0xa54dba5cUL)
> +#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL)
> +#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL)
> +#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL)
> +#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL)
> +#define PCIE3_STATUS0_UR_FMT (0x5724146cUL)
> +#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL)
> +#define PCIE3_STATUS0_UR_REG (0x6cd416UL)
> +#define PCIE3_STAT_CTRL (0xdef3e1d7UL)
> +#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL)
> +#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL)
> +#define PCIE3_STAT_REFCLK (0xa4423dd2UL)
> +#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL)
> +#define PCIE3_STAT_RQ_RDY (0x3ab72682UL)
> +#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL)
> +#define PCIE3_STAT_RQ_VLD (0x9661688fUL)
> +#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL)
> +#define PCIE3_STAT_RX (0xf2a8e7a1UL)
> +#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL)
> +#define PCIE3_STAT_TX (0xa4f24027UL)
> +#define PCIE3_STAT_TX_COUNTER (0x80908563UL)
> +#define PCIE3_TEST0 (0xa0e404f1UL)
> +#define PCIE3_TEST0_DATA (0xf82b8d9cUL)
> +#define PCIE3_TEST1 (0xd7e33467UL)
> +#define PCIE3_TEST1_DATA (0x33775e39UL)
> +#define PCIE3_TEST2_DATA (0x7151e5e8UL)
> +#define PCIE3_TEST3_DATA (0xba0d364dUL)
> +#define PCIE3_UUID0 (0x96ee4e29UL)
> +#define PCIE3_UUID0_UUID0 (0x459d36b3UL)
> +#define PCIE3_UUID1 (0xe1e97ebfUL)
> +#define PCIE3_UUID1_UUID1 (0x94ed0d91UL)
> +#define PCIE3_UUID2 (0x78e02f05UL)
> +#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL)
> +#define PCIE3_UUID3 (0xfe71f93UL)
> +#define PCIE3_UUID3_UUID3 (0xed7c7d94UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCI= E3_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > new file mode 100644
> index 0000000000..34c10c3bea
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h > @@ -0,0 +1,19 @@
> +/*
> + * nthw_fpga_reg_defs_pcm_nt400dxx.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_
> +#define _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCM= _NT400DXX_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h
> new file mode 100644
> index 0000000000..a3447de224
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01 > .h
> @@ -0,0 +1,19 @@
> +/*
> + * nthw_fpga_reg_defs_pcm_nt50b01_01.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_
> +#define _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCM= _NT50B01_01_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
> new file mode 100644
> index 0000000000..61efcee4e8
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
> @@ -0,0 +1,92 @@
> +/*
> + * nthw_fpga_reg_defs_pcs.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCS_
> +#define _NTHW_FPGA_REG_DEFS_PCS_
> +
> +/* PCS */
> +#define NTHW_MOD_PCS (0x8286adcaUL)
> +#define PCS_BER_COUNT (0x2e91033bUL)
> +#define PCS_BER_COUNT_CNT (0x8069b483UL)
> +#define PCS_BIP_COUNT (0xeea1075dUL)
> +#define PCS_BIP_COUNT_CNT (0xdd0f40c3UL)
> +#define PCS_BLOCK_LOCK (0xcca988f2UL)
> +#define PCS_BLOCK_LOCK_LOCK (0x8372ac9aUL)
> +#define PCS_BLOCK_LOCK_LATCH (0x4b4db873UL)
> +#define PCS_BLOCK_LOCK_LATCH_LATCH_LOCK (0x3e50cbe6UL)
> +#define PCS_BLOCK_LOCK_ST (0x8f218598UL)
> +#define PCS_BLOCK_LOCK_ST_LATCH_STATE (0xc29c506eUL)
> +#define PCS_DDR3_STATUS (0xe0963286UL)
> +#define PCS_DDR3_STATUS_CALIB_DONE (0x9a8acba0UL)
> +#define PCS_DRP_CONFIG (0x7a62f621UL)
> +#define PCS_DRP_CONFIG_DRP_ADR (0x77a5e19eUL)
> +#define PCS_DRP_CONFIG_DRP_DI (0xae7df08dUL)
> +#define PCS_DRP_CONFIG_DRP_EN (0x2902546fUL)
> +#define PCS_DRP_CONFIG_DRP_WREN (0x3cfccbafUL)
> +#define PCS_DRP_DATA (0x1d57f9a0UL)
> +#define PCS_DRP_DATA_DRP_DO (0x5719fe67UL)
> +#define PCS_DRP_DATA_DRP_RDY (0xe86bedd1UL)
> +#define PCS_FSM_DONE (0xfb93f7e4UL)
> +#define PCS_FSM_DONE_RX_RST_DONE (0x57e501cbUL)
> +#define PCS_FSM_DONE_TX_RST_DONE (0xbf50cb88UL)
> +#define PCS_GTH_CONFIG (0x4d111e36UL)
> +#define PCS_GTH_CONFIG_EYE_SCAN_RST (0xf26521beUL)
> +#define PCS_GTH_CONFIG_EYE_SCAN_TRIG (0xcd5499e3UL)
> +#define PCS_GTH_CONFIG_GT_LOOP (0x8f0a29e8UL)
> +#define PCS_GTH_CONFIG_GT_LPM_EN (0xca43244fUL)
> +#define PCS_GTH_CONFIG_GT_MRST (0xc252e7eaUL)
> +#define PCS_GTH_CONFIG_GT_RX_RST (0xd0dd4c8fUL)
> +#define PCS_GTH_CONFIG_GT_SOFT_RST (0xf4291740UL)
> +#define PCS_GTH_CONFIG_GT_TX_RST (0x684af92UL)
> +#define PCS_GTH_CONFIG_RX_MONITOR_SEL (0xdb170715UL)
> +#define PCS_GTH_CONFIG_RX_PCS_RST (0x63f7aa78UL)
> +#define PCS_GTH_CONFIG_RX_USER_RDY (0x25431f5fUL)
> +#define PCS_GTH_CONFIG_TX_PCS_RST (0x6ee9da3fUL)
> +#define PCS_GTH_CONFIG_TX_USER_RDYU (0xddcfe06cUL)
> +#define PCS_GTH_CONTROL (0x40253f3cUL)
> +#define PCS_GTH_CONTROL_CPLL_LOCK (0xa7d1c749UL)
> +#define PCS_GTH_CONTROL_CPLL_REFCLK_LOST (0x5d089cc9UL)
> +#define PCS_GTH_CONTROL_RX_BUF_RST (0x44d16a8eUL)
> +#define PCS_GTH_TX_TUNING (0x712f49ceUL)
> +#define PCS_GTH_TX_TUNING_DIFF_CTRL (0x28d64209UL)
> +#define PCS_GTH_TX_TUNING_POST_CURSOR (0x1baff955UL)
> +#define PCS_GTH_TX_TUNING_PRE_CURSOR (0xc6ba5499UL)
> +#define PCS_LANE_LOCK (0xfe988167UL)
> +#define PCS_LANE_LOCK_LOCK (0x2f4590a6UL)
> +#define PCS_LANE_LOCK_LATCH (0x648ef3c8UL)
> +#define PCS_LANE_LOCK_LATCH_LATCH_LOCK (0x85bc8101UL)
> +#define PCS_LANE_LOCK_ST (0xf4e544c2UL)
> +#define PCS_LANE_LOCK_ST_LATCH_STATE (0x7755e260UL)
> +#define PCS_LANE_MAPPING (0xabb9e1caUL)
> +#define PCS_LANE_MAPPING_LANE (0x3a1fc704UL)
> +#define PCS_LANE_OFFSET (0xbebd9e39UL)
> +#define PCS_LANE_OFFSET_DIFF (0xac1cb16eUL)
> +#define PCS_PCS_CONFIG (0x61138662UL)
> +#define PCS_PCS_CONFIG_BER_RST (0x1ed2e4bfUL)
> +#define PCS_PCS_CONFIG_BIP_RST (0x13d077a4UL)
> +#define PCS_PCS_CONFIG_LANE_ADDR (0xc48ed818UL)
> +#define PCS_PCS_CONFIG_LANE_BLOCK_CLR (0x6b249b8UL)
> +#define PCS_PCS_CONFIG_TIME_OFFSET_RX (0xc19c631dUL)
> +#define PCS_PCS_CONFIG_TXRX_LOOP (0x5c917a55UL)
> +#define PCS_PCS_STATUS (0xce99cc02UL)
> +#define PCS_PCS_STATUS_ALIGN (0x5376e136UL)
> +#define PCS_PCS_STATUS_DELAY_ERR (0x3c8d9a55UL)
> +#define PCS_PCS_STATUS_FIFO_DELAY (0x4e88e0e6UL)
> +#define PCS_PCS_STATUS_HI_BER (0xe72cf1f6UL)
> +#define PCS_POLARITY (0x206611d1UL)
> +#define PCS_POLARITY_RX_POL (0xcfec2b60UL)
> +#define PCS_POLARITY_TX_POL (0x19b5c87dUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCS= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs10= 0.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
> new file mode 100644
> index 0000000000..7c5b076eff
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
> @@ -0,0 +1,90 @@
> +/*
> + * nthw_fpga_reg_defs_pcs100.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PCS100_
> +#define _NTHW_FPGA_REG_DEFS_PCS100_
> +
> +/* PCS100 */
> +#define NTHW_MOD_PCS100 (0xa03da74fUL)
> +#define PCS100_BER_COUNT (0x682da9a4UL)
> +#define PCS100_BER_COUNT_CNT (0x666a98d6UL)
> +#define PCS100_BIP_COUNT (0xa81dadc2UL)
> +#define PCS100_BIP_COUNT_CNT (0x3b0c6c96UL)
> +#define PCS100_BLOCK_LOCK (0xac5fba8dUL)
> +#define PCS100_BLOCK_LOCK_LOCK (0x76668f6bUL)
> +#define PCS100_BLOCK_LOCK_LATCH (0x81026edaUL)
> +#define PCS100_BLOCK_LOCK_LATCH_LATCH_LOCK (0xc22270cUL)
> +#define PCS100_BLOCK_LOCK_ST (0x6922a9cdUL)
> +#define PCS100_BLOCK_LOCK_ST_LATCH_STATE (0x48d92300UL)
> +#define PCS100_DDR3_STATUS (0x204ca819UL)
> +#define PCS100_DDR3_STATUS_CALIB_DONE (0xfd635a82UL)
> +#define PCS100_DRP_CONFIG (0x1a94c45eUL)
> +#define PCS100_DRP_CONFIG_DRP_ADR (0x67d05b90UL)
> +#define PCS100_DRP_CONFIG_DRP_DI (0x1bda417UL)
> +#define PCS100_DRP_CONFIG_DRP_EN (0x86c200f5UL)
> +#define PCS100_DRP_CONFIG_DRP_WREN (0xdb549312UL)
> +#define PCS100_DRP_DATA (0xc8431f0fUL)
> +#define PCS100_DRP_DATA_DRP_DO (0xa20ddd96UL)
> +#define PCS100_DRP_DATA_DRP_RDY (0x22243b78UL)
> +#define PCS100_FSM_DONE (0x2e87114bUL)
> +#define PCS100_FSM_DONE_RX_RST_DONE (0xe2d266a2UL)
> +#define PCS100_FSM_DONE_TX_RST_DONE (0xa67ace1UL)
> +#define PCS100_GTH_CONFIG (0x2de72c49UL)
> +#define PCS100_GTH_CONFIG_EYE_SCAN_RST (0x276289cbUL)
> +#define PCS100_GTH_CONFIG_EYE_SCAN_TRIG (0xedee1bf8UL)
> +#define PCS100_GTH_CONFIG_GT_LOOP (0x9f7f93e6UL)
> +#define PCS100_GTH_CONFIG_GT_MRST (0xd2275de4UL)
> +#define PCS100_GTH_CONFIG_GT_RX_RST (0x65ea2be6UL)
> +#define PCS100_GTH_CONFIG_GT_SOFT_RST (0x93c08662UL)
> +#define PCS100_GTH_CONFIG_GT_TX_RST (0xb3b3c8fbUL)
> +#define PCS100_GTH_CONFIG_RX_MONITOR_SEL (0x5152747bUL)
> +#define PCS100_GTH_CONFIG_RX_PCS_RST (0x572c44e3UL)
> +#define PCS100_GTH_CONFIG_RX_USER_RDY (0x42aa8e7dUL)
> +#define PCS100_GTH_CONFIG_TX_PCS_RST (0x5a3234a4UL)
> +#define PCS100_GTH_CONFIG_TX_USER_RDYU (0x8c84819UL)
> +#define PCS100_GTH_CONTROL (0x80ffa5a3UL)
> +#define PCS100_GTH_CONTROL_CPLL_LOCK (0x930a29d2UL)
> +#define PCS100_GTH_CONTROL_CPLL_REFCLK_LOST (0x1de5e543UL)
> +#define PCS100_GTH_CONTROL_QPLL_LOCK (0x113c4325UL)
> +#define PCS100_GTH_CONTROL_QPLL_REFCLK_LOST (0x7c62febeUL)
> +#define PCS100_GTH_CONTROL_RX_BUF_RST (0x2338fbacUL)
> +#define PCS100_GTH_TX_TUNING (0x972c659bUL)
> +#define PCS100_GTH_TX_TUNING_DIFF_CTRL (0xfdd1ea7cUL)
> +#define PCS100_GTH_TX_TUNING_POST_CURSOR (0x91ea8a3bUL)
> +#define PCS100_GTH_TX_TUNING_PRE_CURSOR (0xe600d682UL)
> +#define PCS100_LANE_LOCK (0xb8242bf8UL)
> +#define PCS100_LANE_LOCK_LOCK (0x34a236f1UL)
> +#define PCS100_LANE_LOCK_LATCH (0x919ad039UL)
> +#define PCS100_LANE_LOCK_LATCH_LATCH_LOCK (0x2f3c882dUL)
> +#define PCS100_LANE_LOCK_ST (0x9495108dUL)
> +#define PCS100_LANE_LOCK_ST_LATCH_STATE (0x57ef607bUL)
> +#define PCS100_LANE_MAPPING (0xcbc9b585UL)
> +#define PCS100_LANE_MAPPING_LANE (0x95df939eUL)
> +#define PCS100_LANE_OFFSET (0x7e6704a6UL)
> +#define PCS100_LANE_OFFSET_DIFF (0x665367c7UL)
> +#define PCS100_PCS_CONFIG (0x1e5b41dUL)
> +#define PCS100_PCS_CONFIG_BER_RST (0xea75eb1UL)
> +#define PCS100_PCS_CONFIG_BIP_RST (0x3a5cdaaUL)
> +#define PCS100_PCS_CONFIG_LANE_ADDR (0x71b9bf71UL)
> +#define PCS100_PCS_CONFIG_LANE_BLOCK_CLR (0x8cf73ad6UL)
> +#define PCS100_PCS_CONFIG_TIME_OFFSET_RX (0x4bd91073UL)
> +#define PCS100_PCS_CONFIG_TXRX_LOOP (0xe9a61d3cUL)
> +#define PCS100_PCS_STATUS (0xae6ffe7dUL)
> +#define PCS100_PCS_STATUS_ALIGN (0x9939379fUL)
> +#define PCS100_PCS_STATUS_DELAY_ERR (0x89bafd3cUL)
> +#define PCS100_PCS_STATUS_FIFO_DELAY (0x7a530e7dUL)
> +#define PCS100_PCS_STATUS_HI_BER (0x48eca56cUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PCS= 100_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
> new file mode 100644
> index 0000000000..03d7c89dda
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
> @@ -0,0 +1,47 @@
> +/*
> + * nthw_fpga_reg_defs_pdb.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PDB_
> +#define _NTHW_FPGA_REG_DEFS_PDB_
> +
> +/* PDB */
> +#define NTHW_MOD_PDB (0xa7771bffUL)
> +#define PDB_CONFIG (0xf73771edUL)
> +#define PDB_CONFIG_PORT_OFS (0xb5b30335UL)
> +#define PDB_CONFIG_TS_FORMAT (0x7013d8aUL)
> +#define PDB_RCP_CTRL (0x28ac2b3aUL)
> +#define PDB_RCP_CTRL_ADR (0x9d08b0e4UL)
> +#define PDB_RCP_CTRL_CNT (0x8d002935UL)
> +#define PDB_RCP_DATA (0x877da923UL)
> +#define PDB_RCP_DATA_ALIGN (0xe802afb8UL)
> +#define PDB_RCP_DATA_CRC_OVERWRITE (0x4847dc0aUL)
> +#define PDB_RCP_DATA_DESCRIPTOR (0x46cb76faUL)
> +#define PDB_RCP_DATA_DESC_LEN (0xf467e85bUL)
> +#define PDB_RCP_DATA_DUPLICATE_BIT (0xaeb59507UL)
> +#define PDB_RCP_DATA_DUPLICATE_EN (0xbab03efeUL)
> +#define PDB_RCP_DATA_IP_PROT_TNL (0xec892325UL)
> +#define PDB_RCP_DATA_OFS0_DYN (0xcef3786aUL)
> +#define PDB_RCP_DATA_OFS0_REL (0xde219bd9UL)
> +#define PDB_RCP_DATA_OFS1_DYN (0xf39351daUL)
> +#define PDB_RCP_DATA_OFS1_REL (0xe341b269UL)
> +#define PDB_RCP_DATA_OFS2_DYN (0xb4332b0aUL)
> +#define PDB_RCP_DATA_OFS2_REL (0xa4e1c8b9UL)
> +#define PDB_RCP_DATA_PCAP_KEEP_FCS (0x90bc735eUL)
> +#define PDB_RCP_DATA_PPC_HSH (0xac10e9f8UL)
> +#define PDB_RCP_DATA_TX_IGNORE (0x14c556dcUL)
> +#define PDB_RCP_DATA_TX_NOW (0x479cb22cUL)
> +#define PDB_RCP_DATA_TX_PORT (0x412a5ed8UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PDB= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
> new file mode 100644
> index 0000000000..8c48d5c2e5
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
> @@ -0,0 +1,48 @@
> +/*
> + * nthw_fpga_reg_defs_pdi.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PDI_
> +#define _NTHW_FPGA_REG_DEFS_PDI_
> +
> +/* PDI */
> +#define NTHW_MOD_PDI (0x30a5c277UL)
> +#define PDI_CR (0x9d6d02a8UL)
> +#define PDI_CR_EN (0x7a6160dUL)
> +#define PDI_CR_PARITY (0xaed85250UL)
> +#define PDI_CR_RST (0x26b77922UL)
> +#define PDI_CR_RXRST (0xe1aedb39UL)
> +#define PDI_CR_STOP (0x78eaf29eUL)
> +#define PDI_CR_TXRST (0x6eee2e99UL)
> +#define PDI_DRR (0x8ab88f08UL)
> +#define PDI_DRR_DRR (0x157e17dfUL)
> +#define PDI_DTR (0xdce2288eUL)
> +#define PDI_DTR_DTR (0x957d5344UL)
> +#define PDI_PRE (0x12440163UL)
> +#define PDI_PRE_PRE (0xccd36afbUL)
> +#define PDI_SR (0xd7af10f9UL)
> +#define PDI_SR_DISABLE_BUSY (0xd8936666UL)
> +#define PDI_SR_DONE (0xb64f984dUL)
> +#define PDI_SR_ENABLE_BUSY (0xee39b4e3UL)
> +#define PDI_SR_FRAME_ERR (0x7c7b177dUL)
> +#define PDI_SR_OVERRUN_ERR (0x4093d29dUL)
> +#define PDI_SR_PARITY_ERR (0xa12e1293UL)
> +#define PDI_SR_RXLVL (0xe5b6087bUL)
> +#define PDI_SR_RX_BUSY (0xeb248de4UL)
> +#define PDI_SR_TXLVL (0x6af6fddbUL)
> +#define PDI_SR_TX_BUSY (0x88f4b8deUL)
> +#define PDI_SRR (0x93d13afdUL)
> +#define PDI_SRR_RST (0x5fd4fe29UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PDI= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
> new file mode 100644
> index 0000000000..a2fbb01da8
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h > @@ -0,0 +1,196 @@
> +/*
> + * nthw_fpga_reg_defs_phy_tile.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PHY_TILE_
> +#define _NTHW_FPGA_REG_DEFS_PHY_TILE_
> +
> +/* PHY_TILE */
> +#define NTHW_MOD_PHY_TILE (0x4e0aef6eUL)
> +#define PHY_TILE_DR_CFG_STATUS (0x252aff33UL)
> +#define PHY_TILE_DR_CFG_STATUS_CURR_PROFILE_ID (0x98db7e13UL)
> +#define PHY_TILE_DR_CFG_STATUS_ERROR (0x594c35e7UL)
> +#define PHY_TILE_DR_CFG_STATUS_IN_PROGRESS (0x62cdc29fUL)
> +#define PHY_TILE_DYN_RECONFIG_BASE (0xda7abd93UL)
> +#define PHY_TILE_DYN_RECONFIG_BASE_BUSY (0x3b97f6c6UL)
> +#define PHY_TILE_DYN_RECONFIG_BASE_CMD (0xf6b609f6UL)
> +#define PHY_TILE_DYN_RECONFIG_BASE_PTR (0x87020896UL)
> +#define PHY_TILE_DYN_RECONFIG_DATA (0xb73db091UL)
> +#define PHY_TILE_DYN_RECONFIG_DATA_DATA (0x74d2a935UL)
> +#define PHY_TILE_LINK_SUMMARY_0 (0x2e6c2bb2UL)
> +#define PHY_TILE_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT
> (0x658fa4f2UL)
> +#define PHY_TILE_LINK_SUMMARY_0_LH_REMOTE_FAULT (0x12c794faUL)
> +#define PHY_TILE_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE
> (0x99e0ad8bUL)
> +#define PHY_TILE_LINK_SUMMARY_0_LINK_DOWN_CNT (0x7c6a63a9UL)
> +#define PHY_TILE_LINK_SUMMARY_0_LL_PHY_LINK_STATE (0x694563dcUL)
> +#define PHY_TILE_LINK_SUMMARY_0_LL_RX_AM_LOCK (0xc958731bUL)
> +#define PHY_TILE_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (0x1ae5c634UL)
> +#define PHY_TILE_LINK_SUMMARY_0_NT_PHY_LINK_STATE (0x284d52caUL)
> +#define PHY_TILE_LINK_SUMMARY_1 (0x596b1b24UL)
> +#define PHY_TILE_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT
> (0xc00434fcUL)
> +#define PHY_TILE_LINK_SUMMARY_1_LH_REMOTE_FAULT (0x95615fb9UL)
> +#define PHY_TILE_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE
> (0xf76cb6caUL)
> +#define PHY_TILE_LINK_SUMMARY_1_LINK_DOWN_CNT (0xc591b841UL)
> +#define PHY_TILE_LINK_SUMMARY_1_LL_PHY_LINK_STATE (0xbea7e384UL)
> +#define PHY_TILE_LINK_SUMMARY_1_LL_RX_AM_LOCK (0x70a3a8f3UL)
> +#define PHY_TILE_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (0xf5b770d5UL)
> +#define PHY_TILE_LINK_SUMMARY_1_NT_PHY_LINK_STATE (0xffafd292UL)
> +#define PHY_TILE_PORT_0_ETH_0_BASE (0x337c4712UL)
> +#define PHY_TILE_PORT_0_ETH_0_BASE_BUSY (0xd5fbad30UL)
> +#define PHY_TILE_PORT_0_ETH_0_BASE_CMD (0x948cd3f4UL)
> +#define PHY_TILE_PORT_0_ETH_0_BASE_PTR (0xe538d294UL)
> +#define PHY_TILE_PORT_0_ETH_0_DATA (0x5e3b4a10UL)
> +#define PHY_TILE_PORT_0_ETH_0_DATA_DATA (0x9abef2c3UL)
> +#define PHY_TILE_PORT_0_ETH_1_BASE (0xf82094b7UL)
> +#define PHY_TILE_PORT_0_ETH_1_BASE_BUSY (0x147572f0UL)
> +#define PHY_TILE_PORT_0_ETH_1_BASE_CMD (0x7b4eb8caUL)
> +#define PHY_TILE_PORT_0_ETH_1_BASE_PTR (0xafab9aaUL)
> +#define PHY_TILE_PORT_0_ETH_1_DATA (0x956799b5UL)
> +#define PHY_TILE_PORT_0_ETH_1_DATA_DATA (0x5b302d03UL)
> +#define PHY_TILE_PORT_0_ETH_2_BASE (0x7eb4e619UL)
> +#define PHY_TILE_PORT_0_ETH_2_BASE_BUSY (0x8d9714f1UL)
> +#define PHY_TILE_PORT_0_ETH_2_BASE_CMD (0x907903c9UL)
> +#define PHY_TILE_PORT_0_ETH_2_BASE_PTR (0xe1cd02a9UL)
> +#define PHY_TILE_PORT_0_ETH_2_DATA (0x13f3eb1bUL)
> +#define PHY_TILE_PORT_0_ETH_2_DATA_DATA (0xc2d24b02UL)
> +#define PHY_TILE_PORT_0_ETH_3_BASE (0xb5e835bcUL)
> +#define PHY_TILE_PORT_0_ETH_3_BASE_BUSY (0x4c19cb31UL)
> +#define PHY_TILE_PORT_0_ETH_3_BASE_CMD (0x7fbb68f7UL)
> +#define PHY_TILE_PORT_0_ETH_3_BASE_PTR (0xe0f6997UL)
> +#define PHY_TILE_PORT_0_ETH_3_DATA (0xd8af38beUL)
> +#define PHY_TILE_PORT_0_ETH_3_DATA_DATA (0x35c94c2UL)
> +#define PHY_TILE_PORT_0_XCVR_0_BASE (0x758a7765UL)
> +#define PHY_TILE_PORT_0_XCVR_0_BASE_BUSY (0x79488eafUL)
> +#define PHY_TILE_PORT_0_XCVR_0_BASE_CMD (0x9b560cdfUL)
> +#define PHY_TILE_PORT_0_XCVR_0_BASE_PTR (0xeae20dbfUL)
> +#define PHY_TILE_PORT_0_XCVR_0_DATA (0x18cd7a67UL)
> +#define PHY_TILE_PORT_0_XCVR_0_DATA_DATA (0x360dd15cUL)
> +#define PHY_TILE_PORT_0_XCVR_1_BASE (0xbed6a4c0UL)
> +#define PHY_TILE_PORT_0_XCVR_1_BASE_BUSY (0xb8c6516fUL)
> +#define PHY_TILE_PORT_0_XCVR_1_BASE_CMD (0x749467e1UL)
> +#define PHY_TILE_PORT_0_XCVR_1_BASE_PTR (0x5206681UL)
> +#define PHY_TILE_PORT_0_XCVR_1_DATA (0xd391a9c2UL)
> +#define PHY_TILE_PORT_0_XCVR_1_DATA_DATA (0xf7830e9cUL)
> +#define PHY_TILE_PORT_0_XCVR_2_BASE (0x3842d66eUL)
> +#define PHY_TILE_PORT_0_XCVR_2_BASE_BUSY (0x2124376eUL)
> +#define PHY_TILE_PORT_0_XCVR_2_BASE_CMD (0x9fa3dce2UL)
> +#define PHY_TILE_PORT_0_XCVR_2_BASE_PTR (0xee17dd82UL)
> +#define PHY_TILE_PORT_0_XCVR_2_DATA (0x5505db6cUL)
> +#define PHY_TILE_PORT_0_XCVR_2_DATA_DATA (0x6e61689dUL)
> +#define PHY_TILE_PORT_0_XCVR_3_BASE (0xf31e05cbUL)
> +#define PHY_TILE_PORT_0_XCVR_3_BASE_BUSY (0xe0aae8aeUL)
> +#define PHY_TILE_PORT_0_XCVR_3_BASE_CMD (0x7061b7dcUL)
> +#define PHY_TILE_PORT_0_XCVR_3_BASE_PTR (0x1d5b6bcUL)
> +#define PHY_TILE_PORT_0_XCVR_3_DATA (0x9e5908c9UL)
> +#define PHY_TILE_PORT_0_XCVR_3_DATA_DATA (0xafefb75dUL)
> +#define PHY_TILE_PORT_1_ETH_0_BASE (0xa8d90b7dUL)
> +#define PHY_TILE_PORT_1_ETH_0_BASE_BUSY (0x525d6673UL)
> +#define PHY_TILE_PORT_1_ETH_0_BASE_CMD (0x3ae44265UL)
> +#define PHY_TILE_PORT_1_ETH_0_BASE_PTR (0x4b504305UL)
> +#define PHY_TILE_PORT_1_ETH_0_DATA (0xc59e067fUL)
> +#define PHY_TILE_PORT_1_ETH_0_DATA_DATA (0x1d183980UL)
> +#define PHY_TILE_PORT_1_ETH_1_BASE (0x6385d8d8UL)
> +#define PHY_TILE_PORT_1_ETH_1_BASE_BUSY (0x93d3b9b3UL)
> +#define PHY_TILE_PORT_1_ETH_1_BASE_CMD (0xd526295bUL)
> +#define PHY_TILE_PORT_1_ETH_1_BASE_PTR (0xa492283bUL)
> +#define PHY_TILE_PORT_1_ETH_1_DATA (0xec2d5daUL)
> +#define PHY_TILE_PORT_1_ETH_1_DATA_DATA (0xdc96e640UL)
> +#define PHY_TILE_PORT_1_ETH_2_BASE (0xe511aa76UL)
> +#define PHY_TILE_PORT_1_ETH_2_BASE_BUSY (0xa31dfb2UL)
> +#define PHY_TILE_PORT_1_ETH_2_BASE_CMD (0x3e119258UL)
> +#define PHY_TILE_PORT_1_ETH_2_BASE_PTR (0x4fa59338UL)
> +#define PHY_TILE_PORT_1_ETH_2_DATA (0x8856a774UL)
> +#define PHY_TILE_PORT_1_ETH_2_DATA_DATA (0x45748041UL)
> +#define PHY_TILE_PORT_1_ETH_3_BASE (0x2e4d79d3UL)
> +#define PHY_TILE_PORT_1_ETH_3_BASE_BUSY (0xcbbf0072UL)
> +#define PHY_TILE_PORT_1_ETH_3_BASE_CMD (0xd1d3f966UL)
> +#define PHY_TILE_PORT_1_ETH_3_BASE_PTR (0xa067f806UL)
> +#define PHY_TILE_PORT_1_ETH_3_DATA (0x430a74d1UL)
> +#define PHY_TILE_PORT_1_ETH_3_DATA_DATA (0x84fa5f81UL)
> +#define PHY_TILE_PORT_1_XCVR_0_BASE (0xa81caee0UL)
> +#define PHY_TILE_PORT_1_XCVR_0_BASE_BUSY (0x961a384eUL)
> +#define PHY_TILE_PORT_1_XCVR_0_BASE_CMD (0x1cf0c79cUL)
> +#define PHY_TILE_PORT_1_XCVR_0_BASE_PTR (0x6d44c6fcUL)
> +#define PHY_TILE_PORT_1_XCVR_0_DATA (0xc55ba3e2UL)
> +#define PHY_TILE_PORT_1_XCVR_0_DATA_DATA (0xd95f67bdUL)
> +#define PHY_TILE_PORT_1_XCVR_1_BASE (0x63407d45UL)
> +#define PHY_TILE_PORT_1_XCVR_1_BASE_BUSY (0x5794e78eUL)
> +#define PHY_TILE_PORT_1_XCVR_1_BASE_CMD (0xf332aca2UL)
> +#define PHY_TILE_PORT_1_XCVR_1_BASE_PTR (0x8286adc2UL)
> +#define PHY_TILE_PORT_1_XCVR_1_DATA (0xe077047UL)
> +#define PHY_TILE_PORT_1_XCVR_1_DATA_DATA (0x18d1b87dUL)
> +#define PHY_TILE_PORT_1_XCVR_2_BASE (0xe5d40febUL)
> +#define PHY_TILE_PORT_1_XCVR_2_BASE_BUSY (0xce76818fUL)
> +#define PHY_TILE_PORT_1_XCVR_2_BASE_CMD (0x180517a1UL)
> +#define PHY_TILE_PORT_1_XCVR_2_BASE_PTR (0x69b116c1UL)
> +#define PHY_TILE_PORT_1_XCVR_2_DATA (0x889302e9UL)
> +#define PHY_TILE_PORT_1_XCVR_2_DATA_DATA (0x8133de7cUL)
> +#define PHY_TILE_PORT_1_XCVR_3_BASE (0x2e88dc4eUL)
> +#define PHY_TILE_PORT_1_XCVR_3_BASE_BUSY (0xff85e4fUL)
> +#define PHY_TILE_PORT_1_XCVR_3_BASE_CMD (0xf7c77c9fUL)
> +#define PHY_TILE_PORT_1_XCVR_3_BASE_PTR (0x86737dffUL)
> +#define PHY_TILE_PORT_1_XCVR_3_DATA (0x43cfd14cUL)
> +#define PHY_TILE_PORT_1_XCVR_3_DATA_DATA (0x40bd01bcUL)
> +#define PHY_TILE_PORT_COMP_0 (0xfc048a04UL)
> +#define PHY_TILE_PORT_COMP_0_RX_COMPENSATION (0xffba9733UL)
> +#define PHY_TILE_PORT_COMP_0_TX_COMPENSATION (0xdd4043c1UL)
> +#define PHY_TILE_PORT_COMP_1 (0x8b03ba92UL)
> +#define PHY_TILE_PORT_COMP_1_RX_COMPENSATION (0x781c5c70UL)
> +#define PHY_TILE_PORT_COMP_1_TX_COMPENSATION (0x5ae68882UL)
> +#define PHY_TILE_PORT_CONFIG (0x24e3ab60UL)
> +#define PHY_TILE_PORT_CONFIG_DYN_RESET (0x72b5f859UL)
> +#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_0
> (0x7e66781UL)
> +#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_1
> (0x70e15717UL)
> +#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_0 (0x33fd94c2UL)
> +#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_1 (0x44faa454UL)
> +#define PHY_TILE_PORT_CONFIG_RESET_0 (0xf0e1e1c4UL)
> +#define PHY_TILE_PORT_CONFIG_RESET_1 (0x87e6d152UL)
> +#define PHY_TILE_PORT_CONFIG_RX_RESET_0 (0x70027edeUL)
> +#define PHY_TILE_PORT_CONFIG_RX_RESET_1 (0x7054e48UL)
> +#define PHY_TILE_PORT_CONFIG_TX_RESET_0 (0x7d1c0e99UL)
> +#define PHY_TILE_PORT_CONFIG_TX_RESET_1 (0xa1b3e0fUL)
> +#define PHY_TILE_PORT_STATUS (0x8b69e100UL)
> +#define PHY_TILE_PORT_STATUS_RESET_ACK_N_0 (0x812f344UL)
> +#define PHY_TILE_PORT_STATUS_RESET_ACK_N_1 (0x7f15c3d2UL)
> +#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_0 (0x18c38950UL)
> +#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_1 (0x6fc4b9c6UL)
> +#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_0 (0x72b847a5UL)
> +#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_1 (0x5bf7733UL)
> +#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_0 (0x8557733cUL)
> +#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_1 (0xf25043aaUL)
> +#define PHY_TILE_PORT_STATUS_RX_HI_BER_0 (0xae6e5427UL)
> +#define PHY_TILE_PORT_STATUS_RX_HI_BER_1 (0xd96964b1UL)
> +#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_0 (0xb7de3d5eUL)
> +#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_1 (0xc0d90dc8UL)
> +#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_0
> (0x690e7dbcUL)
> +#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_1
> (0x1e094d2aUL)
> +#define PHY_TILE_PORT_STATUS_RX_PCS_READY_0 (0x4bb3d53cUL)
> +#define PHY_TILE_PORT_STATUS_RX_PCS_READY_1 (0x3cb4e5aaUL)
> +#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_0
> (0x4a8305e7UL)
> +#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_1
> (0x3d843571UL)
> +#define PHY_TILE_PORT_STATUS_RX_PTP_READY_0 (0xb74c7368UL)
> +#define PHY_TILE_PORT_STATUS_RX_PTP_READY_1 (0xc04b43feUL)
> +#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_0 (0x7160c5c7UL)
> +#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_1 (0x667f551UL)
> +#define PHY_TILE_PORT_STATUS_SYSTEMPLL_LOCK (0x3d44b5b8UL)
> +#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_0 (0x9a284858UL)
> +#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_1 (0xed2f78ceUL)
> +#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_0 (0x9d0d322aUL)
> +#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_1 (0xea0a02bcUL)
> +#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_0 (0x56587371UL)
> +#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_1 (0x215f43e7UL)
> +#define PHY_TILE_SCRATCH (0xcd637527UL)
> +#define PHY_TILE_SCRATCH_DATA (0x1934d873UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PHY= _TILE_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > new file mode 100644
> index 0000000000..87f255bfea
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h > @@ -0,0 +1,19 @@
> +/*
> + * nthw_fpga_reg_defs_prm_nt400dxx.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_
> +#define _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PRM= _NT400DXX_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h
> new file mode 100644
> index 0000000000..193598092d
> --- /dev/null
> +++
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01 > .h
> @@ -0,0 +1,19 @@
> +/*
> + * nthw_fpga_reg_defs_prm_nt50b01_01.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_
> +#define _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_PRM= _NT50B01_01_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
> new file mode 100644
> index 0000000000..c768109866
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
> @@ -0,0 +1,65 @@
> +/*
> + * nthw_fpga_reg_defs_qsl.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_QSL_
> +#define _NTHW_FPGA_REG_DEFS_QSL_
> +
> +/* QSL */
> +#define NTHW_MOD_QSL (0x448ed859UL)
> +#define QSL_LTX_CTRL (0xd16859aUL)
> +#define QSL_LTX_CTRL_ADR (0x56ab4bfeUL)
> +#define QSL_LTX_CTRL_CNT (0x46a3d22fUL)
> +#define QSL_LTX_DATA (0xa2c70783UL)
> +#define QSL_LTX_DATA_LR (0xbd09e686UL)
> +#define QSL_LTX_DATA_TSA (0xdc9172f1UL)
> +#define QSL_LTX_DATA_TX_PORT (0x4e838100UL)
> +#define QSL_QEN_CTRL (0xfe8ed79cUL)
> +#define QSL_QEN_CTRL_ADR (0x81d44d48UL)
> +#define QSL_QEN_CTRL_CNT (0x91dcd499UL)
> +#define QSL_QEN_DATA (0x515f5585UL)
> +#define QSL_QEN_DATA_EN (0xa1e5961UL)
> +#define QSL_QST_CTRL (0x58cd5f95UL)
> +#define QSL_QST_CTRL_ADR (0xf71b52e1UL)
> +#define QSL_QST_CTRL_CNT (0xe713cb30UL)
> +#define QSL_QST_DATA (0xf71cdd8cUL)
> +#define QSL_QST_DATA_EN (0x19406021UL)
> +#define QSL_QST_DATA_LRE (0x71626c7eUL)
> +#define QSL_QST_DATA_QEN (0xf7cd0143UL)
> +#define QSL_QST_DATA_QUEUE (0x70bc6d12UL)
> +#define QSL_QST_DATA_TCI (0x3938f18dUL)
> +#define QSL_QST_DATA_TX_PORT (0x101a63f0UL)
> +#define QSL_QST_DATA_VEN (0xf28217c6UL)
> +#define QSL_RCP_CTRL (0x2a0d86aeUL)
> +#define QSL_RCP_CTRL_ADR (0x2798e4a0UL)
> +#define QSL_RCP_CTRL_CNT (0x37907d71UL)
> +#define QSL_RCP_DATA (0x85dc04b7UL)
> +#define QSL_RCP_DATA_CAO (0x2b87358eUL)
> +#define QSL_RCP_DATA_DISCARD (0x5b3da2b8UL)
> +#define QSL_RCP_DATA_DROP (0x30f5b2fbUL)
> +#define QSL_RCP_DATA_LR (0x3f2331c2UL)
> +#define QSL_RCP_DATA_TBL_HI (0xde81892fUL)
> +#define QSL_RCP_DATA_TBL_IDX (0xa8d19ee1UL)
> +#define QSL_RCP_DATA_TBL_LO (0x538ee91eUL)
> +#define QSL_RCP_DATA_TBL_MSK (0x2ee5f375UL)
> +#define QSL_RCP_DATA_TSA (0xada2ddafUL)
> +#define QSL_RCP_DATA_VLI (0x6da78f6dUL)
> +#define QSL_UNMQ_CTRL (0xe759d3f1UL)
> +#define QSL_UNMQ_CTRL_ADR (0xe5833152UL)
> +#define QSL_UNMQ_CTRL_CNT (0xf58ba883UL)
> +#define QSL_UNMQ_DATA (0x488851e8UL)
> +#define QSL_UNMQ_DATA_DEST_QUEUE (0xef8ce959UL)
> +#define QSL_UNMQ_DATA_EN (0x36ca8378UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_QSL= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
> new file mode 100644
> index 0000000000..a34df75c14
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
> @@ -0,0 +1,89 @@
> +/*
> + * nthw_fpga_reg_defs_qspi.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_QSPI_
> +#define _NTHW_FPGA_REG_DEFS_QSPI_
> +
> +/* QSPI */
> +#define NTHW_MOD_QSPI (0x29862c6cUL)
> +#define QSPI_CR (0xef84e130UL)
> +#define QSPI_CR_CPHA (0x948dc9b4UL)
> +#define QSPI_CR_CPOL (0xa57d23ceUL)
> +#define QSPI_CR_LOOP (0xfe658b9aUL)
> +#define QSPI_CR_LSBF (0xaa231a92UL)
> +#define QSPI_CR_MSSAE (0xa5dafdd0UL)
> +#define QSPI_CR_MST (0xd32a6268UL)
> +#define QSPI_CR_MTI (0xff6d9876UL)
> +#define QSPI_CR_RXFIFO_RST (0x66004882UL)
> +#define QSPI_CR_SPE (0x840f9f23UL)
> +#define QSPI_CR_TXFIFO_RST (0x6b1e38c5UL)
> +#define QSPI_DGIE (0xe9a50117UL)
> +#define QSPI_DGIE_GIE (0xf5dbca66UL)
> +#define QSPI_DRR (0x741e7d9dUL)
> +#define QSPI_DRR_DATA_VAL (0xd7977338UL)
> +#define QSPI_DTR (0x2244da1bUL)
> +#define QSPI_DTR_DATA_VAL (0x3f22b97bUL)
> +#define QSPI_IER (0x79456a58UL)
> +#define QSPI_IER_CMD_ERR (0x80d9abaUL)
> +#define QSPI_IER_CPOL_CPHA_ERR (0x607c3883UL)
> +#define QSPI_IER_DRR_FULL (0xbb33732UL)
> +#define QSPI_IER_DRR_NEMPTY (0xf947b1acUL)
> +#define QSPI_IER_DRR_OR (0x1fe5371bUL)
> +#define QSPI_IER_DTR_EMPTY (0x8b2c2a00UL)
> +#define QSPI_IER_DTR_UR (0x20883860UL)
> +#define QSPI_IER_LOOP_ERR (0xfc3eeec4UL)
> +#define QSPI_IER_MODF (0x75955c38UL)
> +#define QSPI_IER_MSB_ERR (0xeeae77acUL)
> +#define QSPI_IER_SLV_ERR (0xbeaf1133UL)
> +#define QSPI_IER_SLV_MODF (0x3f016834UL)
> +#define QSPI_IER_SLV_MS (0x14b5e998UL)
> +#define QSPI_IER_TXFIFO_HEMPTY (0x4711acf3UL)
> +#define QSPI_ISR (0x65dddf8fUL)
> +#define QSPI_ISR_CMD_ERR (0x22bd6b15UL)
> +#define QSPI_ISR_CPOL_CPHA_ERR (0xd5ca6ff9UL)
> +#define QSPI_ISR_DRR_FULL (0x4df039baUL)
> +#define QSPI_ISR_DRR_NEMPTY (0xeda5c8abUL)
> +#define QSPI_ISR_DRR_OR (0xc03f0ce0UL)
> +#define QSPI_ISR_DTR_EMPTY (0x6809621cUL)
> +#define QSPI_ISR_DTR_UR (0xff52039bUL)
> +#define QSPI_ISR_LOOP_ERR (0xba7de04cUL)
> +#define QSPI_ISR_MODF (0x719bf5ccUL)
> +#define QSPI_ISR_MSB_ERR (0xc41e8603UL)
> +#define QSPI_ISR_SLV_ERR (0x941fe09cUL)
> +#define QSPI_ISR_SLV_MODF (0x794266bcUL)
> +#define QSPI_ISR_SLV_MS (0xcb6fd263UL)
> +#define QSPI_ISR_TXFIFO_HEMPTY (0xf2a7fb89UL)
> +#define QSPI_RX_FIFO_OCY (0xd5306ee6UL)
> +#define QSPI_RX_FIFO_OCY_OCY_VAL (0x315cad36UL)
> +#define QSPI_SR (0xa546f361UL)
> +#define QSPI_SR_CMD_ERR (0x224e01f5UL)
> +#define QSPI_SR_CPOL_CPHA_ERR (0x84dfa2deUL)
> +#define QSPI_SR_LOOP_ERR (0x1a77f15eUL)
> +#define QSPI_SR_MODF (0x36271cabUL)
> +#define QSPI_SR_MSB_ERR (0xc4edece3UL)
> +#define QSPI_SR_RXEMPTY (0xace9ac96UL)
> +#define QSPI_SR_RXFULL (0xafa43e79UL)
> +#define QSPI_SR_SLVMS (0x50619a67UL)
> +#define QSPI_SR_SLV_ERR (0x94ec8a7cUL)
> +#define QSPI_SR_TXEMPTY (0xcf3999acUL)
> +#define QSPI_SR_TXFULL (0x79fddd64UL)
> +#define QSPI_SRR (0x6d77c868UL)
> +#define QSPI_SRR_RST (0xc1528c75UL)
> +#define QSPI_SSR (0x746cf929UL)
> +#define QSPI_SSR_SEL_SLV (0x1e9e863cUL)
> +#define QSPI_TX_FIFO_OCY (0x3d85a4a5UL)
> +#define QSPI_TX_FIFO_OCY_OCY_VAL (0xac80a625UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_QSP= I_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp= .h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
> new file mode 100644
> index 0000000000..ffff2552fe
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
> @@ -0,0 +1,29 @@
> +/*
> + * nthw_fpga_reg_defs_r2drp.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_R2DRP_
> +#define _NTHW_FPGA_REG_DEFS_R2DRP_
> +
> +/* R2DRP */
> +#define NTHW_MOD_R2DRP (0x8b673fa6UL)
> +#define R2DRP_CTRL (0x6fe03b4eUL)
> +#define R2DRP_CTRL_ADR (0xd107f065UL)
> +#define R2DRP_CTRL_DATA (0x899f99f3UL)
> +#define R2DRP_CTRL_DBG_BUSY (0x96d9901aUL)
> +#define R2DRP_CTRL_DONE (0x34418a3bUL)
> +#define R2DRP_CTRL_RES (0xa17bec9bUL)
> +#define R2DRP_CTRL_WREN (0x1635422aUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_R2D= RP_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
> new file mode 100644
> index 0000000000..b4af411b47
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
> @@ -0,0 +1,72 @@
> +/*
> + * nthw_fpga_reg_defs_rac.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RAC_
> +#define _NTHW_FPGA_REG_DEFS_RAC_
> +
> +/* RAC */
> +#define NTHW_MOD_RAC (0xae830b42UL)
> +#define RAC_DBG_CTRL (0x587273e2UL)
> +#define RAC_DBG_CTRL_C (0x4fe263UL)
> +#define RAC_DBG_DATA (0xf7a3f1fbUL)
> +#define RAC_DBG_DATA_D (0x69d9305UL)
> +#define RAC_DUMMY0 (0xd8e9ed5bUL)
> +#define RAC_DUMMY1 (0xafeeddcdUL)
> +#define RAC_DUMMY2 (0x36e78c77UL)
> +#define RAC_NDM_REGISTER (0x36b9e7d0UL)
> +#define RAC_NDM_REGISTER_NDM (0xf791ef23UL)
> +#define RAC_NMB_DATA (0xc0e60c69UL)
> +#define RAC_NMB_DATA_NMB_DATA (0x21f71466UL)
> +#define RAC_NMB_RD_ADR (0x274e1df2UL)
> +#define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL)
> +#define RAC_NMB_RD_ADR_RES (0x829c7f2eUL)
> +#define RAC_NMB_STATUS (0x2070b64UL)
> +#define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL)
> +#define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL)
> +#define RAC_NMB_WR_ADR (0x9823ee63UL)
> +#define RAC_NMB_WR_ADR_ADR (0xcb13936fUL)
> +#define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL)
> +#define RAC_RAB_BUF_FREE (0x60f7f2d8UL)
> +#define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL)
> +#define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL)
> +#define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL)
> +#define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL)
> +#define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL)
> +#define RAC_RAB_BUF_USED (0x549e5008UL)
> +#define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL)
> +#define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL)
> +#define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL)
> +#define RAC_RAB_DMA_IB_HI (0x3adf4e92UL)
> +#define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL)
> +#define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL)
> +#define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL)
> +#define RAC_RAB_DMA_IB_RD (0xf443c8f4UL)
> +#define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL)
> +#define RAC_RAB_DMA_IB_WR (0x7de089e0UL)
> +#define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL)
> +#define RAC_RAB_DMA_OB_HI (0xb59fbb32UL)
> +#define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL)
> +#define RAC_RAB_DMA_OB_LO (0x3890db03UL)
> +#define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL)
> +#define RAC_RAB_DMA_OB_WR (0xf2a07c40UL)
> +#define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL)
> +#define RAC_RAB_IB_DATA (0xea524b52UL)
> +#define RAC_RAB_IB_DATA_D (0x52ecd3c6UL)
> +#define RAC_RAB_INIT (0x47d5556eUL)
> +#define RAC_RAB_INIT_RAB (0xda582a35UL)
> +#define RAC_RAB_OB_DATA (0x89827e68UL)
> +#define RAC_RAB_OB_DATA_D (0x21f6aa4cUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RAC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
> new file mode 100644
> index 0000000000..5e5a7e96d1
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
> @@ -0,0 +1,37 @@
> +/*
> + * nthw_fpga_reg_defs_rfd.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RFD_
> +#define _NTHW_FPGA_REG_DEFS_RFD_
> +
> +/* RFD */
> +#define NTHW_MOD_RFD (0x7fa60826UL)
> +#define RFD_CTRL (0x5347930aUL)
> +#define RFD_CTRL_CFP (0x38fb2beUL)
> +#define RFD_CTRL_ISL (0x2dac8d33UL)
> +#define RFD_CTRL_PWMCW (0xebb075fcUL)
> +#define RFD_MAX_FRAME_SIZE (0x8369a9a2UL)
> +#define RFD_MAX_FRAME_SIZE_MAX (0x647c0b15UL)
> +#define RFD_TNL_VLAN (0xb85aa35fUL)
> +#define RFD_TNL_VLAN_TPID0 (0xe2dfb0a4UL)
> +#define RFD_TNL_VLAN_TPID1 (0x95d88032UL)
> +#define RFD_VLAN (0xa954e6d1UL)
> +#define RFD_VLAN_TPID0 (0xab4dac41UL)
> +#define RFD_VLAN_TPID1 (0xdc4a9cd7UL)
> +#define RFD_VXLAN (0xe2207aeaUL)
> +#define RFD_VXLAN_DP0 (0xb17ca4d9UL)
> +#define RFD_VXLAN_DP1 (0xc67b944fUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RFD= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
> new file mode 100644
> index 0000000000..7857314251
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
> @@ -0,0 +1,35 @@
> +/*
> + * nthw_fpga_reg_defs_rmc.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RMC_
> +#define _NTHW_FPGA_REG_DEFS_RMC_
> +
> +/* RMC */
> +#define NTHW_MOD_RMC (0x236444eUL)
> +#define RMC_CTRL (0x4c45f748UL)
> +#define RMC_CTRL_BLOCK_KEEPA (0x5e036c8UL)
> +#define RMC_CTRL_BLOCK_MAC_PORT (0x582a6486UL)
> +#define RMC_CTRL_BLOCK_RPP_SLICE (0x58c719cUL)
> +#define RMC_CTRL_BLOCK_STATT (0xb36d5342UL)
> +#define RMC_CTRL_LAG_PHY_ODD_EVEN (0xf4613c9UL)
> +#define RMC_DBG (0x578721f2UL)
> +#define RMC_DBG_MERGE (0xebfd6f00UL)
> +#define RMC_MAC_IF (0x806bb8b0UL)
> +#define RMC_MAC_IF_ERR (0xa79e974aUL)
> +#define RMC_STATUS (0x3c415d75UL)
> +#define RMC_STATUS_DESCR_FIFO_OF (0x7be968baUL)
> +#define RMC_STATUS_SF_RAM_OF (0x1832173dUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RMC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
> new file mode 100644
> index 0000000000..a776ac1dfb
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
> @@ -0,0 +1,67 @@
> +/*
> + * nthw_fpga_reg_defs_roa.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_ROA_
> +#define _NTHW_FPGA_REG_DEFS_ROA_
> +
> +/* ROA */
> +#define NTHW_MOD_ROA (0xde0e47e0UL)
> +#define ROA_CONFIG (0xff1838eeUL)
> +#define ROA_CONFIG_FWD_CELLBUILDER_PCKS (0xd6e1416dUL)
> +#define ROA_CONFIG_FWD_NON_NORMAL_PCKS (0xc5d32d2eUL)
> +#define ROA_CONFIG_FWD_NORMAL_PCKS (0x1127f510UL)
> +#define ROA_CONFIG_FWD_RECIRCULATE (0x500dc0bcUL)
> +#define ROA_CONFIG_FWD_TXPORT0 (0xf5b61631UL)
> +#define ROA_CONFIG_FWD_TXPORT1 (0x82b126a7UL)
> +#define ROA_IGS (0xffa60f2UL)
> +#define ROA_IGS_BYTE (0x4dbd049UL)
> +#define ROA_IGS_BYTE_DROP (0x8da204f9UL)
> +#define ROA_IGS_PKT (0x68ca2b28UL)
> +#define ROA_IGS_PKT_DROP (0xac3b264eUL)
> +#define ROA_LAGCFG_CTRL (0xd5c2463cUL)
> +#define ROA_LAGCFG_CTRL_ADR (0xc01e7fc3UL)
> +#define ROA_LAGCFG_CTRL_CNT (0xd016e612UL)
> +#define ROA_LAGCFG_DATA (0x7a13c425UL)
> +#define ROA_LAGCFG_DATA_TXPHY_PORT (0xf1a085aUL)
> +#define ROA_RCC (0x6652f903UL)
> +#define ROA_RCC_BYTE (0xd293dbbcUL)
> +#define ROA_RCC_BYTE_DROP (0x739ce234UL)
> +#define ROA_RCC_PKT (0xf6623688UL)
> +#define ROA_RCC_PKT_DROP (0x46c69dd6UL)
> +#define ROA_TUNCFG_CTRL (0x4311f47bUL)
> +#define ROA_TUNCFG_CTRL_ADR (0xb37e9594UL)
> +#define ROA_TUNCFG_CTRL_CNT (0xa3760c45UL)
> +#define ROA_TUNCFG_DATA (0xecc07662UL)
> +#define ROA_TUNCFG_DATA_PUSH_TUNNEL (0x2b684608UL)
> +#define ROA_TUNCFG_DATA_RECIRCULATE (0xc0947b2fUL)
> +#define ROA_TUNCFG_DATA_RECIRC_BYPASS (0xb167919dUL)
> +#define ROA_TUNCFG_DATA_RECIRC_PORT (0xa69f21d7UL)
> +#define ROA_TUNCFG_DATA_TUN_IPCS_PRECALC (0xf78f25e0UL)
> +#define ROA_TUNCFG_DATA_TUN_IPCS_UPD (0xa524f432UL)
> +#define ROA_TUNCFG_DATA_TUN_IPTL_PRECALC (0x418432d1UL)
> +#define ROA_TUNCFG_DATA_TUN_IPTL_UPD (0x5947c642UL)
> +#define ROA_TUNCFG_DATA_TUN_IP_TYPE (0xdcb0763UL)
> +#define ROA_TUNCFG_DATA_TUN_LEN (0xf2fad7ffUL)
> +#define ROA_TUNCFG_DATA_TUN_TYPE (0xad945573UL)
> +#define ROA_TUNCFG_DATA_TUN_VLAN (0xd97b06fbUL)
> +#define ROA_TUNCFG_DATA_TUN_VXLAN_UDP_LEN_UPD (0x9b13a7cbUL)
> +#define ROA_TUNCFG_DATA_TX_LAG_IX (0x1ed24069UL)
> +#define ROA_TUNHDR_CTRL (0xdaff6a2cUL)
> +#define ROA_TUNHDR_CTRL_ADR (0x5b07c2f7UL)
> +#define ROA_TUNHDR_CTRL_CNT (0x4b0f5b26UL)
> +#define ROA_TUNHDR_DATA (0x752ee835UL)
> +#define ROA_TUNHDR_DATA_TUNNEL_HDR (0xf2fed211UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_ROA= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
> new file mode 100644
> index 0000000000..90afca44c7
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
> @@ -0,0 +1,30 @@
> +/*
> + * nthw_fpga_reg_defs_rpf.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RPF_
> +#define _NTHW_FPGA_REG_DEFS_RPF_
> +
> +/* RPF */
> +#define NTHW_MOD_RPF (0x8d30dcddUL)
> +#define RPF_CONTROL (0x7a5bdb50UL)
> +#define RPF_CONTROL_KEEP_ALIVE_EN (0x80be3ffcUL)
> +#define RPF_CONTROL_PEN (0xb23137b8UL)
> +#define RPF_CONTROL_RPP_EN (0xdb51f109UL)
> +#define RPF_CONTROL_ST_TGL_EN (0x45a6ecfaUL)
> +#define RPF_TS_SORT_PRG (0xff1d137eUL)
> +#define RPF_TS_SORT_PRG_MATURING_DELAY (0x2a38e127UL)
> +#define RPF_TS_SORT_PRG_TS_AT_EOF (0x9f27d433UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RPF= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
> new file mode 100644
> index 0000000000..5346bc673d
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
> @@ -0,0 +1,42 @@
> +/*
> + * nthw_fpga_reg_defs_rpl.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RPL_
> +#define _NTHW_FPGA_REG_DEFS_RPL_
> +
> +/* RPL */
> +#define NTHW_MOD_RPL (0x6de535c3UL)
> +#define RPL_EXT_CTRL (0x4c47804fUL)
> +#define RPL_EXT_CTRL_ADR (0xe391ddadUL)
> +#define RPL_EXT_CTRL_CNT (0xf399447cUL)
> +#define RPL_EXT_DATA (0xe3960256UL)
> +#define RPL_EXT_DATA_RPL_PTR (0xa8e4d0d9UL)
> +#define RPL_RCP_CTRL (0xc471325fUL)
> +#define RPL_RCP_CTRL_ADR (0x1f2d3a2bUL)
> +#define RPL_RCP_CTRL_CNT (0xf25a3faUL)
> +#define RPL_RCP_DATA (0x6ba0b046UL)
> +#define RPL_RCP_DATA_DYN (0xe361554fUL)
> +#define RPL_RCP_DATA_ETH_TYPE_WR (0xfc7f05c1UL)
> +#define RPL_RCP_DATA_EXT_PRIO (0xcd2ae9d1UL)
> +#define RPL_RCP_DATA_LEN (0xb0559aaUL)
> +#define RPL_RCP_DATA_OFS (0x4168d8e9UL)
> +#define RPL_RCP_DATA_RPL_PTR (0x3000a098UL)
> +#define RPL_RPL_CTRL (0xe65376ecUL)
> +#define RPL_RPL_CTRL_ADR (0x15abf987UL)
> +#define RPL_RPL_CTRL_CNT (0x5a36056UL)
> +#define RPL_RPL_DATA (0x4982f4f5UL)
> +#define RPL_RPL_DATA_VALUE (0x60951eb4UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RPL= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_l= r.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
> new file mode 100644
> index 0000000000..c8a6efb2b6
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
> @@ -0,0 +1,36 @@
> +/*
> + * nthw_fpga_reg_defs_rpp_lr.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RPP_LR_
> +#define _NTHW_FPGA_REG_DEFS_RPP_LR_
> +
> +/* RPP_LR */
> +#define NTHW_MOD_RPP_LR (0xba7f945cUL)
> +#define RPP_LR_IFR_RCP_CTRL (0xce88594UL)
> +#define RPP_LR_IFR_RCP_CTRL_ADR (0x4b4cc068UL)
> +#define RPP_LR_IFR_RCP_CTRL_CNT (0x5b4459b9UL)
> +#define RPP_LR_IFR_RCP_DATA (0xa339078dUL)
> +#define RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP (0xee1d681fUL)
> +#define RPP_LR_IFR_RCP_DATA_IPV4_EN (0xfe386131UL)
> +#define RPP_LR_IFR_RCP_DATA_IPV6_DROP (0x41f324ffUL)
> +#define RPP_LR_IFR_RCP_DATA_IPV6_EN (0x5431a9baUL)
> +#define RPP_LR_IFR_RCP_DATA_MTU (0x871a2322UL)
> +#define RPP_LR_RCP_CTRL (0xf3395d47UL)
> +#define RPP_LR_RCP_CTRL_ADR (0x4916a944UL)
> +#define RPP_LR_RCP_CTRL_CNT (0x591e3095UL)
> +#define RPP_LR_RCP_DATA (0x5ce8df5eUL)
> +#define RPP_LR_RCP_DATA_EXP (0x578ca035UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RPP= _LR_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
> new file mode 100644
> index 0000000000..0a1fecd649
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h > @@ -0,0 +1,59 @@
> +/*
> + * nthw_fpga_reg_defs_rst9563.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_RST9563_
> +#define _NTHW_FPGA_REG_DEFS_RST9563_
> +
> +/* RST9563 */
> +#define NTHW_MOD_RST9563 (0x385d6d1dUL)
> +#define RST9563_CTRL (0x8fe7585fUL)
> +#define RST9563_CTRL_PTP_MMCM_CLKSEL (0xf441b405UL)
> +#define RST9563_CTRL_TS_CLKSEL (0x210e9a78UL)
> +#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (0x304bbf3UL)
> +#define RST9563_POWER (0xdb6d3006UL)
> +#define RST9563_POWER_PU_NSEB (0x68a55de6UL)
> +#define RST9563_POWER_PU_PHY (0xdc0b7719UL)
> +#define RST9563_RST (0x366a2a03UL)
> +#define RST9563_RST_CORE_MMCM (0x4055af70UL)
> +#define RST9563_RST_DDR4 (0x367cad64UL)
> +#define RST9563_RST_MAC_RX (0x46da79e6UL)
> +#define RST9563_RST_PERIPH (0xd39d53bdUL)
> +#define RST9563_RST_PHY (0x50c57f90UL)
> +#define RST9563_RST_PTP (0xcf6e9a69UL)
> +#define RST9563_RST_PTP_MMCM (0xf69029c8UL)
> +#define RST9563_RST_RPP (0xa8868b03UL)
> +#define RST9563_RST_SDC (0x35477bfUL)
> +#define RST9563_RST_SYS (0xe18f0bc7UL)
> +#define RST9563_RST_SYS_MMCM (0x9f5c3d45UL)
> +#define RST9563_RST_TMC (0xd7d9da73UL)
> +#define RST9563_RST_TS (0x216dd0e7UL)
> +#define RST9563_RST_TSM_REF_MMCM (0x664f1a24UL)
> +#define RST9563_RST_TS_MMCM (0xce54ff59UL)
> +#define RST9563_STAT (0xad7dd604UL)
> +#define RST9563_STAT_CORE_MMCM_LOCKED (0xfd6d0a5aUL)
> +#define RST9563_STAT_DDR4_MMCM_LOCKED (0xb902f1d0UL)
> +#define RST9563_STAT_DDR4_PLL_LOCKED (0xe8a6d1b9UL)
> +#define RST9563_STAT_PTP_MMCM_LOCKED (0x4e4fd2a9UL)
> +#define RST9563_STAT_SYS_MMCM_LOCKED (0x5502a445UL)
> +#define RST9563_STAT_TS_MMCM_LOCKED (0xe6405b02UL)
> +#define RST9563_STICKY (0x97e2efe3UL)
> +#define RST9563_STICKY_CORE_MMCM_UNLOCKED (0xac340bb6UL)
> +#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (0x4737148cUL)
> +#define RST9563_STICKY_DDR4_PLL_UNLOCKED (0xf9857d1bUL)
> +#define RST9563_STICKY_PTP_MMCM_UNLOCKED (0x2a4e9819UL)
> +#define RST9563_STICKY_SYS_MMCM_UNLOCKED (0x61e3ebbdUL)
> +#define RST9563_STICKY_TS_MMCM_UNLOCKED (0x7e9f941eUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_RST= 9563_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
> new file mode 100644
> index 0000000000..ed3a25ebfa
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
> @@ -0,0 +1,44 @@
> +/*
> + * nthw_fpga_reg_defs_sdc.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_SDC_
> +#define _NTHW_FPGA_REG_DEFS_SDC_
> +
> +/* SDC */
> +#define NTHW_MOD_SDC (0xd2369530UL)
> +#define SDC_CELL_CNT (0xc6d82110UL)
> +#define SDC_CELL_CNT_CELL_CNT (0xdd4de629UL)
> +#define SDC_CELL_CNT_PERIOD (0x8dfef1d4UL)
> +#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (0x2b5819c1UL)
> +#define SDC_CTRL (0x1577b205UL)
> +#define SDC_CTRL_INIT (0x70e62104UL)
> +#define SDC_CTRL_RESET_POINTERS (0xec1c0f9cUL)
> +#define SDC_CTRL_RUN_TEST (0x2efbe98eUL)
> +#define SDC_CTRL_STOP_CLIENT (0xb11ebe2dUL)
> +#define SDC_CTRL_TEST_EN (0xaa1fa4UL)
> +#define SDC_FILL_LVL (0xd3b30232UL)
> +#define SDC_FILL_LVL_FILL_LVL (0xc97281acUL)
> +#define SDC_MAX_FILL_LVL (0x326de743UL)
> +#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (0x915fbf73UL)
> +#define SDC_STAT (0x37ed3c5eUL)
> +#define SDC_STAT_CALIB (0x27122e80UL)
> +#define SDC_STAT_CELL_CNT_STOPPED (0x517d5cafUL)
> +#define SDC_STAT_ERR_FOUND (0x3bb6bd0UL)
> +#define SDC_STAT_INIT_DONE (0x1dc2e095UL)
> +#define SDC_STAT_MMCM_LOCK (0xd9aac1c2UL)
> +#define SDC_STAT_PLL_LOCK (0x3bcab6ebUL)
> +#define SDC_STAT_RESETTING (0xa85349c1UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_SDC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
> new file mode 100644
> index 0000000000..da257a9425
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
> @@ -0,0 +1,33 @@
> +/*
> + * nthw_fpga_reg_defs_slc.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_SLC_
> +#define _NTHW_FPGA_REG_DEFS_SLC_
> +
> +/* SLC */
> +#define NTHW_MOD_SLC (0x1aef1f38UL)
> +#define SLC_RCP_CTRL (0xa3373b1UL)
> +#define SLC_RCP_CTRL_ADR (0xe64629e7UL)
> +#define SLC_RCP_CTRL_CNT (0xf64eb036UL)
> +#define SLC_RCP_DATA (0xa5e2f1a8UL)
> +#define SLC_RCP_DATA_HEAD_DYN (0x86b55a78UL)
> +#define SLC_RCP_DATA_HEAD_OFS (0x24bcd7deUL)
> +#define SLC_RCP_DATA_HEAD_SLC_EN (0x61cf5ef7UL)
> +#define SLC_RCP_DATA_PCAP (0x84909c04UL)
> +#define SLC_RCP_DATA_TAIL_DYN (0x85cd93a3UL)
> +#define SLC_RCP_DATA_TAIL_OFS (0x27c41e05UL)
> +#define SLC_RCP_DATA_TAIL_SLC_EN (0xa4f5112cUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_SLC= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_l= r.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
> new file mode 100644
> index 0000000000..6d1cf03bd8
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_slc_lr.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_SLC_LR_
> +#define _NTHW_FPGA_REG_DEFS_SLC_LR_
> +
> +/* SLC_LR */
> +#define NTHW_MOD_SLC_LR (0x969fc50bUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_SLC= _LR_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
> new file mode 100644
> index 0000000000..1e9eebd59a
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
> @@ -0,0 +1,75 @@
> +/*
> + * nthw_fpga_reg_defs_spim.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_SPIM_
> +#define _NTHW_FPGA_REG_DEFS_SPIM_
> +
> +/* SPIM */
> +#define NTHW_MOD_SPIM (0x1da437bfUL)
> +#define SPIM_CFG (0x90b6b0d5UL)
> +#define SPIM_CFG_PRE (0x156a8ea9UL)
> +#define SPIM_CFG_CLK (0xeb7046a1UL)
> +#define SPIM_CFG_CLK_MODE (0x228be0cbUL)
> +#define SPIM_CMD (0xea4b38a4UL)
> +#define SPIM_CMD_ADDR (0x95fe56baUL)
> +#define SPIM_CMD_CMD (0x9c30279bUL)
> +#define SPIM_CMD_DATA (0x6a9737ecUL)
> +#define SPIM_CONF0 (0x84d4acb5UL)
> +#define SPIM_CONF0_BYTE_PACE (0xc9a95016UL)
> +#define SPIM_CONF0_MIRROR_EN (0xa710688UL)
> +#define SPIM_CONF0_MSB_FIRST (0x5f60c96aUL)
> +#define SPIM_CONF0_PRESCAL_CLK (0xadb38a7UL)
> +#define SPIM_CONF0_RESTART (0x1fda85dcUL)
> +#define SPIM_CONF0_RST (0x64e3b3bUL)
> +#define SPIM_CONF0_SYNC_MON_EN (0x591a639eUL)
> +#define SPIM_CONF1 (0xf3d39c23UL)
> +#define SPIM_CONF1_MIRROR_PACE (0x370f3f34UL)
> +#define SPIM_CONF1_MIRROR_SCAN (0x83daffbeUL)
> +#define SPIM_CONF1_SYNCTIMEOUT (0x1b5d30cdUL)
> +#define SPIM_CONF2 (0x6adacd99UL)
> +#define SPIM_CONF2_MIRROR_PRESC (0x3a8c10e2UL)
> +#define SPIM_CONF2_OPCODE_RD (0x3eb6084fUL)
> +#define SPIM_CONF2_OPCODE_WR (0xb715495bUL)
> +#define SPIM_CONF3 (0x1dddfd0fUL)
> +#define SPIM_CONF3_MIRROR_RDADR (0xc00ba60fUL)
> +#define SPIM_CONF3_MIRROR_WRADR (0x7d99213cUL)
> +#define SPIM_CR (0x1c1de013UL)
> +#define SPIM_CR_EN (0xf2e0e72fUL)
> +#define SPIM_CR_LOOP (0xdeb882aUL)
> +#define SPIM_CR_RXRST (0x487f7d1bUL)
> +#define SPIM_CR_TXRST (0xc73f88bbUL)
> +#define SPIM_DRR (0xd68a95eeUL)
> +#define SPIM_DRR_DRR (0x78766633UL)
> +#define SPIM_DTR (0x80d03268UL)
> +#define SPIM_DTR_DTR (0xf87522a8UL)
> +#define SPIM_REPLY (0x6ed04defUL)
> +#define SPIM_REPLY_RDDATA (0x40db3b24UL)
> +#define SPIM_SR (0x56dff242UL)
> +#define SPIM_SR_DONE (0xdb47e9a1UL)
> +#define SPIM_SR_RXEMPTY (0x489aaf91UL)
> +#define SPIM_SR_RXFULL (0xd26832f5UL)
> +#define SPIM_SR_RXLVL (0x4c67ae59UL)
> +#define SPIM_SR_TXEMPTY (0x2b4a9aabUL)
> +#define SPIM_SR_TXFULL (0x431d1e8UL)
> +#define SPIM_SR_TXLVL (0xc3275bf9UL)
> +#define SPIM_SRR (0xcfe3201bUL)
> +#define SPIM_SRR_RST (0x32dc8fc5UL)
> +#define SPIM_STATUS (0xd04220ceUL)
> +#define SPIM_STATUS_CMDPENDING (0x74ed833fUL)
> +#define SPIM_STATUS_RESERVED (0xa50278bUL)
> +#define SPIM_STATUS_RESYNCDETECT (0x5b268881UL)
> +#define SPIM_STATUS_RESYNCING (0x5ec3f11UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_SPI= M_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
> new file mode 100644
> index 0000000000..30ff3a624e
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
> @@ -0,0 +1,50 @@
> +/*
> + * nthw_fpga_reg_defs_spis.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_SPIS_
> +#define _NTHW_FPGA_REG_DEFS_SPIS_
> +
> +/* SPIS */
> +#define NTHW_MOD_SPIS (0xe7ab0adcUL)
> +#define SPIS_CR (0xacdbc0bfUL)
> +#define SPIS_CR_DEBUG (0xf2096408UL)
> +#define SPIS_CR_EN (0xc50100bcUL)
> +#define SPIS_CR_LOOP (0x69e911c9UL)
> +#define SPIS_CR_RXRST (0x7118cc40UL)
> +#define SPIS_CR_TXRST (0xfe5839e0UL)
> +#define SPIS_DRR (0x95abc0dUL)
> +#define SPIS_DRR_DRR (0x1c74ffd0UL)
> +#define SPIS_DTR (0x5f001b8bUL)
> +#define SPIS_DTR_DTR (0x9c77bb4bUL)
> +#define SPIS_RAM_CTRL (0x682dc7d8UL)
> +#define SPIS_RAM_CTRL_ADR (0x15c2f809UL)
> +#define SPIS_RAM_CTRL_CNT (0x5ca61d8UL)
> +#define SPIS_RAM_DATA (0xc7fc45c1UL)
> +#define SPIS_RAM_DATA_DATA (0x422b05eaUL)
> +#define SPIS_SR (0xe619d2eeUL)
> +#define SPIS_SR_DONE (0xbf457042UL)
> +#define SPIS_SR_FRAME_ERR (0x31b5d7e4UL)
> +#define SPIS_SR_READ_ERR (0xa83d91f1UL)
> +#define SPIS_SR_RXEMPTY (0xadb39173UL)
> +#define SPIS_SR_RXFULL (0x2ee8dd38UL)
> +#define SPIS_SR_RXLVL (0x75001f02UL)
> +#define SPIS_SR_TXEMPTY (0xce63a449UL)
> +#define SPIS_SR_TXFULL (0xf8b13e25UL)
> +#define SPIS_SR_TXLVL (0xfa40eaa2UL)
> +#define SPIS_SR_WRITE_ERR (0x9d389ce2UL)
> +#define SPIS_SRR (0x103309f8UL)
> +#define SPIS_SRR_RST (0x56de1626UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_SPI= S_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
> new file mode 100644
> index 0000000000..a028ece8d8
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
> @@ -0,0 +1,59 @@
> +/*
> + * nthw_fpga_reg_defs_sta.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_STA_
> +#define _NTHW_FPGA_REG_DEFS_STA_
> +
> +/* STA */
> +#define NTHW_MOD_STA (0x76fae64dUL)
> +#define STA_BYTE (0xa08364d4UL)
> +#define STA_BYTE_CNT (0x3119e6bcUL)
> +#define STA_CFG (0xcecaf9f4UL)
> +#define STA_CFG_CNT_CLEAR (0xc325e12eUL)
> +#define STA_CFG_CNT_FRZ (0x8c27a596UL)
> +#define STA_CFG_DMA_ENA (0x940dbacUL)
> +#define STA_CFG_TX_DISABLE (0x30f43250UL)
> +#define STA_CV_ERR (0x7db7db5dUL)
> +#define STA_CV_ERR_CNT (0x2c02fbbeUL)
> +#define STA_FCS_ERR (0xa0de1647UL)
> +#define STA_FCS_ERR_CNT (0xc68c37d1UL)
> +#define STA_HOST_ADR_LSB (0xde569336UL)
> +#define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL)
> +#define STA_HOST_ADR_MSB (0xdf94f901UL)
> +#define STA_HOST_ADR_MSB_MSB (0x114798c8UL)
> +#define STA_LOAD_BIN (0x2e842591UL)
> +#define STA_LOAD_BIN_BIN (0x1a2b942eUL)
> +#define STA_LOAD_BPS_RX_0 (0xbf8f4595UL)
> +#define STA_LOAD_BPS_RX_0_BPS (0x41647781UL)
> +#define STA_LOAD_BPS_RX_1 (0xc8887503UL)
> +#define STA_LOAD_BPS_RX_1_BPS (0x7c045e31UL)
> +#define STA_LOAD_BPS_TX_0 (0x9ae41a49UL)
> +#define STA_LOAD_BPS_TX_0_BPS (0x870b7e06UL)
> +#define STA_LOAD_BPS_TX_1 (0xede32adfUL)
> +#define STA_LOAD_BPS_TX_1_BPS (0xba6b57b6UL)
> +#define STA_LOAD_PPS_RX_0 (0x811173c3UL)
> +#define STA_LOAD_PPS_RX_0_PPS (0xbee573fcUL)
> +#define STA_LOAD_PPS_RX_1 (0xf6164355UL)
> +#define STA_LOAD_PPS_RX_1_PPS (0x83855a4cUL)
> +#define STA_LOAD_PPS_TX_0 (0xa47a2c1fUL)
> +#define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL)
> +#define STA_LOAD_PPS_TX_1 (0xd37d1c89UL)
> +#define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL)
> +#define STA_PCKT (0xecc8f30aUL)
> +#define STA_PCKT_CNT (0x63291d16UL)
> +#define STA_STATUS (0x91c5c51cUL)
> +#define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_STA= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git
> a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
> new file mode 100644
> index 0000000000..5c5190bb4f
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h > @@ -0,0 +1,29 @@
> +/*
> + * nthw_fpga_reg_defs_tempmon.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TEMPMON_
> +#define _NTHW_FPGA_REG_DEFS_TEMPMON_
> +
> +/* TEMPMON */
> +#define NTHW_MOD_TEMPMON (0x2f77020dUL)
> +#define TEMPMON_ALARMS (0x3f7046c2UL)
> +#define TEMPMON_ALARMS_OT (0xb278af71UL)
> +#define TEMPMON_ALARMS_OT_OVERWR (0x6e4d38d3UL)
> +#define TEMPMON_ALARMS_OT_OVERWRVAL (0x9145f23eUL)
> +#define TEMPMON_ALARMS_TEMP (0x85d42f2cUL)
> +#define TEMPMON_STAT (0x9e81e173UL)
> +#define TEMPMON_STAT_TEMP (0x7bd5bb7bUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TEM= PMON_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.= h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
> new file mode 100644
> index 0000000000..9ffcec3bf6
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
> @@ -0,0 +1,27 @@
> +/*
> + * nthw_fpga_reg_defs_tint.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TINT_
> +#define _NTHW_FPGA_REG_DEFS_TINT_
> +
> +/* TINT */
> +#define NTHW_MOD_TINT (0xb8aea9feUL)
> +#define TINT_CTRL (0x95bdc9c3UL)
> +#define TINT_CTRL_INTERVAL (0xfe472b70UL)
> +#define TINT_STATUS (0x2557d8a6UL)
> +#define TINT_STATUS_DELAYED (0xabd2ff4cUL)
> +#define TINT_STATUS_SKIPPED (0x1c35b879UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TIN= T_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h=
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
> new file mode 100644
> index 0000000000..1eb7939d3a
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
> @@ -0,0 +1,294 @@
> +/*
> + * nthw_fpga_reg_defs_tsm.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TSM_
> +#define _NTHW_FPGA_REG_DEFS_TSM_
> +
> +/* TSM */
> +#define NTHW_MOD_TSM (0x35422a24UL)
> +#define TSM_ADJ_FINE_N (0x5ee7eb67UL)
> +#define TSM_ADJ_FINE_N_2DY (0x5e4ebc9dUL)
> +#define TSM_ADJ_FINE_N_2DY2DX (0x5d41df5UL)
> +#define TSM_ADJ_FINE_P (0xa4e8d604UL)
> +#define TSM_ADJ_FINE_P_2DY (0x819e957eUL)
> +#define TSM_ADJ_FINE_P_2DY2DX (0x6ce53eecUL)
> +#define TSM_ADJ_LIMIT_HI (0x735c7b90UL)
> +#define TSM_ADJ_LIMIT_HI_LIMIT (0x868cb9a6UL)
> +#define TSM_ADJ_LIMIT_LO (0xfe531ba1UL)
> +#define TSM_ADJ_LIMIT_LO_LIMIT (0x61168266UL)
> +#define TSM_BASIC_2DY (0x70dd9159UL)
> +#define TSM_BASIC_2DY_2DY (0xeea30d3fUL)
> +#define TSM_BASIC_2DY2DX (0xda5ebb56UL)
> +#define TSM_BASIC_2DY2DX_2DY2DX (0x78a2f0edUL)
> +#define TSM_CON0_CONFIG (0xf893d371UL)
> +#define TSM_CON0_CONFIG_BLIND (0x59ccfcbUL)
> +#define TSM_CON0_CONFIG_DC_SRC (0x1879812bUL)
> +#define TSM_CON0_CONFIG_PORT (0x3ff0bb08UL)
> +#define TSM_CON0_CONFIG_PPSIN_2_5V (0xb8e78227UL)
> +#define TSM_CON0_CONFIG_SAMPLE_EDGE (0x4a4022ebUL)
> +#define TSM_CON0_INTERFACE (0x76e93b59UL)
> +#define TSM_CON0_INTERFACE_EX_TERM (0xd079b416UL)
> +#define TSM_CON0_INTERFACE_IN_REF_PWM (0x16f73c33UL)
> +#define TSM_CON0_INTERFACE_PWM_ENA (0x3629e73fUL)
> +#define TSM_CON0_INTERFACE_RESERVED (0xf9c5066UL)
> +#define TSM_CON0_INTERFACE_VTERM_PWM (0x6d2b1e23UL)
> +#define TSM_CON0_SAMPLE_HI (0x6e536b8UL)
> +#define TSM_CON0_SAMPLE_HI_SEC (0x5fc26159UL)
> +#define TSM_CON0_SAMPLE_LO (0x8bea5689UL)
> +#define TSM_CON0_SAMPLE_LO_NS (0x13d0010dUL)
> +#define TSM_CON1_CONFIG (0x3439d3efUL)
> +#define TSM_CON1_CONFIG_BLIND (0x98932ebdUL)
> +#define TSM_CON1_CONFIG_DC_SRC (0xa1825ac3UL)
> +#define TSM_CON1_CONFIG_PORT (0xe266628dUL)
> +#define TSM_CON1_CONFIG_PPSIN_2_5V (0x6f05027fUL)
> +#define TSM_CON1_CONFIG_SAMPLE_EDGE (0x2f2719adUL)
> +#define TSM_CON1_SAMPLE_HI (0xc76be978UL)
> +#define TSM_CON1_SAMPLE_HI_SEC (0xe639bab1UL)
> +#define TSM_CON1_SAMPLE_LO (0x4a648949UL)
> +#define TSM_CON1_SAMPLE_LO_NS (0x8edfe07bUL)
> +#define TSM_CON2_CONFIG (0xbab6d40cUL)
> +#define TSM_CON2_CONFIG_BLIND (0xe4f20b66UL)
> +#define TSM_CON2_CONFIG_DC_SRC (0xb0ff30baUL)
> +#define TSM_CON2_CONFIG_PORT (0x5fac0e43UL)
> +#define TSM_CON2_CONFIG_PPSIN_2_5V (0xcc5384d6UL)
> +#define TSM_CON2_CONFIG_SAMPLE_EDGE (0x808e5467UL)
> +#define TSM_CON2_SAMPLE_HI (0x5e898f79UL)
> +#define TSM_CON2_SAMPLE_HI_SEC (0xf744d0c8UL)
> +#define TSM_CON2_SAMPLE_LO (0xd386ef48UL)
> +#define TSM_CON2_SAMPLE_LO_NS (0xf2bec5a0UL)
> +#define TSM_CON3_CONFIG (0x761cd492UL)
> +#define TSM_CON3_CONFIG_BLIND (0x79fdea10UL)
> +#define TSM_CON3_CONFIG_PORT (0x823ad7c6UL)
> +#define TSM_CON3_CONFIG_SAMPLE_EDGE (0xe5e96f21UL)
> +#define TSM_CON3_SAMPLE_HI (0x9f0750b9UL)
> +#define TSM_CON3_SAMPLE_HI_SEC (0x4ebf0b20UL)
> +#define TSM_CON3_SAMPLE_LO (0x12083088UL)
> +#define TSM_CON3_SAMPLE_LO_NS (0x6fb124d6UL)
> +#define TSM_CON4_CONFIG (0x7cd9dd8bUL)
> +#define TSM_CON4_CONFIG_BLIND (0x1c3040d0UL)
> +#define TSM_CON4_CONFIG_PORT (0xff49d19eUL)
> +#define TSM_CON4_CONFIG_SAMPLE_EDGE (0x4adc9b2UL)
> +#define TSM_CON4_SAMPLE_HI (0xb63c453aUL)
> +#define TSM_CON4_SAMPLE_HI_SEC (0xd5be043aUL)
> +#define TSM_CON4_SAMPLE_LO (0x3b33250bUL)
> +#define TSM_CON4_SAMPLE_LO_NS (0xa7c8e16UL)
> +#define TSM_CON5_CONFIG (0xb073dd15UL)
> +#define TSM_CON5_CONFIG_BLIND (0x813fa1a6UL)
> +#define TSM_CON5_CONFIG_PORT (0x22df081bUL)
> +#define TSM_CON5_CONFIG_SAMPLE_EDGE (0x61caf2f4UL)
> +#define TSM_CON5_SAMPLE_HI (0x77b29afaUL)
> +#define TSM_CON5_SAMPLE_HI_SEC (0x6c45dfd2UL)
> +#define TSM_CON5_SAMPLE_LO (0xfabdfacbUL)
> +#define TSM_CON5_SAMPLE_LO_TIME (0x945d87e8UL)
> +#define TSM_CON6_CONFIG (0x3efcdaf6UL)
> +#define TSM_CON6_CONFIG_BLIND (0xfd5e847dUL)
> +#define TSM_CON6_CONFIG_PORT (0x9f1564d5UL)
> +#define TSM_CON6_CONFIG_SAMPLE_EDGE (0xce63bf3eUL)
> +#define TSM_CON6_SAMPLE_HI (0xee50fcfbUL)
> +#define TSM_CON6_SAMPLE_HI_SEC (0x7d38b5abUL)
> +#define TSM_CON6_SAMPLE_LO (0x635f9ccaUL)
> +#define TSM_CON6_SAMPLE_LO_NS (0xeb124abbUL)
> +#define TSM_CON7_HOST_SAMPLE_HI (0xdcd90e52UL)
> +#define TSM_CON7_HOST_SAMPLE_HI_SEC (0xd98d3618UL)
> +#define TSM_CON7_HOST_SAMPLE_LO (0x51d66e63UL)
> +#define TSM_CON7_HOST_SAMPLE_LO_NS (0x8f5594ddUL)
> +#define TSM_CONFIG (0xef5dec83UL)
> +#define TSM_CONFIG_NTTS_SRC (0x1b60227bUL)
> +#define TSM_CONFIG_NTTS_SYNC (0x43e0a69dUL)
> +#define TSM_CONFIG_TIMESET_EDGE (0x8c381127UL)
> +#define TSM_CONFIG_TIMESET_SRC (0xe7590a31UL)
> +#define TSM_CONFIG_TIMESET_UP (0x561980c1UL)
> +#define TSM_CONFIG_TS_FORMAT (0xe6efc2faUL)
> +#define TSM_CTRL (0x87c1782cUL)
> +#define TSM_CTRL_DCEN_CON0 (0x50b3db87UL)
> +#define TSM_CTRL_DCEN_CON1 (0x27b4eb11UL)
> +#define TSM_CTRL_DCEN_CON2 (0xbebdbaabUL)
> +#define TSM_CTRL_FORMAT (0xd6f91ae8UL)
> +#define TSM_CTRL_HIGH_SAMPLE (0x6d4509b1UL)
> +#define TSM_CTRL_LED_CON0 (0x225af447UL)
> +#define TSM_CTRL_LED_CON1 (0x555dc4d1UL)
> +#define TSM_CTRL_LED_CON2 (0xcc54956bUL)
> +#define TSM_CTRL_MASTER_STAT (0x6a0e3d17UL)
> +#define TSM_CTRL_OEN_CON0 (0xd4ed0c2UL)
> +#define TSM_CTRL_OEN_CON1 (0x7a49e054UL)
> +#define TSM_CTRL_OEN_CON2 (0xe340b1eeUL)
> +#define TSM_CTRL_PPSEN (0x9eada897UL)
> +#define TSM_CTRL_PPS_NEGEDGE (0x8390d486UL)
> +#define TSM_CTRL_PPS_TIME_UP (0x78161775UL)
> +#define TSM_CTRL_PTP_TIME_UP (0x48708bcaUL)
> +#define TSM_CTRL_RESERVED (0x3026aeb5UL)
> +#define TSM_CTRL_SEL_EXTSRC (0x57855b43UL)
> +#define TSM_CTRL_SYNEN (0xb0fbadeeUL)
> +#define TSM_CTRL_TS_CON0 (0x7c756725UL)
> +#define TSM_CTRL_TS_CON1 (0xb7257b3UL)
> +#define TSM_CTRL_TS_CON2 (0x927b0609UL)
> +#define TSM_EXT_STAT (0xf7c0a6cbUL)
> +#define TSM_EXT_STAT_STAT (0xb32dd5d8UL)
> +#define TSM_EXT_TIME_HI (0x678de1fUL)
> +#define TSM_EXT_TIME_HI_TIME (0xe8159c02UL)
> +#define TSM_EXT_TIME_LO (0x8b77be2eUL)
> +#define TSM_EXT_TIME_LO_TIME (0xca035b0cUL)
> +#define TSM_INTERFACE (0xe4ab597bUL)
> +#define TSM_INTERFACE_EX_TERM (0x9e5553e6UL)
> +#define TSM_INTERFACE_IN_REF_PWM (0x80d44665UL)
> +#define TSM_INTERFACE_PWM_ENA (0x780500cfUL)
> +#define TSM_INTERFACE_RESERVED (0xb26f8e9dUL)
> +#define TSM_INTERFACE_VTERM_PWM (0x47f9c669UL)
> +#define TSM_INT_CONFIG (0x9a0d52dUL)
> +#define TSM_INT_CONFIG_AUTO_DISABLE (0x9581470UL)
> +#define TSM_INT_CONFIG_MASK (0xf00cd3d7UL)
> +#define TSM_INT_STAT (0xa4611a70UL)
> +#define TSM_INT_STAT_CAUSE (0x315168cfUL)
> +#define TSM_INT_STAT_ENABLE (0x980a12d1UL)
> +#define TSM_INT_TIME_HI (0x26d2bd77UL)
> +#define TSM_INT_TIME_HI_TIME (0x29af0477UL)
> +#define TSM_INT_TIME_LO (0xabdddd46UL)
> +#define TSM_INT_TIME_LO_TIME (0xbb9c379UL)
> +#define TSM_LED (0x6ae05f87UL)
> +#define TSM_LED_LED0_BG_COLOR (0x897cf9eeUL)
> +#define TSM_LED_LED0_COLOR (0x6d7ada39UL)
> +#define TSM_LED_LED0_MODE (0x6087b644UL)
> +#define TSM_LED_LED0_SRC (0x4fe29639UL)
> +#define TSM_LED_LED1_BG_COLOR (0x66be92d0UL)
> +#define TSM_LED_LED1_COLOR (0xcb0dd18dUL)
> +#define TSM_LED_LED1_MODE (0xabdb65e1UL)
> +#define TSM_LED_LED1_SRC (0x7282bf89UL)
> +#define TSM_LED_LED2_BG_COLOR (0x8d8929d3UL)
> +#define TSM_LED_LED2_COLOR (0xfae5cb10UL)
> +#define TSM_LED_LED2_MODE (0x2d4f174fUL)
> +#define TSM_LED_LED2_SRC (0x3522c559UL)
> +#define TSM_NTTS_CONFIG (0x8bc38bdeUL)
> +#define TSM_NTTS_CONFIG_AUTO_HARDSET (0xd75be25dUL)
> +#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (0x700425b6UL)
> +#define TSM_NTTS_CONFIG_HIGH_SAMPLE (0x37135b7eUL)
> +#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (0x6e6e707UL)
> +#define TSM_NTTS_CTRL (0x4798367bUL)
> +#define TSM_NTTS_CTRL_NTTS_CMD (0x85e132cfUL)
> +#define TSM_NTTS_DATA_HI (0x6bfb0188UL)
> +#define TSM_NTTS_DATA_HI_DATA (0x44315d8UL)
> +#define TSM_NTTS_DATA_LO (0xe6f461b9UL)
> +#define TSM_NTTS_DATA_LO_DATA (0x2655d2d6UL)
> +#define TSM_NTTS_EXT_STAT (0x2b0315b7UL)
> +#define TSM_NTTS_EXT_STAT_MASTER_ID (0xf263315eUL)
> +#define TSM_NTTS_EXT_STAT_MASTER_REV (0xd543795eUL)
> +#define TSM_NTTS_EXT_STAT_MASTER_STAT (0x92d96f5eUL)
> +#define TSM_NTTS_LIMIT_HI (0x1ddaa85fUL)
> +#define TSM_NTTS_LIMIT_HI_SEC (0x315c6ef2UL)
> +#define TSM_NTTS_LIMIT_LO (0x90d5c86eUL)
> +#define TSM_NTTS_LIMIT_LO_NS (0xe6d94d9aUL)
> +#define TSM_NTTS_OFFSET (0x6436e72UL)
> +#define TSM_NTTS_OFFSET_NS (0x12d43a06UL)
> +#define TSM_NTTS_SAMPLE_HI (0xcdc8aa3eUL)
> +#define TSM_NTTS_SAMPLE_HI_SEC (0x4f6588fdUL)
> +#define TSM_NTTS_SAMPLE_LO (0x40c7ca0fUL)
> +#define TSM_NTTS_SAMPLE_LO_NS (0x6e43ff97UL)
> +#define TSM_NTTS_STAT (0x6502b820UL)
> +#define TSM_NTTS_STAT_NTTS_VALID (0x3e184471UL)
> +#define TSM_NTTS_STAT_SIGNAL_LOST (0x178bedfdUL)
> +#define TSM_NTTS_STAT_SYNC_LOST (0xe4cd53dfUL)
> +#define TSM_NTTS_TS_T0_HI (0x1300d1b6UL)
> +#define TSM_NTTS_TS_T0_HI_TIME (0xa016ae4fUL)
> +#define TSM_NTTS_TS_T0_LO (0x9e0fb187UL)
> +#define TSM_NTTS_TS_T0_LO_TIME (0x82006941UL)
> +#define TSM_NTTS_TS_T0_OFFSET (0xbf70ce4fUL)
> +#define TSM_NTTS_TS_T0_OFFSET_COUNT (0x35dd4398UL)
> +#define TSM_OFFSET_HI (0xb5b09839UL)
> +#define TSM_OFFSET_HI_OFFSET (0xec7bf359UL)
> +#define TSM_OFFSET_LO (0x38bff808UL)
> +#define TSM_OFFSET_LO_OFFSET (0x77f8abd2UL)
> +#define TSM_PB_CTRL (0x7a8b60faUL)
> +#define TSM_PB_CTRL_INSTMEM_WR (0xf96e2cbcUL)
> +#define TSM_PB_CTRL_RESET (0xa38ade8bUL)
> +#define TSM_PB_CTRL_RST (0x3aaa82f4UL)
> +#define TSM_PB_INSTMEM (0xb54aeecUL)
> +#define TSM_PB_INSTMEM_ADDR (0x3549ddaaUL)
> +#define TSM_PB_INSTMEM_DATA (0xca20bcfcUL)
> +#define TSM_PB_INSTMEM_MEM_ADDR (0x9ac79b6eUL)
> +#define TSM_PB_INSTMEM_MEM_DATA (0x65aefa38UL)
> +#define TSM_PI_CTRL_I (0x8d71a4e2UL)
> +#define TSM_PI_CTRL_I_VAL (0x98baedc9UL)
> +#define TSM_PI_CTRL_KI (0xa1bd86cbUL)
> +#define TSM_PI_CTRL_KI_GAIN (0x53faa916UL)
> +#define TSM_PI_CTRL_KP (0xc5d62e0bUL)
> +#define TSM_PI_CTRL_KP_GAIN (0x7723fa45UL)
> +#define TSM_PI_CTRL_SHL (0xaa518701UL)
> +#define TSM_PI_CTRL_SHL_VAL (0x56f56a6fUL)
> +#define TSM_RSYNC_COUNT (0xa7bb7108UL)
> +#define TSM_RSYNC_COUNT_COUNT (0x66e7d46UL)
> +#define TSM_STAT (0xa55bf677UL)
> +#define TSM_STAT_EXT_SRC_OK (0x62036046UL)
> +#define TSM_STAT_HARD_SYNC (0x7fff20fdUL)
> +#define TSM_STAT_INSYNC (0x29f2e4adUL)
> +#define TSM_STAT_LINK_ACTIVE (0x575513d4UL)
> +#define TSM_STAT_LINK_CON0 (0x216086f0UL)
> +#define TSM_STAT_LINK_CON1 (0x5667b666UL)
> +#define TSM_STAT_LINK_CON2 (0xcf6ee7dcUL)
> +#define TSM_STAT_LINK_CON3 (0xb869d74aUL)
> +#define TSM_STAT_LINK_CON4 (0x260d42e9UL)
> +#define TSM_STAT_LINK_CON5 (0x510a727fUL)
> +#define TSM_STAT_NTTS_INSYNC (0xb593a245UL)
> +#define TSM_STAT_PTP_MI_PRESENT (0x43131eb0UL)
> +#define TSM_TIMER_CTRL (0x648da051UL)
> +#define TSM_TIMER_CTRL_TIMER_EN_T0 (0x17cee154UL)
> +#define TSM_TIMER_CTRL_TIMER_EN_T1 (0x60c9d1c2UL)
> +#define TSM_TIMER_CTRL_TRIGGER_SEL (0x79f7c3a5UL)
> +#define TSM_TIMER_D_T0 (0xfae6ed98UL)
> +#define TSM_TIMER_D_T0_MAX_COUNT (0xbd0df6dbUL)
> +#define TSM_TIMER_T0 (0x417217a5UL)
> +#define TSM_TIMER_T0_MAX_COUNT (0xaa601706UL)
> +#define TSM_TIMER_T1 (0x36752733UL)
> +#define TSM_TIMER_T1_MAX_COUNT (0x6beec8c6UL)
> +#define TSM_TIMESTAMP_HI (0x59f35088UL)
> +#define TSM_TIMESTAMP_HI_TIME (0x56f613f0UL)
> +#define TSM_TIMESTAMP_LO (0xd4fc30b9UL)
> +#define TSM_TIMESTAMP_LO_TIME (0x74e0d4feUL)
> +#define TSM_TIME_HARDSET_HI (0xf28bdb46UL)
> +#define TSM_TIME_HARDSET_HI_TIME (0x2d9a28baUL)
> +#define TSM_TIME_HARDSET_LO (0x7f84bb77UL)
> +#define TSM_TIME_HARDSET_LO_TIME (0xf8cefb4UL)
> +#define TSM_TIME_HI (0x175acea1UL)
> +#define TSM_TIME_HI_SEC (0xc0e9c9a1UL)
> +#define TSM_TIME_HI_TIME (0x7febcc76UL)
> +#define TSM_TIME_LO (0x9a55ae90UL)
> +#define TSM_TIME_LO_NS (0x879c5c4bUL)
> +#define TSM_TIME_RATE_ADJ (0xb1cc4bb1UL)
> +#define TSM_TIME_RATE_ADJ_FRACTION (0xb7ab96UL)
> +#define TSM_TS_HI (0xccfe9e5eUL)
> +#define TSM_TS_HI_TIME (0xc23fed30UL)
> +#define TSM_TS_LO (0x41f1fe6fUL)
> +#define TSM_TS_LO_TIME (0xe0292a3eUL)
> +#define TSM_TS_OFFSET (0x4b2e6e13UL)
> +#define TSM_TS_OFFSET_NS (0x68c286b9UL)
> +#define TSM_TS_STAT (0x64d41b8cUL)
> +#define TSM_TS_STAT_OVERRUN (0xad9db92aUL)
> +#define TSM_TS_STAT_SAMPLES (0xb6350e0bUL)
> +#define TSM_TS_STAT_HI_OFFSET (0x1aa2ddf2UL)
> +#define TSM_TS_STAT_HI_OFFSET_NS (0xeb040e0fUL)
> +#define TSM_TS_STAT_LO_OFFSET (0x81218579UL)
> +#define TSM_TS_STAT_LO_OFFSET_NS (0xb7ff33UL)
> +#define TSM_TS_STAT_TAR_HI (0x65af24b6UL)
> +#define TSM_TS_STAT_TAR_HI_SEC (0x7e92f619UL)
> +#define TSM_TS_STAT_TAR_LO (0xe8a04487UL)
> +#define TSM_TS_STAT_TAR_LO_NS (0xf7b3f439UL)
> +#define TSM_TS_STAT_X (0x419f0ddUL)
> +#define TSM_TS_STAT_X_NS (0xa48c3f27UL)
> +#define TSM_TS_STAT_X2_HI (0xd6b1c517UL)
> +#define TSM_TS_STAT_X2_HI_NS (0x4288c50fUL)
> +#define TSM_TS_STAT_X2_LO (0x5bbea526UL)
> +#define TSM_TS_STAT_X2_LO_NS (0x92633c13UL)
> +#define TSM_UTC_OFFSET (0xf622a13aUL)
> +#define TSM_UTC_OFFSET_SEC (0xd9c80209UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TSM= _ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cp= y.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
> new file mode 100644
> index 0000000000..2b156f9de9
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_tx_cpy.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TX_CPY_
> +#define _NTHW_FPGA_REG_DEFS_TX_CPY_
> +
> +/* TX_CPY */
> +#define NTHW_MOD_TX_CPY (0x60acf217UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TX_= CPY_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cs= i.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
> new file mode 100644
> index 0000000000..98d9bbc452
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_tx_csi.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TX_CSI_
> +#define _NTHW_FPGA_REG_DEFS_TX_CSI_
> +
> +/* TX_CSI */
> +#define NTHW_MOD_TX_CSI (0x5636b1b0UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TX_= CSI_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cs= o.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
> new file mode 100644
> index 0000000000..8b2d77878b
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_tx_cso.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TX_CSO_
> +#define _NTHW_FPGA_REG_DEFS_TX_CSO_
> +
> +/* TX_CSO */
> +#define NTHW_MOD_TX_CSO (0xbf551485UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TX_= CSO_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_in= s.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
> new file mode 100644
> index 0000000000..48add8d788
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_tx_ins.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TX_INS_
> +#define _NTHW_FPGA_REG_DEFS_TX_INS_
> +
> +/* TX_INS */
> +#define NTHW_MOD_TX_INS (0x59afa100UL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TX_= INS_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rp= l.h
> b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
> new file mode 100644
> index 0000000000..2ddeadaf53
> --- /dev/null
> +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
> @@ -0,0 +1,22 @@
> +/*
> + * nthw_fpga_reg_defs_tx_rpl.h
> + *
> + * Auto-generated file - do *NOT* edit
> + *
> + */
> +
> +#ifndef _NTHW_FPGA_REG_DEFS_TX_RPL_
> +#define _NTHW_FPGA_REG_DEFS_TX_RPL_
> +
> +/* TX_RPL */
> +#define NTHW_MOD_TX_RPL (0x1095dfbbUL)
> +
> +#endif       /* _NTHW_FPGA_REG_DEFS_TX_= RPL_ */
> +
> +/*
> + * Auto-generated file - do *NOT* edit
> + */
> +
> +/*
> + * EOF
> + */
> --
> 2.45.0

--_000_VE1P190MB08300D0553879E2525AC6FE380FB2VE1P190MB0830EURP_--