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X-Microsoft-Antispam-Message-Info: FWSYk5J36G5tap5y0Ff0LD46Mf1yupubhGiUvH9Dh1wNXOWrgzpgn++RGbFBWcOKajm4oOS1NBIB1SjqlGKAVpinqLvLHRTDFNRqoHh8ttvr/7AynYHNfkp7he/9E+FhO7tDd++bNJAYRBtXi9ZTJ9Om3u4rJ8RdrLvGcsqcvEcywrlPr2YiJ3FS6KXYV3l9y8t+Kc+ptpE6kwvcnivQ9sCb0s3fyED2eyeY/3D+NvghJ66j75ompFtTYY0ZDI+YtoG3b4GlNfYJRyzHJBssZ4fDCeaTzRTYacvLYFubl8+RTzg39LdcUhX2ejKttEYu5WVrJWaQZicUlzQU/K78vINORpDYWkcYYbbDsm7ucFUtu/UTkoO3qHyQNVvykxybb0RQ9gRTOKjqUfUwEv39zk5jIw+woiNVIovuoO0aS7LLgLxn4fkXauGzpJk4YXCfSxNJNinx28dOl3hKtu8e2LpwHvJh7phMSFq3M8K/Vf3rXU5IN1SShNzpgvEmBvEkRI9Lpg8zoAQ4OeTHOOJYkYxi2PYOtbloHldewDBzuKw= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2020 06:25:52.7691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9506686-16fd-4a41-8335-08d7d4733268 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0801MB2041 Subject: Re: [dpdk-dev] [PATCH] event/octeontx2: use c11 atomics for statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: pbhagavatula@marvell.com > Sent: Friday, March 27, 2020 4:56 PM > To: jerinj@marvell.com; Honnappa Nagarahalli > ; Phil Yang ; Pavan > Nikhilesh > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] event/octeontx2: use c11 atomics for statisti= cs >=20 > From: Pavan Nikhilesh >=20 > Use c11 atomics with RELAXED ordering instead of rte_atomic ops which > enforce unnessary barries on arm64. >=20 > Signed-off-by: Pavan Nikhilesh > --- > drivers/event/octeontx2/otx2_tim_evdev.c | 5 +++-- > drivers/event/octeontx2/otx2_tim_evdev.h | 2 +- > drivers/event/octeontx2/otx2_tim_worker.c | 5 +++-- > 3 files changed, 7 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c > b/drivers/event/octeontx2/otx2_tim_evdev.c > index cd0dcde24..4c24cc8a6 100644 > --- a/drivers/event/octeontx2/otx2_tim_evdev.c > +++ b/drivers/event/octeontx2/otx2_tim_evdev.c > @@ -526,7 +526,8 @@ otx2_tim_stats_get(const struct > rte_event_timer_adapter *adapter, > uint64_t bkt_cyc =3D rte_rdtsc() - tim_ring->ring_start_cyc; >=20 >=20 > - stats->evtim_exp_count =3D rte_atomic64_read(&tim_ring->arm_cnt); > + stats->evtim_exp_count =3D __atomic_load_n(&tim_ring->arm_cnt, > + __ATOMIC_RELAXED); > stats->ev_enq_count =3D stats->evtim_exp_count; > stats->adapter_tick_count =3D rte_reciprocal_divide_u64(bkt_cyc, > &tim_ring->fast_div); > @@ -538,7 +539,7 @@ otx2_tim_stats_reset(const struct > rte_event_timer_adapter *adapter) > { > struct otx2_tim_ring *tim_ring =3D adapter->data->adapter_priv; >=20 > - rte_atomic64_clear(&tim_ring->arm_cnt); > + __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED); Both otx2_tim_stats_get & otx2_tim_stats_reset operations are handled in th= e same thread, and the arm_cmn read & store operations are sequential consistent in this c= ase.=20 So RELAXED memory ordering here is enough. > return 0; > } >=20 > diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h > b/drivers/event/octeontx2/otx2_tim_evdev.h > index 56895dcbf..44e3c7b51 100644 > --- a/drivers/event/octeontx2/otx2_tim_evdev.h > +++ b/drivers/event/octeontx2/otx2_tim_evdev.h > @@ -149,7 +149,7 @@ struct otx2_tim_ring { > struct otx2_tim_bkt *bkt; > struct rte_mempool *chunk_pool; > struct rte_reciprocal_u64 fast_div; > - rte_atomic64_t arm_cnt; > + uint64_t arm_cnt; > uint8_t prod_type_sp; > uint8_t enable_stats; > uint8_t disable_npa; > diff --git a/drivers/event/octeontx2/otx2_tim_worker.c > b/drivers/event/octeontx2/otx2_tim_worker.c > index 104674c79..4b5cfdc72 100644 > --- a/drivers/event/octeontx2/otx2_tim_worker.c > +++ b/drivers/event/octeontx2/otx2_tim_worker.c > @@ -88,7 +88,7 @@ tim_timer_arm_burst(const struct > rte_event_timer_adapter *adptr, > } >=20 > if (flags & OTX2_TIM_ENA_STATS) > - rte_atomic64_add(&tim_ring->arm_cnt, index); > + __atomic_fetch_add(&tim_ring->arm_cnt, index, > __ATOMIC_RELAXED); >=20 > return index; > } > @@ -130,7 +130,8 @@ tim_timer_arm_tmo_brst(const struct > rte_event_timer_adapter *adptr, > break; > } > if (flags & OTX2_TIM_ENA_STATS) > - rte_atomic64_add(&tim_ring->arm_cnt, set_timers); > + __atomic_fetch_add(&tim_ring->arm_cnt, set_timers, > + __ATOMIC_RELAXED); >=20 > return set_timers; > } > -- > 2.17.1 It goods good to me. Reviewed-by: Phil Yang Thanks, Phil