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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4957 Subject: Re: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" + Gavin > -----Original Message----- > From: dev On Behalf Of Phil Yang > Sent: Monday, August 26, 2019 7:00 PM > To: jgrajcia@cisco.com; dev@dpdk.org > Cc: thomas@monjalon.net; jerinj@marvell.com; Honnappa Nagarahalli > ; damarion@cisco.com; nd > > Subject: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier >=20 > Using 'rte_mb' to synchronize the shared ring head/tail between producer > and consumer will stall the pipeline and damage performance on the weak > memory model platforms, such like aarch64. Meanwhile update the shared > ring head and tail are observable and ordered between CPUs on IA. >=20 > Optimized this full barrier with the one-way barrier can improve the > throughput. On aarch64 n1sdp server this patch make testpmd throughput > boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain. >=20 > Signed-off-by: Phil Yang > Reviewed-by: Gavin Hu > --- > drivers/net/memif/memif.h | 4 +-- > drivers/net/memif/rte_eth_memif.c | 53 +++++++++++++++++++++-------- > ---------- > 2 files changed, 31 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/net/memif/memif.h b/drivers/net/memif/memif.h > index 3948b1f..a4d88c0 100644 > --- a/drivers/net/memif/memif.h > +++ b/drivers/net/memif/memif.h > @@ -169,9 +169,9 @@ typedef struct { > uint32_t cookie; /**< MEMIF_COOKIE */ > uint16_t flags; /**< flags */ > #define MEMIF_RING_FLAG_MASK_INT 1 /**< disable interrupt > mode */ > - volatile uint16_t head; /**< pointer to ring buffer > head */ > + uint16_t head; /**< pointer to ring buffer head */ > MEMIF_CACHELINE_ALIGN_MARK(cacheline1); > - volatile uint16_t tail; /**< pointer to ring buffer > tail */ > + uint16_t tail; /**< pointer to ring buffer tail */ > MEMIF_CACHELINE_ALIGN_MARK(cacheline2); > memif_desc_t desc[0]; /**< buffer descriptors */ > } memif_ring_t; > diff --git a/drivers/net/memif/rte_eth_memif.c > b/drivers/net/memif/rte_eth_memif.c > index a59f809..b1c871e 100644 > --- a/drivers/net/memif/rte_eth_memif.c > +++ b/drivers/net/memif/rte_eth_memif.c > @@ -275,8 +275,14 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, > uint16_t nb_pkts) > ring_size =3D 1 << mq->log2_ring_size; > mask =3D ring_size - 1; >=20 > - cur_slot =3D (type =3D=3D MEMIF_RING_S2M) ? mq->last_head : mq- > >last_tail; > - last_slot =3D (type =3D=3D MEMIF_RING_S2M) ? ring->head : ring->tail; > + if (type =3D=3D MEMIF_RING_S2M) { > + cur_slot =3D mq->last_head; > + last_slot =3D __atomic_load_n(&ring->head, > __ATOMIC_ACQUIRE); > + } else { > + cur_slot =3D mq->last_tail; > + last_slot =3D __atomic_load_n(&ring->tail, > __ATOMIC_ACQUIRE); > + } > + > if (cur_slot =3D=3D last_slot) > goto refill; > n_slots =3D last_slot - cur_slot; > @@ -344,8 +350,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, > uint16_t nb_pkts) >=20 > no_free_bufs: > if (type =3D=3D MEMIF_RING_S2M) { > - rte_mb(); > - ring->tail =3D cur_slot; > + __atomic_store_n(&ring->tail, cur_slot, > __ATOMIC_RELEASE); > mq->last_head =3D cur_slot; > } else { > mq->last_tail =3D cur_slot; > @@ -353,7 +358,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, > uint16_t nb_pkts) >=20 > refill: > if (type =3D=3D MEMIF_RING_M2S) { > - head =3D ring->head; > + head =3D __atomic_load_n(&ring->head, > __ATOMIC_ACQUIRE); > n_slots =3D ring_size - head + mq->last_tail; >=20 > while (n_slots--) { > @@ -361,8 +366,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, > uint16_t nb_pkts) > d0 =3D &ring->desc[s0]; > d0->length =3D pmd->run.pkt_buffer_size; > } > - rte_mb(); > - ring->head =3D head; > + __atomic_store_n(&ring->head, head, __ATOMIC_RELEASE); > } >=20 > mq->n_pkts +=3D n_rx_pkts; > @@ -398,14 +402,16 @@ eth_memif_tx(void *queue, struct rte_mbuf > **bufs, uint16_t nb_pkts) > ring_size =3D 1 << mq->log2_ring_size; > mask =3D ring_size - 1; >=20 > - n_free =3D ring->tail - mq->last_tail; > + n_free =3D __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE) - mq- > >last_tail; > mq->last_tail +=3D n_free; > - slot =3D (type =3D=3D MEMIF_RING_S2M) ? ring->head : ring->tail; >=20 > - if (type =3D=3D MEMIF_RING_S2M) > - n_free =3D ring_size - ring->head + mq->last_tail; > - else > - n_free =3D ring->head - ring->tail; > + if (type =3D=3D MEMIF_RING_S2M) { > + slot =3D __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE); > + n_free =3D ring_size - slot + mq->last_tail; > + } else { > + slot =3D __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE); > + n_free =3D __atomic_load_n(&ring->head, > __ATOMIC_ACQUIRE) - slot; > + } >=20 > while (n_tx_pkts < nb_pkts && n_free) { > mbuf_head =3D *bufs++; > @@ -464,11 +470,10 @@ eth_memif_tx(void *queue, struct rte_mbuf > **bufs, uint16_t nb_pkts) > } >=20 > no_free_slots: > - rte_mb(); > if (type =3D=3D MEMIF_RING_S2M) > - ring->head =3D slot; > + __atomic_store_n(&ring->head, slot, __ATOMIC_RELEASE); > else > - ring->tail =3D slot; > + __atomic_store_n(&ring->tail, slot, __ATOMIC_RELEASE); >=20 > if ((ring->flags & MEMIF_RING_FLAG_MASK_INT) =3D=3D 0) { > a =3D 1; > @@ -611,8 +616,8 @@ memif_init_rings(struct rte_eth_dev *dev) >=20 > for (i =3D 0; i < pmd->run.num_s2m_rings; i++) { > ring =3D memif_get_ring(pmd, proc_private, > MEMIF_RING_S2M, i); > - ring->head =3D 0; > - ring->tail =3D 0; > + __atomic_store_n(&ring->head, 0, __ATOMIC_RELAXED); > + __atomic_store_n(&ring->tail, 0, __ATOMIC_RELAXED); > ring->cookie =3D MEMIF_COOKIE; > ring->flags =3D 0; > for (j =3D 0; j < (1 << pmd->run.log2_ring_size); j++) { > @@ -627,8 +632,8 @@ memif_init_rings(struct rte_eth_dev *dev) >=20 > for (i =3D 0; i < pmd->run.num_m2s_rings; i++) { > ring =3D memif_get_ring(pmd, proc_private, > MEMIF_RING_M2S, i); > - ring->head =3D 0; > - ring->tail =3D 0; > + __atomic_store_n(&ring->head, 0, __ATOMIC_RELAXED); > + __atomic_store_n(&ring->tail, 0, __ATOMIC_RELAXED); > ring->cookie =3D MEMIF_COOKIE; > ring->flags =3D 0; > for (j =3D 0; j < (1 << pmd->run.log2_ring_size); j++) { > @@ -734,8 +739,8 @@ memif_connect(struct rte_eth_dev *dev) > MIF_LOG(ERR, "Wrong ring"); > return -1; > } > - ring->head =3D 0; > - ring->tail =3D 0; > + __atomic_store_n(&ring->head, 0, > __ATOMIC_RELAXED); > + __atomic_store_n(&ring->tail, 0, > __ATOMIC_RELAXED); > mq->last_head =3D 0; > mq->last_tail =3D 0; > /* enable polling mode */ > @@ -750,8 +755,8 @@ memif_connect(struct rte_eth_dev *dev) > MIF_LOG(ERR, "Wrong ring"); > return -1; > } > - ring->head =3D 0; > - ring->tail =3D 0; > + __atomic_store_n(&ring->head, 0, > __ATOMIC_RELAXED); > + __atomic_store_n(&ring->tail, 0, > __ATOMIC_RELAXED); > mq->last_head =3D 0; > mq->last_tail =3D 0; > /* enable polling mode */ > -- > 2.7.4