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Tue, 28 Jul 2020 16:23:45 +0000 Received: from VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::28a3:3a4e:65ca:5707]) by VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::28a3:3a4e:65ca:5707%3]) with mapi id 15.20.3216.033; Tue, 28 Jul 2020 16:23:44 +0000 From: Phil Yang To: Viacheslav Ovsiienko CC: "matan@mellanox.com" , "rasland@mellanox.com" , "thomas@monjalon.net" , "ferruh.yigit@intel.com" , Honnappa Nagarahalli , nd , "dev@dpdk.org" , nd Thread-Topic: [dpdk-dev] [PATCH] app/testpmd: fix txonly mode timestamp intitialization Thread-Index: AQHWZCpe/3OmdULKVEGKjH29L88WFakczJ6Q Date: Tue, 28 Jul 2020 16:23:44 +0000 Message-ID: References: <1595863595-11344-1-git-send-email-viacheslavo@mellanox.com> In-Reply-To: <1595863595-11344-1-git-send-email-viacheslavo@mellanox.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: a128dfb9-5c63-4651-bd05-79eb020355b2.0 x-checkrecipientchecked: true Authentication-Results-Original: mellanox.com; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFTY:; SFS:(4636009)(136003)(396003)(376002)(346002)(39860400002)(46966005)(52536014)(9686003)(5660300002)(478600001)(33656002)(83380400001)(336012)(4326008)(2906002)(6862004)(8936002)(55016002)(47076004)(82310400002)(54906003)(7696005)(356005)(82740400003)(6506007)(53546011)(81166007)(86362001)(186003)(316002)(70586007)(26005)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2020 16:23:58.8641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8bebd9a-1301-4e35-8ea6-08d83312a1ba X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT057.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4040 Subject: Re: [dpdk-dev] [PATCH] app/testpmd: fix txonly mode timestamp intitialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Viacheslav Ovsiienko > Sent: Monday, July 27, 2020 11:27 PM > To: dev@dpdk.org > Cc: matan@mellanox.com; rasland@mellanox.com; thomas@monjalon.net; > ferruh.yigit@intel.com > Subject: [dpdk-dev] [PATCH] app/testpmd: fix txonly mode timestamp > intitialization >=20 > The testpmd application forwards data in multiple threads. > In the txonly mode the Tx timestamps must be initialized > on per thread basis to provide phase shift for the packet > burst being sent. This per thread initialization was performed > on zero value of the variable in thread local storage and > happened only once after testpmd forwarding start. Executing > "start" and "stop" commands did not cause thread local variables > zeroing and wrong timestamp values were used. I think it is too heavy to use rte_wmb() to guarantee the visibility of 'ti= mestamp_init_req' updating for subsequent read operations. We can use C11 atomics with explicit memory ordering instead of rte_wmb() t= o achieve the same goal. >=20 > Fixes: 4940344dab1d ("app/testpmd: add Tx scheduling command") >=20 > Signed-off-by: Viacheslav Ovsiienko > --- > app/test-pmd/txonly.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) >=20 > diff --git a/app/test-pmd/txonly.c b/app/test-pmd/txonly.c > index 97f4a45..415431d 100644 > --- a/app/test-pmd/txonly.c > +++ b/app/test-pmd/txonly.c > @@ -55,9 +55,13 @@ > static struct rte_udp_hdr pkt_udp_hdr; /**< UDP header of tx packets. */ > RTE_DEFINE_PER_LCORE(uint64_t, timestamp_qskew); > /**< Timestamp offset per queue */ > +RTE_DEFINE_PER_LCORE(uint32_t, timestamp_idone); /**< Timestamp init > done. */ > + > static uint64_t timestamp_mask; /**< Timestamp dynamic flag mask */ > static int32_t timestamp_off; /**< Timestamp dynamic field offset */ > static bool timestamp_enable; /**< Timestamp enable */ > +static volatile uint32_t timestamp_init_req; If we use C11 atomic builtins for 'timestamp_init_req' accessing, the volat= ile key word becomes unnecessary. Because they will generate same instructions. > + /**< Timestamp initialization request. */ > static uint64_t timestamp_initial[RTE_MAX_ETHPORTS]; >=20 > static void > @@ -229,7 +233,8 @@ > rte_be64_t ts; > } timestamp_mark; >=20 > - if (unlikely(!skew)) { > + if (unlikely(timestamp_init_req !=3D if (unlikely(__atomic_load_n(×tamp_init_req, __ATOMIC_RELAXED) !=3D > + RTE_PER_LCORE(timestamp_idone))) { > struct rte_eth_dev *dev =3D &rte_eth_devices[fs- > >tx_port]; > unsigned int txqs_n =3D dev->data->nb_tx_queues; > uint64_t phase =3D tx_pkt_times_inter * fs->tx_queue > / > @@ -241,6 +246,7 @@ > skew =3D timestamp_initial[fs->tx_port] + > tx_pkt_times_inter + phase; > RTE_PER_LCORE(timestamp_qskew) =3D skew; > + RTE_PER_LCORE(timestamp_idone) =3D > timestamp_init_req; RTE_PER_LCORE(timestamp_idone) =3D __atomic_load_n(×tamp_init_req, __A= TOMIC_RELAXED); > } > timestamp_mark.pkt_idx =3D rte_cpu_to_be_16(idx); > timestamp_mark.queue_idx =3D rte_cpu_to_be_16(fs- > >tx_queue); > @@ -426,6 +432,9 @@ > timestamp_mask && > timestamp_off >=3D 0 && > !rte_eth_read_clock(pi, ×tamp_initial[pi]); > + if (timestamp_enable) > + timestamp_init_req++; __atomic_add_fetch(×tamp_init_req, 1, __ATOMIC_ACQ_REL); > + rte_wmb(); We can remove it now. Thanks, Phil