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From: Phil Yang <Phil.Yang@arm.com>
To: "matan@mellanox.com" <matan@mellanox.com>, "shahafs@mellanox.com"
<shahafs@mellanox.com>, "viacheslavo@mellanox.com" <viacheslavo@mellanox.com>
CC: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"drc@linux.vnet.ibm.com" <drc@linux.vnet.ibm.com>, nd <nd@arm.com>, Phil Yang
<Phil.Yang@arm.com>, "dev@dpdk.org" <dev@dpdk.org>, nd <nd@arm.com>
Thread-Topic: [dpdk-dev] [PATCH v3] net/mlx5: relaxed ordering for
multi-packet RQ buffer refcnt
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Date: Mon, 13 Jul 2020 03:02:27 +0000
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Subject: Re: [dpdk-dev] [PATCH v3] net/mlx5: relaxed ordering for
multi-packet RQ buffer refcnt
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Sender: "dev" <dev-bounces@dpdk.org>
Hi,
We are also doing C11 atomics converting for other components.
Your insight would be much appreciated.
Thanks,
Phil Yang
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Phil Yang
> Sent: Tuesday, June 23, 2020 4:27 PM
> To: dev@dpdk.org
> Cc: matan@mellanox.com; shahafs@mellanox.com;
> viacheslavo@mellanox.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; drc@linux.vnet.ibm.com; nd
> <nd@arm.com>
> Subject: [dpdk-dev] [PATCH v3] net/mlx5: relaxed ordering for multi-packe=
t
> RQ buffer refcnt
>=20
> Use c11 atomics with explicit ordering instead of the rte_atomic ops
> which enforce unnecessary barriers on aarch64.
>=20
> Signed-off-by: Phil Yang <phil.yang@arm.com>
> ---
> v3:
> Split from the patchset:
> http://patchwork.dpdk.org/cover/68159/
>=20
> drivers/net/mlx5/mlx5_rxq.c | 2 +-
> drivers/net/mlx5/mlx5_rxtx.c | 16 +++++++++-------
> drivers/net/mlx5/mlx5_rxtx.h | 2 +-
> 3 files changed, 11 insertions(+), 9 deletions(-)
>=20
> diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
> index dda0073..7f487f1 100644
> --- a/drivers/net/mlx5/mlx5_rxq.c
> +++ b/drivers/net/mlx5/mlx5_rxq.c
> @@ -1545,7 +1545,7 @@ mlx5_mprq_buf_init(struct rte_mempool *mp,
> void *opaque_arg,
>=20
> memset(_m, 0, sizeof(*buf));
> buf->mp =3D mp;
> - rte_atomic16_set(&buf->refcnt, 1);
> + __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
> for (j =3D 0; j !=3D strd_n; ++j) {
> shinfo =3D &buf->shinfos[j];
> shinfo->free_cb =3D mlx5_mprq_buf_free_cb;
> diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
> index e4106bf..f0eda88 100644
> --- a/drivers/net/mlx5/mlx5_rxtx.c
> +++ b/drivers/net/mlx5/mlx5_rxtx.c
> @@ -1595,10 +1595,11 @@ mlx5_mprq_buf_free_cb(void *addr
> __rte_unused, void *opaque)
> {
> struct mlx5_mprq_buf *buf =3D opaque;
>=20
> - if (rte_atomic16_read(&buf->refcnt) =3D=3D 1) {
> + if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) =3D=3D 1) {
> rte_mempool_put(buf->mp, buf);
> - } else if (rte_atomic16_add_return(&buf->refcnt, -1) =3D=3D 0) {
> - rte_atomic16_set(&buf->refcnt, 1);
> + } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
> + __ATOMIC_RELAXED) =3D=3D 0)) {
> + __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
> rte_mempool_put(buf->mp, buf);
> }
> }
> @@ -1678,7 +1679,8 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct
> rte_mbuf **pkts, uint16_t pkts_n)
>=20
> if (consumed_strd =3D=3D strd_n) {
> /* Replace WQE only if the buffer is still in use. */
> - if (rte_atomic16_read(&buf->refcnt) > 1) {
> + if (__atomic_load_n(&buf->refcnt,
> + __ATOMIC_RELAXED) > 1) {
> mprq_buf_replace(rxq, rq_ci & wq_mask,
> strd_n);
> /* Release the old buffer. */
> mlx5_mprq_buf_free(buf);
> @@ -1790,9 +1792,9 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct
> rte_mbuf **pkts, uint16_t pkts_n)
> void *buf_addr;
>=20
> /* Increment the refcnt of the whole chunk. */
> - rte_atomic16_add_return(&buf->refcnt, 1);
> - MLX5_ASSERT((uint16_t)rte_atomic16_read(&buf-
> >refcnt) <=3D
> - strd_n + 1);
> + __atomic_add_fetch(&buf->refcnt, 1,
> __ATOMIC_ACQUIRE);
> + MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
> + __ATOMIC_RELAXED) <=3D strd_n + 1);
> buf_addr =3D RTE_PTR_SUB(addr,
> RTE_PKTMBUF_HEADROOM);
> /*
> * MLX5 device doesn't use iova but it is necessary in
> a
> diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
> index 26621ff..0fc15f3 100644
> --- a/drivers/net/mlx5/mlx5_rxtx.h
> +++ b/drivers/net/mlx5/mlx5_rxtx.h
> @@ -78,7 +78,7 @@ struct rxq_zip {
> /* Multi-Packet RQ buffer header. */
> struct mlx5_mprq_buf {
> struct rte_mempool *mp;
> - rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
> + uint16_t refcnt; /* Atomically accessed refcnt. */
> uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first
> packet. */
> struct rte_mbuf_ext_shared_info shinfos[];
> /*
> --
> 2.7.4