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Fri, 12 Jul 2019 20:09:50 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::a89e:33:fbda:ed35]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::a89e:33:fbda:ed35%4]) with mapi id 15.20.2073.012; Fri, 12 Jul 2019 20:09:49 +0000 From: Honnappa Nagarahalli To: "Ruifeng Wang (Arm Technology China)" , "vladimir.medvedkin@intel.com" , "bruce.richardson@intel.com" CC: "dev@dpdk.org" , "Gavin Hu (Arm Technology China)" , nd , "Ruifeng Wang (Arm Technology China)" , Honnappa Nagarahalli , nd Thread-Topic: [PATCH v5 6/6] lib/lpm: data update optimization for v20 Thread-Index: AQHVOF9cTpQ6xtINcUy32ylicZzaVqbHan+g Date: Fri, 12 Jul 2019 20:09:49 +0000 Message-ID: References: <20190605055451.30473-1-ruifeng.wang@arm.com> <20190712030923.37832-1-ruifeng.wang@arm.com> <20190712030923.37832-7-ruifeng.wang@arm.com> In-Reply-To: <20190712030923.37832-7-ruifeng.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: ea60df52-cd6f-4850-8fbe-cce469d6ba1d.0 x-checkrecipientchecked: true authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5088; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: rJ9RaZmcZpFTJ3tJeJG/HL1hmTvmkovVNdP77LBAuYM5ndaZixRy6R9EUz/VXUDQDiiFBlEdI5tXVORgNtloiFBzmxffomNJqX6Itqye8QSOEBh1LAUwlKB3ddYl0ZjXVv4pS14VG3kUBJINuJ7Z8/BXPICsWpY8x9HiuGKS1Af+q6g2VZQHYi1KmcOsdl9OkTZiHdb9jo9BLMn30aJLPgJMIXwm8yHBzwsnogROW63QN+lYbHG/97FfqQ2UlNxl+VFqnEgvVCxdpcU6u4CqxkvnWyJRGGNf51We0oTIXk1jUx+V+cKVh3lVPSF/lFHOwo/kuYB3lLoSTbBz//uSsin5PusLoP4nz9atFh3Z+B5ONxEhRvanPiyfbJFUCzzich9QDM0+IgdxAX+yMEEo8B9rWrV3lXxtDXMk7e6Z+ME= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 69faf382-0bac-405f-3ae6-08d70704e505 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jul 2019 20:09:49.8614 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Honnappa.Nagarahalli@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5088 Subject: Re: [dpdk-dev] [PATCH v5 6/6] lib/lpm: data update optimization for v20 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Similar to 5/6, this patch can also be merged into 4/6. > -----Original Message----- > From: Ruifeng Wang > Sent: Thursday, July 11, 2019 10:09 PM > To: vladimir.medvedkin@intel.com; bruce.richardson@intel.com > Cc: dev@dpdk.org; Honnappa Nagarahalli ; > Gavin Hu (Arm Technology China) ; nd ; > Ruifeng Wang (Arm Technology China) > Subject: [PATCH v5 6/6] lib/lpm: data update optimization for v20 >=20 > The table entries were updated field by field. There were two issues: > 1. bitwise operations are read-modify-write sequences and not atomic, > nor efficient. > 2. the above non-atomic operations causes entries out of synchronization > and inconsistency. > This patch combines the fields into a one-go 32bit entry update to avoid > inconsistency and as a bonus save CPU cycles. >=20 > Suggested-by: Gavin Hu > Signed-off-by: Ruifeng Wang > Reviewed-by: Gavin Hu > --- > lib/librte_lpm/rte_lpm.c | 35 +++++++++++++++++++++++++---------- > 1 file changed, 25 insertions(+), 10 deletions(-) >=20 > diff --git a/lib/librte_lpm/rte_lpm.c b/lib/librte_lpm/rte_lpm.c index > d86248713..95e2f75aa 100644 > --- a/lib/librte_lpm/rte_lpm.c > +++ b/lib/librte_lpm/rte_lpm.c > @@ -906,9 +906,14 @@ add_depth_big_v20(struct rte_lpm_v20 *lpm, > uint32_t ip_masked, uint8_t depth, >=20 > /* Set tbl8 entry. */ > for (i =3D tbl8_index; i < (tbl8_index + tbl8_range); i++) { > - lpm->tbl8[i].depth =3D depth; > - lpm->tbl8[i].next_hop =3D next_hop; > - lpm->tbl8[i].valid =3D VALID; > + struct rte_lpm_tbl_entry_v20 new_tbl8_entry =3D { > + .valid =3D VALID, > + .depth =3D depth, > + .valid_group =3D lpm->tbl8[i].valid_group, > + }; > + new_tbl8_entry.next_hop =3D next_hop; > + __atomic_store(&lpm->tbl8[i], &new_tbl8_entry, > + __ATOMIC_RELAXED); > } >=20 > /* > @@ -943,19 +948,29 @@ add_depth_big_v20(struct rte_lpm_v20 *lpm, > uint32_t ip_masked, uint8_t depth, >=20 > /* Populate new tbl8 with tbl24 value. */ > for (i =3D tbl8_group_start; i < tbl8_group_end; i++) { > - lpm->tbl8[i].valid =3D VALID; > - lpm->tbl8[i].depth =3D lpm->tbl24[tbl24_index].depth; > - lpm->tbl8[i].next_hop =3D > - lpm->tbl24[tbl24_index].next_hop; > + struct rte_lpm_tbl_entry_v20 new_tbl8_entry =3D { > + .valid =3D VALID, > + .depth =3D lpm->tbl24[tbl24_index].depth, > + .valid_group =3D lpm->tbl8[i].valid_group, > + }; > + new_tbl8_entry.next_hop =3D > + lpm->tbl24[tbl24_index].next_hop; > + __atomic_store(&lpm->tbl8[i], &new_tbl8_entry, > + __ATOMIC_RELAXED); > } >=20 > tbl8_index =3D tbl8_group_start + (ip_masked & 0xFF); >=20 > /* Insert new rule into the tbl8 entry. */ > for (i =3D tbl8_index; i < tbl8_index + tbl8_range; i++) { > - lpm->tbl8[i].valid =3D VALID; > - lpm->tbl8[i].depth =3D depth; > - lpm->tbl8[i].next_hop =3D next_hop; > + struct rte_lpm_tbl_entry_v20 new_tbl8_entry =3D { > + .valid =3D VALID, > + .depth =3D depth, > + .valid_group =3D lpm->tbl8[i].valid_group, > + }; > + new_tbl8_entry.next_hop =3D next_hop; > + __atomic_store(&lpm->tbl8[i], &new_tbl8_entry, > + __ATOMIC_RELAXED); > } >=20 > /* > -- > 2.17.1