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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2927 Subject: Re: [dpdk-dev] [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa outbound sqn update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > Subject: RE: [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa > > > outbound sqn update > > > > > > Hi Phil, > > > > > > > > > > > For SA outbound packets, rte_atomic64_add_return is used to > > > > generate SQN atomically. This introduced an unnecessary full > > > > barrier by calling the '__sync' builtin implemented rte_atomic_XX > > > > API on aarch64. This patch optimized it with c11 atomic and > > > > eliminated the expensive barrier for aarch64. > > > > > > > > Signed-off-by: Phil Yang > > > > Reviewed-by: Ruifeng Wang > > > > Reviewed-by: Gavin Hu > > > > --- > > > > lib/librte_ipsec/ipsec_sqn.h | 3 ++- > > > > lib/librte_ipsec/sa.h | 2 +- > > > > 2 files changed, 3 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/lib/librte_ipsec/ipsec_sqn.h > > > > b/lib/librte_ipsec/ipsec_sqn.h index 0c2f76a..e884af7 100644 > > > > --- a/lib/librte_ipsec/ipsec_sqn.h > > > > +++ b/lib/librte_ipsec/ipsec_sqn.h > > > > @@ -128,7 +128,8 @@ esn_outb_update_sqn(struct rte_ipsec_sa *sa, > > > > uint32_t *num) > > > > > > > > n =3D *num; > > > > if (SQN_ATOMIC(sa)) > > > > - sqn =3D (uint64_t)rte_atomic64_add_return(&sa- > > > >sqn.outb.atom, n); > > > > + sqn =3D __atomic_add_fetch(&sa->sqn.outb.atom, n, > > > > + __ATOMIC_RELAXED); > > > > > > One generic thing to note: > > > clang for i686 in some cases will generate a proper function call > > > for 64-bit __atomic builtins (gcc seems to always generate cmpxchng8b= for > such cases). > > > Does anyone consider it as a potential problem? > > > It probably not a big deal, but would like to know broader opinion. > > I had looked at this some time back for GCC. The function call is > > generated only if the underlying platform does not support the atomic > instructions for the operand size. Otherwise, gcc generates the instructi= ons > directly. > > I would think the behavior would be the same for clang. >=20 > From what I see not really. > As an example: >=20 > $ cat tatm11.c > #include >=20 > struct x { > uint64_t v __attribute__((aligned(8))); }; >=20 > uint64_t > ffxadd1(struct x *x, uint32_t n, uint32_t m) { > return __atomic_add_fetch(&x->v, n, __ATOMIC_RELAXED); } >=20 > uint64_t > ffxadd11(uint64_t *v, uint32_t n, uint32_t m) { > return __atomic_add_fetch(v, n, __ATOMIC_RELAXED); } >=20 > gcc for i686 will generate code with cmpxchng8b for both cases. > clang will generate cmpxchng8b for ffxadd1() - when data is explicitly 8B > aligned, but will emit a function call for ffxadd11(). Does it require libatomic to be linked in this case? Clang documentation ca= lls out unaligned case where it would generate the function call [1]. On aarch64, the atomic instructions need the address to be aligned. [1] https://clang.llvm.org/docs/Toolchain.html#atomics-library >=20 > > > > > > > > > else { > > > > sqn =3D sa->sqn.outb.raw + n; > > > > sa->sqn.outb.raw =3D sqn; > > > > diff --git a/lib/librte_ipsec/sa.h b/lib/librte_ipsec/sa.h index > > > > d22451b..cab9a2e 100644 > > > > --- a/lib/librte_ipsec/sa.h > > > > +++ b/lib/librte_ipsec/sa.h > > > > @@ -120,7 +120,7 @@ struct rte_ipsec_sa { > > > > */ > > > > union { > > > > union { > > > > - rte_atomic64_t atom; > > > > + uint64_t atom; > > > > uint64_t raw; > > > > } outb; > > > > > > If we don't need rte_atomic64 here anymore, then I think we can > > > collapse the union to just: > > > uint64_t outb; > > > > > > > struct { > > > > -- > > > > 2.7.4