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Wed, 5 Jun 2019 21:36:40 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::9983:2882:a24:c0b0]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::9983:2882:a24:c0b0%5]) with mapi id 15.20.1965.011; Wed, 5 Jun 2019 21:36:40 +0000 From: Honnappa Nagarahalli To: Aaron Conole , "thomas@monjalon.net" CC: "Ruifeng Wang (Arm Technology China)" , "Gavin Hu (Arm Technology China)" , Dharmik Thakkar , "jerin.jacob@caviumnetworks.com" , "yskoh@mellanox.com" , "dev@dpdk.org" , "msantana@redhat.com" , "bruce.richardson@intel.com" , Honnappa Nagarahalli , nd , nd Thread-Topic: DPDK compilation on arm is failing in Travis Thread-Index: AQHVG8wkMMMcaZRnn0ybtprtxInSOKaNdbmHgAAGj4CAAA8jI4AAAJnAgAAHziA= Date: Wed, 5 Jun 2019 21:36:40 +0000 Message-ID: References: <18576498.0Zn3BvHS7Y@xps> <74282465.H2CcKukIUE@xps> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 75a1feb1-0935-4dd5-bc1a-af551d6fb415.0 x-checkrecipientchecked: true authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4752; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: rdj2bDQ6/oH61FscO2OXPZDKLqvdWMEfV5crEfGwlUfwAXq5duHZQtLeWBpxv/QJiMqIPIZ1MI7Cm9R6Ug4AAu0PmOi7H/IczvnVRPxnmrgjtkwI796EyXxPD2BJ2pzweWWBsCxpr84e+mfm2/FRrpGBv9dxKYltL1tW9WsxdAjFsd5u2Mc2AKsM9b+q5F3vUDBT1pmBgyABOkq+9i/lIuZdLs8qCrLE3DpXtlukkNWuBnnTytN3syFog+JM+PmjG9DYMRbaBEDEXQmDyTLNBFAfMgRNWnobmMlIvsbLvE8YuewmMMxYCNdzXdaj+Q9WMdP+nzA5RcxB1SFm7iOE5Q70H7fVklOutz3e7hOaJ6ctd6hJ+xGRTf4UcVuyovVFpcj8asZ4FpaTn9gjbVWTOax1VPq0+d9c2s3QWq3WwX4= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55c94e6f-af87-4b00-7c7d-08d6e9fde551 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2019 21:36:40.1185 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Honnappa.Nagarahalli@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4752 Subject: Re: [dpdk-dev] DPDK compilation on arm is failing in Travis X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > Thomas Monjalon writes: > > > > > 05/06/2019 21:40, Aaron Conole: > > >> Thomas Monjalon writes: > > >> > > >> > The compilation of the master branch is failing for aarch64: > > >> > https://travis-ci.com/DPDK/dpdk > > >> > The log is so much verbose that I am not able to understand what > > >> > is really wrong. > > >> > Please help to diagnose and fix, thanks. > > >> > > >> A discussion about this: > > >> > > >> http://mails.dpdk.org/archives/dev/2019-June/134012.html > > > > > > I see the error now. > > > It is printing the full log after the error, so I missed the error > > > at the top. > > > > > > I've read your comment about a possible error with the patch > > > removing weak functions but neither me nor Bruce were able to reprodu= ce > it. > > > What is the condition to see this compiler warning? > > > > It is only on ARM, and only when the neon intrinsics are in use. > I am not able to reproduce it from the tip of master. >=20 > I am using: > gcc (Ubuntu 8.3.0-6ubuntu1~18.04) 8.3.0 >=20 > From the log on Travis, looks like the compiler is: > gcc (Ubuntu 5.4.0-6ubuntu1~16.04.11) 5.4.0 20160609 >=20 > Is this the issue? >=20 > Why are we seeing the error now? I tested with gcc-5 (Ubuntu/Linaro 5.5.0-12ubuntu1) 5.5.0 20171010, it work= s fine. I cannot get hold of 5.4.0. Not sure if needs to be supported. Are there any issues in upgrading to 7 or 8? >=20 > > > > The issue is the vector lane setting code looks like: > > > > lval =3D lane_set(scalar, rval, lane id) > > > > In this case, 'rval' is being used before it is ever set, but it > > really could be just 0 for the first lane setting code. Thereafter, > > we use the old value of input as the rval, but each time a different la= ne is set. > > > > It would be nice if there were an intrinsic that formatted correctly > > from the start (something we could call like lval =3D > lane_set_from_array(scalar_array)). > > Then 'input' would never appear as an rval before it was set. > > > > I thought Jerin Jacob (CC'd) would have some opinion on the right fix. > > There are three 'fixes' I know exist - one is to squelch the warning > > (but I don't like it because it could hide future code that introduces > > this), one is to create a static and use assignment, one is to replace > > the first call and pass in a 0'd lane for the first one. > > > > Actually, I think I have a patch that could work to not introduce an > > assignment, but squelch the warning. Something like the following (not > tested). > > > > --- > > > > diff --git a/lib/librte_acl/acl_run_neon.h > > b/lib/librte_acl/acl_run_neon.h index 01b9766d8..37c984fef 100644 > > --- a/lib/librte_acl/acl_run_neon.h > > +++ b/lib/librte_acl/acl_run_neon.h > > @@ -165,6 +165,7 @@ search_neon_8(const struct rte_acl_ctx *ctx, const > > uint8_t **data, > > uint64_t index_array[8]; > > struct completion cmplt[8]; > > struct parms parms[8]; > > + static int32x4_t ZEROVAL; > > int32x4_t input0, input1; > > > > acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, @@ - > > 181,8 +182,8 @@ search_neon_8(const struct rte_acl_ctx *ctx, const > > uint8_t **data, > > > > while (flows.started > 0) { > > /* Gather 4 bytes of input data for each stream. */ > > - input0 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), input0, > > 0); > > - input1 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 4), input1, > > 0); > > + input0 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), > > ZEROVAL, 0); > > + input1 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 4), > > ZEROVAL, 0); > > > > input0 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input0, > 1); > > input1 =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 5), input1, > 1); @@ > > -227,6 +228,7 @@ search_neon_4(const struct rte_acl_ctx *ctx, const > > uint8_t **data, > > uint64_t index_array[4]; > > struct completion cmplt[4]; > > struct parms parms[4]; > > + static int32x4_t ZEROVAL; > > int32x4_t input; > > > > acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, @@ - > > 242,7 +244,7 @@ search_neon_4(const struct rte_acl_ctx *ctx, const > > uint8_t **data, > > > > while (flows.started > 0) { > > /* Gather 4 bytes of input data for each stream. */ > > - input =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), input, 0); > > + input =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), > > ZEROVAL, 0); > > input =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input, 1); > > input =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 2), input, 2); > > input =3D vsetq_lane_s32(GET_NEXT_4BYTES(parms, 3), input, 3); > > -- > > 2.21.0