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From: Shreyansh Jain <shreyansh.jain@nxp.com>
To: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
	"Ruifeng Wang (Arm Technology China)" <Ruifeng.Wang@arm.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer pool per	port
Date: Tue, 16 Apr 2019 12:47:58 +0000	[thread overview]
Message-ID: <VI1PR04MB4688EEF4D7D4D8D478E4AFEB90240@VI1PR04MB4688.eurprd04.prod.outlook.com> (raw)

Hello Ananyev,

> Hi Shreyansh,
> 
> > > > I tried this patch on MacchiatoBin + 82599 NIC.
> > > > Compared with global-pool mode, per-port-pool mode showed slightly
> > > lower performance in single core test.
> > >
> > > That was my thought too - for the case when queues from multiple
> ports
> > > are handled by the same core
> > > it probably would only slowdown things.
> >
> > Thanks for your comments.
> >
> > This is applicable for cases where separate cores can handle separate
> ports - each with their pools. (somehow I felt that message in commit
> > was adequate - I can rephrase if that is misleading)
> >
> > In case there is enough number of cores available for datapath, such
> segregation can result in better performance - possibly because of
> > drop in pool and cache conflicts.
> > At least on some of NXP SoC, this resulted in over 15% improvement.
> > And, in other cases it didn't lead to any drop/negative-impact.
> 
> If each core manages just one port, then yes definitely performance
> increase is expected.
> If that's the case you'd like enable, then can I suggest to have mempool
> per lcore not per port?

As you have stated below, it's just the same thing with two different views.

> I think it would be plausible for both cases:
> - one port per core (your case).
> - multiple ports per core.

Indeed. For this particular patch, I just chose the first one. Probably because that is the most general use-case I come across.
I am sure the second too has equal number of possible use-cases - but probably someone with access to that kind of scenario would be better suited for validating what is the performance increase.
Do you think it would be OK to have that in and then sometime in future enable the second option?

[...]

-
Shreyansh

             reply	other threads:[~2019-04-16 12:48 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-16 12:47 Shreyansh Jain [this message]
2019-04-16 12:47 ` Shreyansh Jain
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-16 12:54   ` Ananyev, Konstantin
  -- strict thread matches above, loose matches on Subject: below --
2019-04-16 16:00 Shreyansh Jain
2019-04-16 16:00 ` Shreyansh Jain
2019-04-17 11:21 ` Ananyev, Konstantin
2019-04-17 11:21   ` Ananyev, Konstantin
2019-04-15 10:29 Shreyansh Jain
2019-04-15 10:29 ` Shreyansh Jain
2019-04-15  6:48 Shreyansh Jain
2019-04-15  6:48 ` Shreyansh Jain
2019-04-15  7:58 ` Ruifeng Wang (Arm Technology China)
2019-04-15  7:58   ` Ruifeng Wang (Arm Technology China)
2019-01-03 11:30 Shreyansh Jain
2019-04-04 11:54 ` Hemant Agrawal
2019-04-04 11:54   ` Hemant Agrawal
2019-04-08  6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08  6:10   ` Ruifeng Wang (Arm Technology China)
2019-04-08  9:29   ` Ananyev, Konstantin
2019-04-08  9:29     ` Ananyev, Konstantin
2019-04-12  9:24     ` Shreyansh Jain
2019-04-12  9:24       ` Shreyansh Jain
2019-04-14  9:13       ` Ruifeng Wang (Arm Technology China)
2019-04-14  9:13         ` Ruifeng Wang (Arm Technology China)
2019-04-15 12:05       ` Ananyev, Konstantin
2019-04-15 12:05         ` Ananyev, Konstantin

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