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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(376002)(346002)(39860400002)(136003)(396003)(46966005)(966005)(8936002)(316002)(8676002)(356005)(110136005)(336012)(54906003)(478600001)(186003)(82740400003)(81166007)(6636002)(26005)(2906002)(55016002)(5660300002)(9686003)(53546011)(47076004)(4326008)(70206006)(6506007)(33656002)(70586007)(83380400001)(7696005)(52536014)(82310400003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2020 13:03:54.3884 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ac5c4e2-9723-4a69-5903-08d892d4e4f9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6311 Subject: Re: [dpdk-dev] [PATCH v2 1/2] eal/arm: fix gcc build for optimization level 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Ruifeng Wang > Sent: Friday, November 27, 2020 6:15 PM > To: jerinj@marvell.com; Ruifeng Wang ; > Honnappa Nagarahalli > Cc: dev@dpdk.org; nd ; Feifei Wang > > Subject: [PATCH v2 1/2] eal/arm: fix gcc build for optimization level 0 >=20 > Gcc build with '-O0' on platforms with RTE_ARM_FEATURE_ATOMICS set > failed for: > ../lib/librte_efd/rte_efd.c > Assembler messages: > 3866: Error: selected processor does not support `crc32cb w0,w0,w1' > 3890: Error: selected processor does not support `crc32ch w0,w0,w1' > 3914: Error: selected processor does not support `crc32cw w0,w0,w1' > 3938: Error: selected processor does not support `crc32cx w0,w0,x1' >=20 > This was caused by an architecture specifier added for Clang. > Unlike Clang, Gcc considers each inline assembly block to be dependent an= d > therefore, the architecture specifier impacts assemble of some blocks > require certain extension support. >=20 > Used arch_extension instead to not override architecture. > Referred for [1] to fix the issue. >=20 > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit= /?i > d=3Ddd1f6308b28edf0452dd5dc7877992903ec61e69 >=20 > Fixes: 8fce34cd0a6a ("eal/arm: fix clang build of native target") >=20 > Reported-by: Feifei Wang > Signed-off-by: Ruifeng Wang > --- > v2: > New approach to use arch_extension instead. >=20 > lib/librte_eal/arm/include/rte_atomic_64.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h > b/lib/librte_eal/arm/include/rte_atomic_64.h > index 7fcd17466..6584bc38c 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > @@ -46,7 +46,7 @@ rte_atomic_thread_fence(int memorder) > /*------------------------ 128 bit atomic operations -------------------= ------*/ >=20 > #if defined(__ARM_FEATURE_ATOMICS) || > defined(RTE_ARM_FEATURE_ATOMICS) > -#define __LSE_PREAMBLE ".arch armv8-a+lse\n" > +#define __LSE_PREAMBLE ".arch_extension lse\n" This approach has issue on earlier version Clang (eg. clang-6). I think it is better to take approach in v1. >=20 > #define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > static __rte_noinline rte_int128_t = \ > -- > 2.20.1