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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(346002)(39840400004)(396003)(376002)(46966005)(36906005)(2906002)(55016002)(478600001)(966005)(82310400003)(110136005)(54906003)(81166007)(47076004)(316002)(70206006)(70586007)(356005)(86362001)(336012)(5660300002)(53546011)(33656002)(52536014)(4326008)(186003)(26005)(8676002)(9686003)(83080400001)(83380400001)(6506007)(7696005)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2020 10:22:06.3355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d48519aa-c209-4982-2324-08d86d0656af X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5861 Subject: Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: > -----Original Message----- > From: dev On Behalf Of Harry van Haaren > Sent: Monday, September 14, 2020 11:10 PM > To: dev@dpdk.org > Cc: pbhagavatula@marvell.com; Harry van Haaren > > Subject: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants >=20 > This commit adds a new rte_prefetch0_write() variants, suggesting to the > compiler to use a prefetch instruction with intention to write. As a comp= iler > builtin, the compiler can choose based on compilation target what the bes= t > implementation for this instruction is. >=20 > Signed-off-by: Harry van Haaren >=20 > --- >=20 > v2: > - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan) >=20 > The integer constants passed to the builtin are not available as a #defin= e > value, and doing #defines just for this write variant does not seems a ni= ce > solution to me... particularly for those using IDEs where any #define val= ue is > auto-hinted for code-completion. > --- > lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) >=20 > diff --git a/lib/librte_eal/include/generic/rte_prefetch.h > b/lib/librte_eal/include/generic/rte_prefetch.h > index 6e47bdfbad..3dfca77a74 100644 > --- a/lib/librte_eal/include/generic/rte_prefetch.h > +++ b/lib/librte_eal/include/generic/rte_prefetch.h > @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *= p); > */ > static inline void rte_prefetch_non_temporal(const volatile void *p); >=20 > +/** > + * Prefetch a cache line into all cache levels, with intention to > +write. This > + * prefetch variant hints to the CPU that the program is expecting to > +write to > + * the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch0_write(const void *p) { > + /* 1 indicates intention to write, 3 sets target cache level to L1. See > + * GCC docs where these integer constants are described in more > detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 3); > +} > + > +/** > + * Prefetch a cache line into all cache levels, except the 0th, with > +intention > + * to write. This prefetch variant hints to the CPU that the program is > + * expecting to write to the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch1_write(const void *p) { > + /* 1 indicates intention to write, 2 sets target cache level to L2. See > + * GCC docs where these integer constants are described in more > detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 2); > +} > + > +/** > + * Prefetch a cache line into all cache levels, except the 0th and 1st, > +with > + * intention to write. This prefetch variant hints to the CPU that the > +program > + * is expecting to write to the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch2_write(const void *p) { > + /* 1 indicates intention to write, 1 sets target cache level to L3. See > + * GCC docs where these integer constants are described in more > detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 1); > +} > + > + > #endif /* _RTE_PREFETCH_H_ */ > -- > 2.17.1 Reviewed-by: Ruifeng Wang