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Thu, 20 Dec 2018 01:01:05 +0000 From: "Gavin Hu (Arm Technology China)" To: "Ananyev, Konstantin" , "Joyce Kong (Arm Technology China)" , "dev@dpdk.org" CC: nd , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , Honnappa Nagarahalli , "stable@dpdk.org" , "chaozhu@linux.vnet.ibm.com" , "jerinj@marvell.com" , nd Thread-Topic: [dpdk-dev] [PATCH v1 1/2] test/rwlock: add perf test case Thread-Index: AQHUkpU+tvfytW5el0WAjOS1oBMpNKWGwbsAgAAXKIA= Date: Thu, 20 Dec 2018 01:01:05 +0000 Message-ID: References: <1544672265-219262-1-git-send-email-joyce.kong@arm.com> <1544672265-219262-2-git-send-email-joyce.kong@arm.com> <2601191342CEEE43887BDE71AB977258010D8BCD43@IRSMSX106.ger.corp.intel.com> In-Reply-To: <2601191342CEEE43887BDE71AB977258010D8BCD43@IRSMSX106.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR08MB0607; H:VI1PR08MB3167.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: UgBbuyslb0jM/zkOsiQIYLXNOA3CLoytcfRYPaHEWJ/ZaWul7Qn2q1bteUWqbLMuKcvgAgNBZaBAOJP2fs16AKW1Ub25oX0itjnf6jNmfqIWyxEMlUuSXrqqD/7wJpOt1vk0jW0K39GsglWLJcnu7QKZB4OipQT7tUyMkjmw5UOuvFKuavGtZYSXQFECrc1w3Tli3eLNzXF1SPw6DglUOGrL5t/BYNV6xIcpvYWifj1OR3pCrmbdyhl6CslshKwWcMnT4WJZZ8TTyic19Y4mDKw8bq+A8j6IJS3NRyJ9EuIzqTS/cvD7eHSHv48oKn62 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 562df5a5-6bfc-4a7a-92ae-08d666169eab X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2018 01:01:05.5741 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB0607 Subject: Re: [dpdk-dev] [PATCH v1 1/2] test/rwlock: add perf test case X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2018 01:01:09 -0000 > -----Original Message----- > From: Ananyev, Konstantin > Sent: Thursday, December 20, 2018 7:35 AM > To: Joyce Kong (Arm Technology China) ; > dev@dpdk.org > Cc: nd ; thomas@monjalon.net; > jerin.jacob@caviumnetworks.com; hemant.agrawal@nxp.com; Honnappa > Nagarahalli ; Gavin Hu (Arm Technology > China) ; stable@dpdk.org > Subject: RE: [dpdk-dev] [PATCH v1 1/2] test/rwlock: add perf test case >=20 >=20 > Hi, >=20 > > > > Add performance test on all available cores to benchmark the scaling > > up performance and fairness of rw_lock. > > > > Fixes: af75078faf ("first public release") > > Cc: stable@dpdk.org > > > > Suggested-by: Gavin Hu > > Signed-off-by: Joyce Kong > > Reviewed-by: Honnappa Nagarahalli > > Reviewed-by: Ola Liljedahl > > Reviewed-by: Gavin Hu > > Reviewed-by: Ruifeng Wang > > --- > > test/test/test_rwlock.c | 71 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 71 insertions(+) > > > > diff --git a/test/test/test_rwlock.c b/test/test/test_rwlock.c index > > 29171c4..4766c09 100644 > > --- a/test/test/test_rwlock.c > > +++ b/test/test/test_rwlock.c > > @@ -4,6 +4,7 @@ > > > > #include > > #include > > +#include > > #include > > #include > > > > @@ -44,6 +45,7 @@ > > > > static rte_rwlock_t sl; > > static rte_rwlock_t sl_tab[RTE_MAX_LCORE]; > > +static rte_atomic32_t synchro; > > > > static int > > test_rwlock_per_core(__attribute__((unused)) void *arg) @@ -65,6 > > +67,72 @@ test_rwlock_per_core(__attribute__((unused)) void *arg) > > return 0; > > } > > > > +static rte_rwlock_t lk =3D RTE_RWLOCK_INITIALIZER; static uint64_t > > +lock_count[RTE_MAX_LCORE] =3D {0}; > > + > > +#define TIME_MS 100 > > + > > +static int > > +load_loop_fn(__attribute__((unused)) void *arg) { > > + uint64_t time_diff =3D 0, begin; > > + uint64_t hz =3D rte_get_timer_hz(); > > + uint64_t lcount =3D 0; > > + const unsigned int lcore =3D rte_lcore_id(); > > + > > + /* wait synchro for slaves */ > > + if (lcore !=3D rte_get_master_lcore()) > > + while (rte_atomic32_read(&synchro) =3D=3D 0) > > + ; > > + > > + begin =3D rte_rdtsc_precise(); > > + while (time_diff < hz * TIME_MS / 1000) { > > + rte_rwlock_write_lock(&lk); > > + rte_pause(); >=20 > Wouldn't it be more realistic to write/read some shared data here? > Again extra checking could be done in that case that lock behaves as > expected. Will do it in v2, thanks! >=20 > > + rte_rwlock_write_unlock(&lk); > > + rte_rwlock_read_lock(&lk); > > + rte_rwlock_read_lock(&lk); >=20 > Wonder what is the point of double rdlock here? > Konstantin Double rd lock is to check rd locks will not block each other.=20 Anyway I will remove it in v2 if no concerns here. >=20 > > + rte_pause(); > > + rte_rwlock_read_unlock(&lk); > > + rte_rwlock_read_unlock(&lk); > > + lcount++; > > + /* delay to make lock duty cycle slightly realistic */ > > + rte_pause(); > > + time_diff =3D rte_rdtsc_precise() - begin; > > + } > > + lock_count[lcore] =3D lcount; > > + return 0; > > +} > > +