From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6EFCBA0A0C; Thu, 13 May 2021 12:04:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3ECB4067E; Thu, 13 May 2021 12:04:38 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 817B14003F for ; Thu, 13 May 2021 12:04:37 +0200 (CEST) IronPort-SDR: QAao6HDeQJplAxT9IdzS41+jG6Mi40BK1LFb9i8ZgTB+s8cXK/AsD8d6Lh/uF88G5oB3+qDsyP 0q1J+DFPhMUg== X-IronPort-AV: E=McAfee;i="6200,9189,9982"; a="199970787" X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="199970787" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 03:04:35 -0700 IronPort-SDR: 6DCUIBVTPMrVqBfIMWBsONfZ0gKgGZD6Ovgdm4FNEejkdYmXswEpA8+B/ELw6rcLxioazMKBKx HfCzqW6pcEfg== X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="400873718" Received: from bricha3-mobl.ger.corp.intel.com ([10.252.3.207]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 13 May 2021 03:04:32 -0700 Date: Thu, 13 May 2021 11:04:27 +0100 From: Bruce Richardson To: Honnappa Nagarahalli Cc: Chengwen Feng , "thomas@monjalon.net" , "ferruh.yigit@intel.com" , "dev@dpdk.org" , "jerinj@marvell.com" , Ruifeng Wang , "viktorin@rehivetech.com" , nd Message-ID: References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1620808126-18876-3-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [dpdk-dev] [PATCH 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, May 12, 2021 at 11:12:36PM +0000, Honnappa Nagarahalli wrote: > > > > > > Currently, the SVE code is compiled only when -march supports SVE (e.g. '- > > march=armv8.2a+sve'), there maybe some problem[1] with this approach. > > > > The solution: > > a. If the minimum instruction set support SVE then compiles it. > > b. Else if the compiler support SVE then compiles it. > > c. Otherwise don't compile it. > > > > [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html > > > > Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") > > Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") > > Cc: stable@dpdk.org > > > > Signed-off-by: Chengwen Feng > > --- > > drivers/net/hns3/hns3_rxtx.c | 2 +- > > drivers/net/hns3/meson.build | 13 +++++++++++++ > > 2 files changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index > > 1d7a769..4ef20c6 100644 > > --- a/drivers/net/hns3/hns3_rxtx.c > > +++ b/drivers/net/hns3/hns3_rxtx.c > > @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) > > static bool > > hns3_get_sve_support(void) > > { > > -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) > > +#if defined(CC_SVE_SUPPORT) > > if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) > > return false; > > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) > > diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index > > 53c7df7..8563d70 100644 > > --- a/drivers/net/hns3/meson.build > > +++ b/drivers/net/hns3/meson.build > > @@ -35,7 +35,20 @@ deps += ['hash'] > > > > if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') > > sources += files('hns3_rxtx_vec.c') > > + > > + # compile SVE when: > > + # a. support SVE in minimum instruction set baseline > > + # b. it's not minimum instruction set, but compiler support > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' > > + cflags += ['-DCC_SVE_SUPPORT'] > Why is the CC_SVE_SUPPORT flag needed? The compiler has __ARM_FEATURE_SVE flag already which gets defined when '+sve" is added to '-march'. > > > sources += files('hns3_rxtx_vec_sve.c') > > + elif cc.has_argument('-march=armv8.2-a+sve') > I think this check and the above check do the same thing. i.e. both of them check if +sve flag is passed to the compiler. > This is similar to what we do for AVX on x86. The first check is indeed checking that +sve is passed to the compiler, but the second is different, and checks whether it is possible for the flag to be passed to the compiler. This second info then allows a separate C file to be compiled for that extra instruction set, and then have the functions in it run-time selected. /Bruce