From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2960AA0548; Wed, 16 Jun 2021 15:11:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C0F44067A; Wed, 16 Jun 2021 15:11:44 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id DEFF640140 for ; Wed, 16 Jun 2021 15:11:42 +0200 (CEST) IronPort-SDR: t7KpCsoSpKPFul/4BkVELdC9UJ4r+rYnCE4gsdIVoxLtaLRQVHIlH1NKUGnzx3VX0SKcdG7mPp wcdwKxRTogSg== X-IronPort-AV: E=McAfee;i="6200,9189,10016"; a="203150413" X-IronPort-AV: E=Sophos;i="5.83,278,1616482800"; d="scan'208";a="203150413" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2021 06:11:41 -0700 IronPort-SDR: k2XCzoJcfpL61fkIeoaZqmzyrQOivzlvvfSLXiaVp1j18gOUNGlCVbzyGXaxvacVexZtJYh29r JQ2+oYWz79dA== X-IronPort-AV: E=Sophos;i="5.83,278,1616482800"; d="scan'208";a="479091987" Received: from bricha3-mobl.ger.corp.intel.com ([10.252.12.169]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 16 Jun 2021 06:11:39 -0700 Date: Wed, 16 Jun 2021 14:11:36 +0100 From: Bruce Richardson To: David Marchand Cc: Chengwen Feng , Thomas Monjalon , "Yigit, Ferruh" , dev , Nipun Gupta , Hemant Agrawal , Maxime Coquelin , Honnappa Nagarahalli , Jerin Jacob Kollanukkaran , Jerin Jacob Message-ID: References: <1623763327-30987-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [dpdk-dev] [RFC PATCH] dmadev: introduce DMA device library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Jun 16, 2021 at 02:14:54PM +0200, David Marchand wrote: > On Tue, Jun 15, 2021 at 3:25 PM Chengwen Feng wrote: > > + > > +#define RTE_DMADEV_NAME_MAX_LEN (64) > > +/**< @internal Max length of name of DMA PMD */ > > + > > +/** @internal > > + * The data structure associated with each DMA device. > > + */ > > +struct rte_dmadev { > > + /**< Device ID for this instance */ > > + uint16_t dev_id; > > + /**< Functions exported by PMD */ > > + const struct rte_dmadev_ops *dev_ops; > > + /**< Device info. supplied during device initialization */ > > + struct rte_device *device; > > + /**< Driver info. supplied by probing */ > > + const char *driver_name; > > + > > + /**< Device name */ > > + char name[RTE_DMADEV_NAME_MAX_LEN]; > > +} __rte_cache_aligned; > > + > > I see no queue/channel notion. > How does a rte_dmadev object relate to a physical hw engine? > One queue, one device. When looking to update the ioat driver for 20.11 release when I added the idxd part, I considered adding a queue parameter to the API to look like one device with multiple queues. However, since each queue acts completely independently of each other, there was no benefit to doing so. It's just easier to have a single id to identify a device queue.