From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4E1AA0093; Thu, 5 May 2022 16:39:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA6094014F; Thu, 5 May 2022 16:39:27 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 4094940042 for ; Thu, 5 May 2022 16:39:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651761565; x=1683297565; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=6azmUoC3e+cJYoGiRQlbVlHMjWP50rNzjsDKWOlHiiw=; b=Huao3H36ZmM2L3+61mcWLvviMNVLBe5weTyw7+MSHSdHS544T8jMZ/pF K7drfnxL1KuecpdQZirt/YU2WvbEwr1wkTM1lQnXDulqmC32Bhcke3ZNQ zrgfrhnGDR9PoU3Ws7ce8MPchXouSaEueTq0MsxQ9Gprp38feaMJZMKDi fWgt6gU8pR2msar53Rw5LOmwkQygWIAIc4ryu+eIdKU9Oq06X53snZF1Z MR2q3SHvmXKDdaiDK7EC8FWXPusFsazRM1uDQNnXoIRO763mL8KFe6ZOM cm/jlDVoL8yZP8EGJq/tL4+O6X7XrfD81y5u4yA+iZOQTbRXukMRALShK w==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="266969475" X-IronPort-AV: E=Sophos;i="5.91,201,1647327600"; d="scan'208";a="266969475" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 07:39:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,201,1647327600"; d="scan'208";a="694683664" Received: from bricha3-mobl.ger.corp.intel.com ([10.55.133.40]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 05 May 2022 07:39:22 -0700 Date: Thu, 5 May 2022 15:39:18 +0100 From: Bruce Richardson To: Rahul Bhansali Cc: dev@dpdk.org, Ruifeng Wang , Jan Viktorin , jerinj@marvell.com Subject: Re: [PATCH 1/2] config/arm: add SVE control flag Message-ID: References: <20220505142744.1423344-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220505142744.1423344-1-rbhansali@marvell.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote: > This add the control flag for SVE to enable or disable > RTE_HAS_SVE_ACLE macro in the build. > > Signed-off-by: Rahul Bhansali > --- > config/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 8aead74086..dafb342cc6 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or > compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] > endif > > -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' > +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and > + soc_config.get('sve', true)) Please double-indent this so that it does not line up with the following lines of the block. > compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] > if (cc.check_header('arm_sve.h')) > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) > -- > 2.25.1 >