Re: [PATCH] net/cpfl: enable AVX2 for singleq Rx/Tx

[Bruce Richardson <bruce.richardson@intel.com>]

On Wed, Mar 12, 2025 at 09:22:42PM +0530, Shaiq Wani wrote:
> In case some CPUs don't support AVX512. Enable AVX2 for them to
> get better per-core performance.
> 
> The single queue model processes all packets in order while
> the split queue model separates packet data and metadata into
> different queues for parallel processing and improved performance.
> 
> Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
> ---
>  doc/guides/nics/cpfl.rst           |  3 ++-
>  drivers/net/intel/cpfl/cpfl_rxtx.c | 24 ++++++++++++++++++++++++
>  2 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst
> index 154201e745..5d267ef667 100644
> --- a/doc/guides/nics/cpfl.rst
> +++ b/doc/guides/nics/cpfl.rst
> @@ -177,7 +177,8 @@ The paths are chosen based on 2 conditions:
>  
>    On the x86 platform, the driver checks if the CPU supports AVX512.
>    If the CPU supports AVX512 and EAL argument ``--force-max-simd-bitwidth``
> -  is set to 512, AVX512 paths will be chosen.
> +  is set to 512, AVX512 paths will be chosen. Otherwise, if --force-max-simd-bitwidth is set to 256,AVX2 paths will be chosen.
> +  (Note that 256 is the default bitwidth if no specific value is provided.)
>  

The word wrapping and spacing here looks wrong. Will fix on apply.

Otherwise
Acked-by: Bruce Richardson <bruce.richardson@intel.com>