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Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> On 11/10/2021 7:48 AM, Apeksha Gupta wrote: > This patch adds Rx/Tx queue configuration setup operations. > On packet reception the respective BD Ring status bit is set > which is then used for packet processing. > > Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com> > Signed-off-by: Apeksha Gupta <apeksha.gupta@nxp.com> <...> > + > + rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_t[queue_idx]), Isn't 'fep->bd_addr_p_t[]' a 64-bit value? <...> > + > + rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_r[queue_idx]), Isn't 'fep->bd_addr_p_r[]' a 64-bit address, why doing endianness operation only on 32-bit and writing only 32-bit of it to register?