From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37FB345502; Wed, 26 Jun 2024 14:05:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B685E43481; Wed, 26 Jun 2024 13:57:19 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id C98D342E95 for ; Wed, 26 Jun 2024 13:45:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402336; x=1750938336; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mR6gc5LGwVAySXndWAjuInaVNZ1VeM7ePUDM808fPxk=; b=oF8plBJ1p9ertVTlnMzPwMEK7MaQ6EF5XozU9qzVj4pso/s0A3reAfZ7 IJKGA6TqAtCCSpb1s+Fym7ouzJwqOKo+x7rvOOyAnIY3JqsCLCZuKMBgc qiFcFk7CvGYnv5FudGxt1gJHkkPQCx5wUgtDpwQF10RiqBR6ZJYXQqGIn I4Oe1w6BTA0i4JX7qHqfMPO3AM/rAhperGqGIVcZEAoKSl+laL+Rwmsbi qQM3J0J4mAQl1PbqsL5NXfq5NGCNXdtfJ/n6yv6MmyH3zyduphgLLOw5O 7IsZVYkkZv4sXD54Z5QE2oe1msOg3yYTOxBihBBGIl8OO7D+2zp3xLZSk w==; X-CSE-ConnectionGUID: Pmwvd2ORQ+u9a8h3JWO8Tg== X-CSE-MsgGUID: nCfftX5PQoi6MDisDY+PWQ== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979581" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979581" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:35 -0700 X-CSE-ConnectionGUID: oR7zbElCQKmop8UdvV/WpQ== X-CSE-MsgGUID: yGZHQr50RimMcAhf8VFYoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874503" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:34 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Milena Olech , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 091/103] net/ice/base: remove PHY port timer bypass mode Date: Wed, 26 Jun 2024 12:42:19 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Milena Olech Previous implementation switches between bypass and Vernier mode dynamically. However bypass mode should be removed due to low precision. Signed-off-by: Milena Olech Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 195 +----------------------------- drivers/net/ice/base/ice_ptp_hw.h | 6 +- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 6 insertions(+), 197 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index bba228ed39..08ff620b34 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2214,7 +2214,6 @@ ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) * ice_start_phy_timer_eth56g - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start - * @bypass: unused, for compatibility * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is @@ -2222,7 +2221,7 @@ ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) * */ int -ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) +ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) { int err; u32 lo, hi; @@ -3926,47 +3925,6 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) return 0; } -/** - * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Calculate and program the fixed Tx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. - */ -static int -ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) -{ - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - int err; - u64 total_offset; - - err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (err) - return err; - - total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); - - /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L - * register, then indicate that the Tx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by the Vernier calibration. - */ - err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, - total_offset); - if (err) - return err; - - err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); - if (err) - return err; - - return 0; -} - /** * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx * @hw: pointer to the HW struct @@ -4277,47 +4235,6 @@ static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) return 0; } -/** - * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Calculate and program the fixed Rx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. - */ -static int -ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) -{ - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - int err; - u64 total_offset; - - err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (err) - return err; - - total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); - - /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L - * register, then indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by Vernier calibration. - */ - err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, - total_offset); - if (err) - return err; - - err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); - if (err) - return err; - - return 0; -} - /** * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct @@ -4498,20 +4415,15 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) * ice_start_phy_timer_e822 - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start - * @bypass: if true, start the PHY in bypass mode * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * - * Bypass mode enables timestamps immediately without waiting for Vernier - * calibration to complete. Hardware will still continue taking Vernier - * measurements on Tx or Rx of packets, but they will not be applied to - * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware - * has completed offset calculation. + * Hardware will take Vernier measurements on Tx or Rx of packets. */ int -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) +ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) { u32 lo, hi, val; u64 incval; @@ -4592,23 +4504,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) if (err) return err; - if (bypass) { - val |= P_REG_PS_BYPASS_MODE_M; - /* Enter BYPASS mode, enabling timestamps immediately. */ - err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (err) - return err; - - /* Program the fixed Tx offset */ - err = ice_phy_cfg_fixed_tx_offset_e822(hw, port); - if (err) - return err; - - /* Program the fixed Rx offset */ - err = ice_phy_cfg_fixed_rx_offset_e822(hw, port); - if (err) - return err; - } ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); @@ -4650,90 +4545,6 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) return 0; } -/** - * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * After hardware finishes vernier calculations for the Tx and Rx offset, this - * function can be used to exit bypass mode by updating the total Tx and Rx - * offsets, and then disabling bypass. This will enable hardware to include - * the more precise offset calibrations, increasing precision of the generated - * timestamps. - * - * This cannot be done until hardware has measured the offsets, which requires - * waiting until at least one packet has been sent and received by the device. - */ -int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port) -{ - int err; - u32 val; - - err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", - port, err); - return err; - } - - if (!(val & P_REG_TX_OV_STATUS_OV_M)) { - ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n", - port); - return ICE_ERR_NOT_READY; - } - - err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", - port, err); - return err; - } - - if (!(val & P_REG_TX_OV_STATUS_OV_M)) { - ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n", - port); - return ICE_ERR_NOT_READY; - } - - err = ice_phy_cfg_tx_offset_e822(hw, port); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, err %d\n", - port, err); - return err; - } - - err = ice_phy_cfg_rx_offset_e822(hw, port); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, err %d\n", - port, err); - return err; - } - - /* Exit bypass mode now that the offset has been updated */ - err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, err %d\n", - port, err); - return err; - } - - if (!(val & P_REG_PS_BYPASS_MODE_M)) - ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n", - port); - - val &= ~P_REG_PS_BYPASS_MODE_M; - err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, err %d\n", - port, err); - return err; - } - - ice_info(hw, "Exiting bypass mode on PHY port %u\n", port); - - return 0; -} - /* E810 functions * * The following functions operate on the E810 series devices which use diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index bd6bb3e839..aa7fd66885 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -270,11 +270,9 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port); int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); -int -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass); +int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); -int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port); /* E810 family functions */ bool ice_is_gps_present_e810t(struct ice_hw *hw); @@ -316,7 +314,7 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status); int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset); int -ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass); +ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 64ac64326a..dbdcacf019 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2518,7 +2518,7 @@ ice_dev_init(struct rte_eth_dev *dev) hw->phy_model = ICE_PHY_E822; if (hw->phy_model == ICE_PHY_E822) { - ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); + ret = ice_start_phy_timer_e822(hw, hw->pf_id); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); } -- 2.43.0