From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AACCDA0C4E; Tue, 2 Nov 2021 12:45:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 813B04069F; Tue, 2 Nov 2021 12:45:22 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 470204068F for ; Tue, 2 Nov 2021 12:45:20 +0100 (CET) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Hk7J147kTzbd2D; Tue, 2 Nov 2021 19:40:33 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Tue, 2 Nov 2021 19:45:17 +0800 Received: from [127.0.0.1] (10.67.100.224) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Tue, 2 Nov 2021 19:45:17 +0800 To: Radha Mohan Chintakuntla , , , , , , , CC: References: <20211026041300.28924-1-radhac@marvell.com> <20211102034019.28900-1-radhac@marvell.com> From: fengchengwen Message-ID: Date: Tue, 2 Nov 2021 19:45:16 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20211102034019.28900-1-radhac@marvell.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.100.224] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote: > Add base support as ROC(Rest of Chip) API which will be used by PMD > dmadev driver. > > This patch adds routines to init, fini, configure the DPI DMA device > found in Marvell's CN9k or CN10k SoC families. > > Signed-off-by: Radha Mohan Chintakuntla > --- ... > --- /dev/null > +++ b/drivers/common/cnxk/hw/dpi.h > @@ -0,0 +1,141 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2021 Marvell. > + */ > +/** > + * DPI device HW definitions. > + */ > +#ifndef __DEV_DPI_HW_H__ > +#define __DEV_DPI_HW_H__ suggest remove __ to avoid conflict with gcc reserved symbol. ... > + > +int > +roc_dpi_configure(struct roc_dpi *roc_dpi) > +{ > + struct plt_pci_device *pci_dev; > + const struct plt_memzone *dpi_mz; > + dpi_mbox_msg_t mbox_msg; > + struct npa_pool_s pool; > + struct npa_aura_s aura; > + int rc, count, buflen; > + uint64_t aura_handle; > + plt_iova_t iova; > + char name[32]; > + > + if (!roc_dpi) { > + plt_err("roc_dpi is NULL"); > + return -EINVAL; > + } > + > + pci_dev = roc_dpi->pci_dev; > + memset(&pool, 0, sizeof(struct npa_pool_s)); > + pool.nat_align = 1; > + > + memset(&aura, 0, sizeof(aura)); > + rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE, > + DPI_CMD_QUEUE_BUFS, &aura, &pool); > + if (rc) { > + plt_err("Failed to create NPA pool, err %d\n", rc); > + return rc; > + } > + > + snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid); > + buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS; > + dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0, > + DPI_CMD_QUEUE_SIZE); > + if (dpi_mz == NULL) { > + plt_err("dpi memzone reserve failed"); > + rc = -ENOMEM; > + goto err1; currently, err1 will free dpi_mz which is NULL, it should invoke roc_npa_pool_destroy instead. > + } > + > + roc_dpi->mz = dpi_mz; > + iova = dpi_mz->iova; > + for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) { > + roc_npa_aura_op_free(aura_handle, 0, iova); > + iova += DPI_CMD_QUEUE_SIZE; > + } > + > + roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0); > + if (!roc_dpi->chunk_base) { > + plt_err("Failed to alloc buffer from NPA aura"); > + rc = -ENOMEM; > + goto err2; > + } > + > + roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0); > + if (!roc_dpi->chunk_next) { > + plt_err("Failed to alloc buffer from NPA aura"); > + rc = -ENOMEM; > + goto err2; > + } > + > + roc_dpi->aura_handle = aura_handle; > + /* subtract 2 as they have already been alloc'ed above */ > + roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2; > + > + plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL); > + plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7, > + roc_dpi->rbase + DPI_VDMA_SADDR); > + mbox_msg.u[0] = 0; > + mbox_msg.u[1] = 0; > + /* DPI PF driver expects vfid starts from index 0 */ > + mbox_msg.s.vfid = roc_dpi->vfid; > + mbox_msg.s.cmd = DPI_QUEUE_OPEN; > + mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE; > + mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle); > + mbox_msg.s.sso_pf_func = idev_sso_pffunc_get(); > + mbox_msg.s.npa_pf_func = idev_npa_pffunc_get(); > + > + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg, > + sizeof(dpi_mbox_msg_t)); > + if (rc < 0) { > + plt_err("Failed to send mbox message %d to DPI PF, err %d", > + mbox_msg.s.cmd, rc); > + goto err2; > + } > + > + return rc; > + > +err2: > + roc_npa_pool_destroy(aura_handle); > +err1: > + plt_memzone_free(dpi_mz); > + return rc; > +} > + ... >