From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 350F5A0C3F; Sat, 12 Jun 2021 09:09:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1100E4014F; Sat, 12 Jun 2021 09:09:13 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 2C9F74003F for ; Sat, 12 Jun 2021 09:09:11 +0200 (CEST) Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G27zV6sX5zZcpB; Sat, 12 Jun 2021 15:06:14 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Sat, 12 Jun 2021 15:09:07 +0800 Received: from [127.0.0.1] (10.40.190.165) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Sat, 12 Jun 2021 15:09:06 +0800 From: fengchengwen To: Ruifeng Wang , Thomas Monjalon , ferruh.yigit CC: dev , Jerin Jacob , viktorin , "Richardson, Bruce" , Honnappa Nagarahalli , jerinjacobk , =?UTF-8?Q?Juraj_Linke=c5=a1?= , nd References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1621862602-51782-1-git-send-email-fengchengwen@huawei.com> <1621862602-51782-3-git-send-email-fengchengwen@huawei.com> Message-ID: Date: Sat, 12 Jun 2021 15:09:06 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [10.40.190.165] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v8 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Friendly ping On 2021/5/27 15:07, Fengchengwen wrote: > > Hi, Ferruh > > Could you review this patch ? Thanks > > > From:Ruifeng Wang > To:Fengchengwen ;Thomas Monjalon ;ferruh.yigit > Cc:dev ;Jerin Jacob ;viktorin ;Richardson, Bruce ;Honnappa Nagarahalli ;jerinjacobk ;Juraj Linkeš ;nd ;nd > Date:2021-05-25 14:04:52 > Subject:RE: [PATCH v8 2/2] net/hns3: refactor SVE code compile method > >> -----Original Message----- >> From: Chengwen Feng < fengchengwen@huawei.com> >> Sent: Monday, May 24, 2021 9:23 PM >> To: thomas@monjalon.net; ferruh.yigit@intel.com >> Cc: dev@dpdk.org; jerinj@marvell.com; Ruifeng Wang >> < Ruifeng.Wang@arm.com>; viktorin@rehivetech.com; >> bruce.richardson@intel.com; Honnappa Nagarahalli >> < Honnappa.Nagarahalli@arm.com>; jerinjacobk@gmail.com; >> juraj.linkes@pantheon.tech; nd < nd@arm.com> >> Subject: [PATCH v8 2/2] net/hns3: refactor SVE code compile method >> >> Currently, the SVE code is compiled only when -march supports SVE (e.g. '- >> march=armv8.2a+sve'), there maybe some problem[1] with this approach. >> >> The solution: >> a. If the minimum instruction set support SVE then compiles it. >> b. Else if the compiler support SVE then compiles it. >> c. Otherwise don't compile it. >> >> Note: this patch also fixes compile error with gcc8.3 + '-march=armv8.a+sve', >> the error is arm_sve.h no such file or directory. >> >> [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html >> >> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") >> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") >> Cc: stable@dpdk.org >> >> Signed-off-by: Chengwen Feng < fengchengwen@huawei.com> >> --- >> drivers/net/hns3/hns3_rxtx.c | 2 +- >> drivers/net/hns3/meson.build | 20 +++++++++++++++++++- >> 2 files changed, 20 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c >> index 1d7a769..9b2f082 100644 >> --- a/drivers/net/hns3/hns3_rxtx.c >> +++ b/drivers/net/hns3/hns3_rxtx.c >> @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) >> static bool >> hns3_get_sve_support(void) >> { >> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) >> +#if defined(CC_SVE_ACLE_SUPPORT) >> if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) >> return false; >> if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) >> diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build >> index 53c7df7..aabcf23 100644 >> --- a/drivers/net/hns3/meson.build >> +++ b/drivers/net/hns3/meson.build >> @@ -35,7 +35,25 @@ deps += ['hash'] >> >> if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') >> sources += files('hns3_rxtx_vec.c') >> - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' >> + >> + # compile SVE when: >> + # a. support SVE in minimum instruction set baseline >> + # b. it's not minimum instruction set, but compiler support >> + if dpdk_conf.has('CC_SVE_ACLE_SUPPORT') >> sources += files('hns3_rxtx_vec_sve.c') >> + elif cc.has_argument('-march=armv8.2-a+sve') and >> cc.check_header('arm_sve.h') >> + cflags += ['-DCC_SVE_ACLE_SUPPORT=1'] >> + sve_cflags = [] >> + foreach flag: cflags >> + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or >> flag.startswith('-mtune=')) >> + sve_cflags += flag >> + endif >> + endforeach >> + hns3_sve_lib = static_library('hns3_sve_lib', >> + 'hns3_rxtx_vec_sve.c', >> + dependencies: [static_rte_ethdev], >> + include_directories: includes, >> + c_args: [sve_cflags, '-march=armv8.2-a+sve']) >> + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') >> endif >> endif >> -- >> 2.8.1 > > Reviewed-by: Ruifeng Wang < ruifeng.wang@arm.com> >