Re: [PATCH v4 23/25] net/intel: support wider x86 vectors for Rx rearm

[Bruce Richardson <bruce.richardson@intel.com>]

On Fri, May 30, 2025 at 02:57:19PM +0100, Anatoly Burakov wrote:
> Currently, for 32-byte descriptor format, only SSE instruction set is
> supported. Add implementation for AVX2 and AVX512 instruction sets. Since
> we are using Rx descriptor definitions from common code, we can just use
> the generic descriptor definition, as we only ever write the first 16 bytes
> of it, and the layout is always the same for that part.
> 
> Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
> ---
> 
> Notes:
>     v3 -> v4:
>     - Use the common descriptor format instead of constant propagation
>     - Syntax and whitespace cleanups
> 
>  drivers/net/intel/common/rx_vec_x86.h | 339 ++++++++++++++------------
>  1 file changed, 183 insertions(+), 156 deletions(-)
> 
> diff --git a/drivers/net/intel/common/rx_vec_x86.h b/drivers/net/intel/common/rx_vec_x86.h
> index 7c57016df7..43f7c59449 100644
> --- a/drivers/net/intel/common/rx_vec_x86.h
> +++ b/drivers/net/intel/common/rx_vec_x86.h
> @@ -43,206 +43,244 @@ _ci_rxq_rearm_get_bufs(struct ci_rx_queue *rxq)
>  	return 0;
>  }
>  
> -/*
> - * SSE code path can handle both 16-byte and 32-byte descriptors with one code
> - * path, as we only ever write 16 bytes at a time.
> - */
> -static __rte_always_inline void
> -_ci_rxq_rearm_sse(struct ci_rx_queue *rxq)
> +static __rte_always_inline __m128i
> +_ci_rxq_rearm_desc_sse(const __m128i vaddr)

This function needs a comment, describing the inputs and outputs.
From my reading, the input is 16bytes of mbuf header starting from the
buffer address, with second 8 bytes being the iova, if we have separate
iova field.
Output is 16B of descriptor to write.

/Bruce