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Mon, 9 Jun 2025 07:58:00 +0000 Date: Mon, 9 Jun 2025 08:57:55 +0100 From: Bruce Richardson To: "Varghese, Vipin" CC: "dev@dpdk.org" , "Song, Keesang" Subject: Re: [PATCH v4] build: reduce use of AVX compiler flags Message-ID: References: <20250325172215.3360590-1-bruce.richardson@intel.com> <20250529154249.1310449-1-bruce.richardson@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: DU6P191CA0051.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:53e::7) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|IA1PR11MB6219:EE_ X-MS-Office365-Filtering-Correlation-Id: a4331359-4b1a-40ca-c6a7-08dda72b5a8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?n2GgjGM/6e850vzFvbYhVUe2yyzFRDCiuEPiBOV+8O8W66cKwCzPuwKkr6RU?= =?us-ascii?Q?CNQcYg9OQYzmNmmNDbOichHINpNcOF3pAZNpRm64xotTWauR+qjonR+p7n3B?= =?us-ascii?Q?1Rj+0oLTiMsxr4XYk2stY9acfVjOxlG/9QsyH4T2HmSSfvzO1wjp3xj2byI8?= =?us-ascii?Q?c2KeoHble/DhgMMSG/IJxRbq7Hd617D0qRduqJGh1z6QUeq4/VWdmMW0rw+p?= =?us-ascii?Q?i1ifRVUF5uZau+xDI947u5dFgOOfdx//K3XGw0xvpAzHCKhKJAznUF0P+bea?= =?us-ascii?Q?3IKO1iAATha7C1YaZpctH15ockXoESvaNDthrLmsALNO3DoOEse7WTBhQzRN?= =?us-ascii?Q?Vuo7C7bIM684UswEKFPW8nd7H9pnxZRZ4syLZPJbmjZY7j6qeXddbcEg9kI+?= =?us-ascii?Q?dwohxGXesHk+ArzxCErv699cB9xLrTLLlR66okhyQHWs01NnbEy1KVDaxW1O?= =?us-ascii?Q?EL1ddisi15nTlaXl1/BrIYmaA4jKUtabkXgH7IHHfyIFuNLSxwms2GWlzl1t?= =?us-ascii?Q?HuiIcuVGgvCJCJSXL7NbyyVQK4oxUQ9cWYiDCgPzrfnUWv9BzjVXWzf4EDaz?= =?us-ascii?Q?FawTT1od5zeo9N9uaDHikY9nwe6rOIX4Sb03UWn+uRtoHouEikptsbyrDrv6?= =?us-ascii?Q?iLv/kZle0uVoFF6u2bs+k+FPPJIzj25fhLGahm2hm352PCf/vhM6LsnxEc+e?= =?us-ascii?Q?kdBc7sCRgjlen0Bu3Q5F1fcVZ/j9m1uDFlNIgWo+sYkT4+QnnBPgBUNUeGdw?= =?us-ascii?Q?fgUjZlvCqhaRNdoZHiU8H40ZzZnCZM97QbI+2HYo4+/5EWhvb9r3JWut0uLy?= =?us-ascii?Q?Igh1Q03wcrPbv6v6eH005XDBTlKebC3mIjifiwSD3lZO7u9bXx1Ic4CacLFF?= =?us-ascii?Q?EMU9qLx3ZHjL5KLsS3TNeeH0Py+UEXfk2YTC+UK5QBLdoZoOYKeN6IIpLlc5?= =?us-ascii?Q?CR/nrK6XaX5xhRlVRjDVwUFXD5toeUHxSv3blHEj2qagxH57p+c8XPJ5qG01?= =?us-ascii?Q?cUsA+AkgP9+Enzdy5Rd9vwzpiJwN0wQS/x0QsEdITxiAX10tiRb0lAQtAIuh?= =?us-ascii?Q?7VneGStT8WWOjX4kzUTDr8iuxCk4O/kgsx9CgMjXQszQaD6ss+sO7thcC8Ez?= =?us-ascii?Q?uoSKe/a+D2C86mp+TVRQk5sv5263yehav793A66K8VzrwgeW+o8M8/EtRDf6?= =?us-ascii?Q?ZlR2FCJ8FgHvyHBw0B77D6Fj13+86YMdTzK62YtS/vmesRw67A1nebMBD8Yz?= =?us-ascii?Q?8Yn2yoXiF++VAB1L2SgHY4RzjNWNa92/D33BcSRTuYqxmogYRB55hs/tkuO8?= =?us-ascii?Q?HF5ohailQTR6SdbSqGW/fRnaFS1QgQ7j3pZJOWUQelPGVtmPFJB3ZN6NuvLs?= =?us-ascii?Q?JcfH6SqrkHh6bRAWF3yQ1pZO1UPy?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Instead, when the default > > flags produce the desired output, just use them unmodified, and don't bother adding > > in extra enabling flags for AVX2 or AVX-512. > > > > Depends-on: series-35006 ("doc/linux_gsg: update recommended compiler > > versions") > > > > Signed-off-by: Bruce Richardson > > --- > > > > V4: Fix error flagged by CI with clang builds without AVX512 - change > > "cc_avx512_args" to correct "cc_avx512_flags" > > > > V3: put in version check to work around an issues with some meson > > versions, (hopefully) allowing builds to pass in all CIs. The > > printout of the extra flags now only happens with meson >= 0.60.2 > > > > V2: dropped the doc update for the minimum compiler version. Based on > > discussion, that version bump is larger than proposed in RFC and is > > now a separate patch/series [series 35006 referenced above] > > > > --- > > config/x86/meson.build | 31 ++++++++++++++++++++----------- > > drivers/meson.build | 9 +-------- > > lib/meson.build | 9 +-------- > > 3 files changed, 22 insertions(+), 27 deletions(-) > > > > diff --git a/config/x86/meson.build b/config/x86/meson.build index > > c3564b0011..e6612dbd80 100644 > > --- a/config/x86/meson.build > > +++ b/config/x86/meson.build > > @@ -4,11 +4,13 @@ > > if is_ms_compiler > > cc_avx2_flags = ['/arch:AVX2'] > > else > > - cc_avx2_flags = ['-mavx2'] > > + cc_avx2_flags = [] > > + if cc.get_define('__AVX2__', args: machine_args) == '' > > + cc_avx2_flags = ['-mavx2'] > > + endif > > endif > > > > cc_has_avx512 = false > > -target_has_avx512 = false > > > > dpdk_conf.set('RTE_ARCH_X86', 1) > > if dpdk_conf.get('RTE_ARCH_64') > > @@ -65,26 +67,33 @@ if is_linux or cc.get_id() == 'gcc' > > endif > > endif > > > > -cc_avx512_flags = ['-mavx512f', '-mavx512vl', '-mavx512dq', '-mavx512bw', '- > > mavx512cd'] -if (binutils_ok and cc.has_multi_arguments(cc_avx512_flags) > > +avx512_march_flag = '-march=skylake-avx512' > > +cc_avx512_flags = [] > > +if (binutils_ok and cc.has_argument(avx512_march_flag) > > and '-mno-avx512f' not in get_option('c_args')) > > # check if compiler is working with _mm512_extracti64x4_epi64 > > # Ref: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82887 > > code = '''#include > > void test(__m512i zmm){ > > __m256i ymm = _mm512_extracti64x4_epi64(zmm, 0);}''' > > - result = cc.compiles(code, args : cc_avx512_flags, name : 'AVX512 checking') > > + result = cc.compiles(code, args : [avx512_march_flag], name : > > + 'AVX512 checking') > > if result == false > > machine_args += '-mno-avx512f' > > warning('Broken _mm512_extracti64x4_epi64, disabling AVX512 support') > > else > > cc_has_avx512 = true > > - target_has_avx512 = ( > > - cc.get_define('__AVX512F__', args: machine_args) != '' and > > - cc.get_define('__AVX512BW__', args: machine_args) != '' and > > - cc.get_define('__AVX512DQ__', args: machine_args) != '' and > > - cc.get_define('__AVX512VL__', args: machine_args) != '' > > - ) > > + if cc.get_define('__AVX512F__', args: machine_args) == '' > > + cc_avx512_flags = [avx512_march_flag] > > Hi Bruce, we have reviewed this internally and tested the same. We would like your thought for the following. > > - Before patch: we were directly setting AVX512 falgs for F, BW, DQ, VL > - new patch: we are setting the flags for `skylake-server` as bare minimal. > - AMD supports AVX512 from `znver4 and higher`. > > As per GCC `https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html`, the extra ISA supported between skylake-server (super set) and znver4 and znver5 are `SAHF, FXSR, XSAVE, RDRND, LZCNT, HLE, PREFETCHW, SGX`. > Currently for DPDK microbenchmarks and examples runs safe as it is not using the `SAHF, FXSR, XSAVE, RDRND, LZCNT, HLE, PREFETCHW, SGX` instructions. > > Question: should we check if target is `AMD EPYC` then apply bare minimum as `-march=znver4`, thus avoid possible unsupported instruction generation when non `c_args for march` is passed? > Can you clarify why you mean by the "target" here? Is there a specific value you are thinking of for the "cpu_instruction_set" option? /Bruce