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Mon, 9 Jun 2025 15:21:16 +0000 Date: Mon, 9 Jun 2025 16:21:10 +0100 From: Bruce Richardson To: Soumyadeep Hore CC: , , Subject: Re: [PATCH v3 5/6] net/intel: add AVX512 Support for TxPP Message-ID: References: <20250606211947.473544-2-soumyadeep.hore@intel.com> <20250608113223.487043-1-soumyadeep.hore@intel.com> <20250608113223.487043-6-soumyadeep.hore@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250608113223.487043-6-soumyadeep.hore@intel.com> X-ClientProxiedBy: DU2PR04CA0034.eurprd04.prod.outlook.com (2603:10a6:10:234::9) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|SJ5PPFD56C4208E:EE_ X-MS-Office365-Filtering-Correlation-Id: 7779c424-31fc-439a-106e-08dda76946e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ExONoBxgvovAUHUwUs2X/36lHJel5vj8AFbpY8fdgXdy803wHB1URJGvSsqH?= =?us-ascii?Q?nl78j72AnftlnfA3zzQ6vPOiW/x8APfe4DfGSpg0BmdXDrwswjJDeb/kmu/r?= =?us-ascii?Q?qWFmMh+fy4WfWCAzI7qns4sBCZw4VIzot80RkJ8wPGpajvfC/ry82ymNoQGu?= =?us-ascii?Q?aIXBJ/F5KabG7AETPwsIusFJ/u/6Q+mV4UB9cEgcHks+uumSZN5SIs6TBd9I?= =?us-ascii?Q?iooI7piLsqLxpni1VjOSZY26vrRsb7hMjj6JrBxhQjPp4DLRfw4kx882VHqR?= =?us-ascii?Q?vPGpGo0l7j5/eG81qyMt0B5PoIY1+565Wc6LIWO5fuQjeOimb25IuV2UcH2+?= =?us-ascii?Q?BrcR23wC2ZNlepy7hxtIYpDQ+ovQssaekzU3Z8GqoUE0hWGI55jw/Ix0p9Y5?= =?us-ascii?Q?mDmuL9hYetTSh6AQXEFHrIznfMdLaSndWWYBv7+oumyJzUHCtX714zQ+U1G4?= =?us-ascii?Q?RbduTx51xjCsGRaAZOAjc+AyX9f3Xa/xQokGuEsQVAzB2EKDsQcebbRoJKxB?= =?us-ascii?Q?JYCS7U51ocPztnSvtS7+eVFj/UCRXsg6tCsy/ywuZzyt7qFI9SZfjuLXCS3d?= =?us-ascii?Q?HzhQLO56pUAknjtAgXN9K2vtFfB6Qp16pxOxfkG0SPJujwlO9sNkZTRQshCR?= =?us-ascii?Q?MVYl3SJ3LjbVq7tfKxpxzP/9ALE/sAMQGC20uxCPmUbcrcpr7/0zuT5HhQej?= =?us-ascii?Q?Ew7QNAcNiilsXXNSCNiaiT7sy85sQwePdO1U2s/fBTreTpjMV/sIlYuxvM3A?= =?us-ascii?Q?r92wmB890L3fAVsxhoBf+VsYm2Dto/49OVUNGvvCYlBNHEEzErWBreOYt/O3?= =?us-ascii?Q?i39v2AMQGXbJLPRCaptPOrnBy6kpud3df2TrvGZBNRstDEqaXLrAgSU1zgEr?= =?us-ascii?Q?T/iJnmZVTjMHEJ3pgIjMTgexe/lqgZYIebpC2g5ojWkL3efJ6bSBcrdhntTF?= =?us-ascii?Q?sbph/kLwEMlQzycPRnthgepFiPbqNQE/QJCRpu+YfvbYHjRWVJcMLKRQgTb9?= =?us-ascii?Q?jPJT6aNKz8nJzl4SesX+B7NwZgVl5QbduGHWKONBxqKMUuYfUtU8viPgWkUg?= =?us-ascii?Q?WeEiArx1obxuRt5m0vBUHxlwwbffW2NWCK0/Rf0Jl+nbGhrvr3qZPmzIx5va?= =?us-ascii?Q?kFCykpBnep35r9LKHYRpGHMCuJf/AzV1sdRZyjoag8I3lKJgAM8oJDv+suLW?= =?us-ascii?Q?dWy/SvDorkqejvHaZ7D+ibdVc9dnDeFDVQHvKK1QBhK6MGN81UlCzMDdlFcl?= =?us-ascii?Q?D7YvDhB4HpgdMflxt/ABvqFF+JYzOZlFJPoij32KOxqQfFkJ7NUnRknMppX4?= =?us-ascii?Q?T/AYFPHAt7iAh6+bGeGbWXtdMM6CVQWiqzPqLjaazaet49UYCmsOsTuZGKlD?= =?us-ascii?Q?jKIY9vPKZ5ABeOJce4qVMupboo8H68+rhjx9x7RjSh6UWkWqUgAgPetef9NM?= =?us-ascii?Q?9ad4Crempe8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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> +} > + > +static __rte_always_inline void > +ice_vts4(volatile struct ice_ts_desc *ts, struct rte_mbuf **pkt, > + uint16_t nb_pkts, uint16_t tx_tail, uint16_t nb_tx_desc, > + int ts_offset) > +{ > + uint16_t tx_id; > + > + for (; nb_pkts > 3; ts += 4, pkt += 4, nb_pkts -= 4, > + tx_tail += 4) { > + tx_id = tx_tail + 4; > + uint32_t ts_dsc3 = ice_get_ts_queue_desc(pkt[3], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 3; > + uint32_t ts_dsc2 = ice_get_ts_queue_desc(pkt[2], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 2; > + uint32_t ts_dsc1 = ice_get_ts_queue_desc(pkt[1], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 1; > + uint32_t ts_dsc0 = ice_get_ts_queue_desc(pkt[0], > + tx_id, nb_tx_desc, ts_offset); > + __m128i desc0_3 = _mm_set_epi32(ts_dsc3, ts_dsc2, > + ts_dsc1, ts_dsc0); > + _mm_store_si128(RTE_CAST_PTR(void *, ts), desc0_3); > + } > + > + /* do any last ones */ > + while (nb_pkts) { > + tx_tail++; > + ice_vts1(ts, *pkt, tx_tail, nb_tx_desc, ts_offset); > + ts++, pkt++, nb_pkts--; > + } > +} > + > +static __rte_always_inline void > +ice_vts8(volatile struct ice_ts_desc *ts, struct rte_mbuf **pkt, > + uint16_t nb_pkts, uint16_t tx_tail, uint16_t nb_tx_desc, > + int ts_offset) > +{ > + uint16_t tx_id; > + > + for (; nb_pkts > 7; ts += 8, pkt += 8, nb_pkts -= 8, > + tx_tail += 8) { > + tx_id = tx_tail + 8; > + uint32_t ts_dsc7 = ice_get_ts_queue_desc(pkt[7], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 7; > + uint32_t ts_dsc6 = ice_get_ts_queue_desc(pkt[6], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 6; > + uint32_t ts_dsc5 = ice_get_ts_queue_desc(pkt[5], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 5; > + uint32_t ts_dsc4 = ice_get_ts_queue_desc(pkt[4], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 4; > + uint32_t ts_dsc3 = ice_get_ts_queue_desc(pkt[3], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 3; > + uint32_t ts_dsc2 = ice_get_ts_queue_desc(pkt[2], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 2; > + uint32_t ts_dsc1 = ice_get_ts_queue_desc(pkt[1], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 1; > + uint32_t ts_dsc0 = ice_get_ts_queue_desc(pkt[0], > + tx_id, nb_tx_desc, ts_offset); > + __m256i desc0_7 = _mm256_set_epi32(ts_dsc7, ts_dsc6, > + ts_dsc5, ts_dsc4, ts_dsc3, ts_dsc2, > + ts_dsc1, ts_dsc0); > + _mm256_storeu_si256(RTE_CAST_PTR(void *, ts), desc0_7); > + } > + > + /* do any last ones */ > + if (nb_pkts) > + ice_vts4(ts, pkt, nb_pkts, tx_tail, nb_tx_desc, > + ts_offset); > +} > + > +static __rte_always_inline void > +ice_vts(volatile struct ice_ts_desc *ts, struct rte_mbuf **pkt, > + uint16_t nb_pkts, uint16_t tx_tail, uint16_t nb_tx_desc, > + int ts_offset) > +{ > + uint16_t tx_id; > + > + for (; nb_pkts > 15; ts += 16, pkt += 16, nb_pkts -= 16, > + tx_tail += 16) { > + tx_id = tx_tail + 16; > + uint32_t ts_dsc15 = ice_get_ts_queue_desc(pkt[15], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 15; > + uint32_t ts_dsc14 = ice_get_ts_queue_desc(pkt[14], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 14; > + uint32_t ts_dsc13 = ice_get_ts_queue_desc(pkt[13], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 13; > + uint32_t ts_dsc12 = ice_get_ts_queue_desc(pkt[12], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 12; > + uint32_t ts_dsc11 = ice_get_ts_queue_desc(pkt[11], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 11; > + uint32_t ts_dsc10 = ice_get_ts_queue_desc(pkt[10], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 10; > + uint32_t ts_dsc9 = ice_get_ts_queue_desc(pkt[9], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 9; > + uint32_t ts_dsc8 = ice_get_ts_queue_desc(pkt[8], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 8; > + uint32_t ts_dsc7 = ice_get_ts_queue_desc(pkt[7], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 7; > + uint32_t ts_dsc6 = ice_get_ts_queue_desc(pkt[6], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 6; > + uint32_t ts_dsc5 = ice_get_ts_queue_desc(pkt[5], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 5; > + uint32_t ts_dsc4 = ice_get_ts_queue_desc(pkt[4], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 4; > + uint32_t ts_dsc3 = ice_get_ts_queue_desc(pkt[3], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 3; > + uint32_t ts_dsc2 = ice_get_ts_queue_desc(pkt[2], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 2; > + uint32_t ts_dsc1 = ice_get_ts_queue_desc(pkt[1], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 1; > + uint32_t ts_dsc0 = ice_get_ts_queue_desc(pkt[0], > + tx_id, nb_tx_desc, ts_offset); > + __m512i desc0_15 = _mm512_set_epi32(ts_dsc15, ts_dsc14, > + ts_dsc13, ts_dsc12, ts_dsc11, ts_dsc10, > + ts_dsc9, ts_dsc8, ts_dsc7, ts_dsc6, > + ts_dsc5, ts_dsc4, ts_dsc3, ts_dsc2, > + ts_dsc1, ts_dsc0); > + _mm512_storeu_si512(RTE_CAST_PTR(void *, ts), desc0_15); > + } > + > + /* do any last ones */ > + if (nb_pkts) > + ice_vts8(ts, pkt, nb_pkts, tx_tail, nb_tx_desc, > + ts_offset); > +} > + > +static __rte_always_inline uint16_t > +ice_xmit_fixed_ts_burst_vec_avx512(struct ci_tx_queue *txq, > + struct rte_mbuf **tx_pkts, uint16_t nb_pkts, > + uint16_t tx_tail) > +{ > + volatile struct ice_ts_desc *ts; > + uint16_t n; > + uint16_t ts_id; > + uint16_t fetch; > + > + ts_id = txq->tsq.ts_tail; > + ts = &txq->tsq.ice_ts_ring[ts_id]; > + > + n = (uint16_t)(txq->tsq.nb_ts_desc - ts_id); > + if (nb_pkts >= n) { > + ice_vts(ts, tx_pkts, n, txq->tx_tail, txq->nb_tx_desc, > + txq->tsq.ts_offset); > + tx_pkts += n; > + ts += n; > + tx_tail += n; > + nb_pkts = (uint16_t)(nb_pkts - n); > + ts_id = 0; > + ts = &txq->tsq.ice_ts_ring[ts_id]; > + fetch = txq->tsq.nb_ts_desc - txq->nb_tx_desc; > + for (; ts_id < fetch; ts_id++, ts++) > + ice_vts1(ts, *tx_pkts, tx_tail + 1, > + txq->nb_tx_desc, txq->tsq.ts_offset); > + } > + > + ice_vts(ts, tx_pkts, nb_pkts, tx_tail, txq->nb_tx_desc, > + txq->tsq.ts_offset); > + ts_id = (uint16_t)(ts_id + nb_pkts); > + > + return ts_id; > +} > + > static __rte_always_inline uint16_t > ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, > uint16_t nb_pkts, bool do_offload) > @@ -920,6 +1114,7 @@ ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, > volatile struct ice_tx_desc *txdp; > struct ci_tx_entry_vec *txep; > uint16_t n, nb_commit, tx_id; > + uint16_t ts_id = -1; > uint64_t flags = ICE_TD_CMD; > uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD; > > @@ -940,6 +1135,10 @@ ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, > > txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts); > > + if (txq->tsq.ts_flag > 0) > + ts_id = ice_xmit_fixed_ts_burst_vec_avx512(txq, > + tx_pkts, nb_commit, tx_id); > + > n = (uint16_t)(txq->nb_tx_desc - tx_id); > if (nb_commit >= n) { > ci_tx_backlog_entry_vec(txep, tx_pkts, n); > @@ -975,7 +1174,12 @@ ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, > > txq->tx_tail = tx_id; > > - ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail); > + if (txq->tsq.ts_flag > 0) { > + ICE_PCI_REG_WC_WRITE(txq->qtx_tail, ts_id); > + txq->tsq.ts_tail = ts_id; > + } else { > + ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail); > + } > > return nb_pkts; > } > -- > 2.43.0 >