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Mon, 9 Jun 2025 15:20:04 +0000 Date: Mon, 9 Jun 2025 16:19:58 +0100 From: Bruce Richardson To: Soumyadeep Hore CC: , , Subject: Re: [PATCH v3 4/6] net/intel: add AVX2 Support for TxPP Message-ID: References: <20250606211947.473544-2-soumyadeep.hore@intel.com> <20250608113223.487043-1-soumyadeep.hore@intel.com> <20250608113223.487043-5-soumyadeep.hore@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250608113223.487043-5-soumyadeep.hore@intel.com> X-ClientProxiedBy: DU2P250CA0015.EURP250.PROD.OUTLOOK.COM (2603:10a6:10:231::20) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|SJ5PPFD56C4208E:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d91397c-f55e-4b7b-667c-08dda7691c4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qA/LdUQ50EV0nB8H7HC2uspO3nHkvsHpxBAeaSPHykSxaNAlKCpU1Wl1RzvO?= =?us-ascii?Q?ojGIofCjJfuasLJqjcPlYP+0y9ux4LDO4QfGksMmOFPA3/9lQlxD/5v7cDF7?= =?us-ascii?Q?Z4Zl2MVNXH8x/Sc0UTzxkDTpTjjSkMoiSpiXhbLwUL/6rEj0mC/UuLwm9Y6b?= =?us-ascii?Q?Y3QNBLl7MdqaMBzupK9nRF5tBCR/2035WRQzzDBoYDE5FmKGd8jNOXLX5/ez?= =?us-ascii?Q?OAZbC61ok5+zZrMmekOvaZ14HUsHcwupf0xR6Z7dlWJJEo4tQiOjE/Rb539R?= =?us-ascii?Q?GjQ91JwrnVzjX3reGDKXzlyXkDKFIe56WyJapb5nWvK96xBDY+60INZTGjNk?= =?us-ascii?Q?OmWaR8ZobNQDE2LE1hD+vkSdY3rEfktkU4yorOC37Os/R8CUTM4ESNubjcgO?= =?us-ascii?Q?1/4l+fMKVPv3YLtKjNQHgIOi05kqREOBvQNfi9V6t+x93OiUJxgP1Vcjv04R?= =?us-ascii?Q?MzO86R9OlU5/0cC5iXPuRlpM1x5jZBcu5u7aSEkjqtYQKlQkoDoPwUfFbXHi?= =?us-ascii?Q?Hhe81+X2gmXgSF47p3ivrsqgmtDYg7lgy5USjzde5A6CYQWfw9DqmxDrh7ts?= =?us-ascii?Q?v6HA4/Y7TxQURSNpBwsUcMOLJjuc5fFjmkWKSR03HzR3GfyRbw84urGHWuqG?= =?us-ascii?Q?zR8Vq6/dyAMzPJetS71MV4h8lHxwj4zVJy84aUpsj8ER53i1acMUl+frJLZW?= =?us-ascii?Q?t5F4oLMrpXsfnJYDes1ZHaFTwpIB2wpLP5G3t1szQbLikrEdyWv8pEYVL6ju?= =?us-ascii?Q?nCjds5yQPTeE3GIjGTQKIuZJKE1u8yRk+EolZ9IZeSES+5EorHTpv61W7IPI?= =?us-ascii?Q?S6na3f8qZ7O8h8wvi537aG5MuzKqs3FTdx94Hobkc2CFCS04SL4BpHIrQSMJ?= =?us-ascii?Q?XwtEOTUNp3E5Cc2IdexJyS3uu1LkCB3b/CZu1ZYfOWQCuQoXoLGGxVZ1+SPr?= =?us-ascii?Q?Ev7movosyp8AP4hVX1gBBXmjmZdvwoLD41oejeVIBYDoQlCFVBohO3PVVra3?= =?us-ascii?Q?FvoBOwJmq9cqPEURQ+VQg3jILfqph6MbGJ8E4MjvdfXpBphhKMXyVMWbCZpw?= =?us-ascii?Q?58CDmxBmYdml7lJ36ivL8Ng16PXaKgiX1QY36hlVgKj735u1xKT+FEIXEZHz?= =?us-ascii?Q?K7r7sMC/9klag11cEbsqYm17ZOHzdMkOej7xp33eUlDB5tdq4QZa5W6mmDYo?= =?us-ascii?Q?GgAAqyqDbAhvy/8Ruemt5DEqHdH1rX1I7C1gAWtyrGqaV3WD9Tlf6rfrL+0Y?= =?us-ascii?Q?4J/p66Ip7xAEc4kPlx4XCvnu8kYVb7rNdEP+dL44SCcP8zRqz22S3bVUeUhj?= =?us-ascii?Q?DfKXeJItGOgNbhW1KTUi7lUXKDeUI9SLUlMM4FOjJWyn4Ga3U3lkIzBDLwBX?= =?us-ascii?Q?KUHjRjp5v5ZHtgL/lHqqlxLmDV/wdlWOgG3SU5WoCXRCFcaTDLKnhNbIICid?= =?us-ascii?Q?pVX8S9KxLfE=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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> +} > + > +static __rte_always_inline void > +ice_vts4(volatile struct ice_ts_desc *ts, struct rte_mbuf **pkt, > + uint16_t nb_pkts, uint16_t tx_tail, uint16_t nb_tx_desc, > + int ts_offset) > +{ > + uint16_t tx_id; > + > + for (; nb_pkts > 3; ts += 4, pkt += 4, nb_pkts -= 4, > + tx_tail += 4) { > + tx_id = tx_tail + 4; > + uint32_t ts_dsc3 = ice_get_ts_queue_desc(pkt[3], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 3; > + uint32_t ts_dsc2 = ice_get_ts_queue_desc(pkt[2], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 2; > + uint32_t ts_dsc1 = ice_get_ts_queue_desc(pkt[1], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 1; > + uint32_t ts_dsc0 = ice_get_ts_queue_desc(pkt[0], > + tx_id, nb_tx_desc, ts_offset); > + __m128i desc0_3 = _mm_set_epi32(ts_dsc3, ts_dsc2, > + ts_dsc1, ts_dsc0); > + _mm_store_si128(RTE_CAST_PTR(void *, ts), desc0_3); > + } > + > + /* do any last ones */ > + while (nb_pkts) { > + tx_tail++; > + ice_vts1(ts, *pkt, tx_tail, nb_tx_desc, ts_offset); > + ts++, pkt++, nb_pkts--; > + } > +} > + > +static __rte_always_inline void > +ice_vts(volatile struct ice_ts_desc *ts, struct rte_mbuf **pkt, > + uint16_t nb_pkts, uint16_t tx_tail, uint16_t nb_tx_desc, > + int ts_offset) > +{ > + uint16_t tx_id; > + > + for (; nb_pkts > 7; ts += 8, pkt += 8, nb_pkts -= 8, > + tx_tail += 8) { > + tx_id = tx_tail + 8; > + uint32_t ts_dsc7 = ice_get_ts_queue_desc(pkt[7], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 7; > + uint32_t ts_dsc6 = ice_get_ts_queue_desc(pkt[6], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 6; > + uint32_t ts_dsc5 = ice_get_ts_queue_desc(pkt[5], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 5; > + uint32_t ts_dsc4 = ice_get_ts_queue_desc(pkt[4], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 4; > + uint32_t ts_dsc3 = ice_get_ts_queue_desc(pkt[3], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 3; > + uint32_t ts_dsc2 = ice_get_ts_queue_desc(pkt[2], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 2; > + uint32_t ts_dsc1 = ice_get_ts_queue_desc(pkt[1], > + tx_id, nb_tx_desc, ts_offset); > + tx_id = tx_tail + 1; > + uint32_t ts_dsc0 = ice_get_ts_queue_desc(pkt[0], > + tx_id, nb_tx_desc, ts_offset); > + __m256i desc0_7 = _mm256_set_epi32(ts_dsc7, ts_dsc6, > + ts_dsc5, ts_dsc4, ts_dsc3, ts_dsc2, > + ts_dsc1, ts_dsc0); > + _mm256_storeu_si256(RTE_CAST_PTR(void *, ts), desc0_7); > + } > + > + /* do any last ones */ > + if (nb_pkts) > + ice_vts4(ts, pkt, nb_pkts, tx_tail, nb_tx_desc, > + ts_offset); > +} > + > +static __rte_always_inline uint16_t > +ice_xmit_fixed_ts_burst_vec_avx512(struct ci_tx_queue *txq, > + struct rte_mbuf **tx_pkts, uint16_t nb_pkts, > + uint16_t tx_tail) Avx512? > +{ > + volatile struct ice_ts_desc *ts; > + uint16_t n; > + uint16_t ts_id; > + uint16_t fetch; > + > + ts_id = txq->tsq.ts_tail; > + ts = &txq->tsq.ice_ts_ring[ts_id]; > + > + n = (uint16_t)(txq->tsq.nb_ts_desc - ts_id); > + if (nb_pkts >= n) { > + ice_vts(ts, tx_pkts, n, txq->tx_tail, txq->nb_tx_desc, > + txq->tsq.ts_offset); > + tx_pkts += n; > + ts += n; > + tx_tail += n; > + nb_pkts = (uint16_t)(nb_pkts - n); > + ts_id = 0; > + ts = &txq->tsq.ice_ts_ring[ts_id]; > + fetch = txq->tsq.nb_ts_desc - txq->nb_tx_desc; > + for (; ts_id < fetch; ts_id++, ts++) > + ice_vts1(ts, *tx_pkts, tx_tail + 1, > + txq->nb_tx_desc, txq->tsq.ts_offset); > + } > + > + ice_vts(ts, tx_pkts, nb_pkts, tx_tail, txq->nb_tx_desc, > + txq->tsq.ts_offset); > + ts_id = (uint16_t)(ts_id + nb_pkts); > + > + return ts_id; > +} > + > static __rte_always_inline uint16_t > ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, > uint16_t nb_pkts, bool offload) > @@ -856,6 +979,7 @@ ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, > volatile struct ice_tx_desc *txdp; > struct ci_tx_entry_vec *txep; > uint16_t n, nb_commit, tx_id; > + uint16_t ts_id = -1; > uint64_t flags = ICE_TD_CMD; > uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD; > > @@ -875,6 +999,10 @@ ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, > > txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts); > > + if (txq->tsq.ts_flag > 0) > + ts_id = ice_xmit_fixed_ts_burst_vec_avx512(txq, > + tx_pkts, nb_commit, tx_id); > + > n = (uint16_t)(txq->nb_tx_desc - tx_id); > if (nb_commit >= n) { > ci_tx_backlog_entry_vec(txep, tx_pkts, n); > @@ -910,7 +1038,12 @@ ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, > > txq->tx_tail = tx_id; > > - ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail); > + if (txq->tsq.ts_flag > 0) { > + ICE_PCI_REG_WC_WRITE(txq->qtx_tail, ts_id); > + txq->tsq.ts_tail = ts_id; > + } else { > + ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail); > + } > Rather than having two branches in this function, if you move the call to ice_xmit_fixed_ts_burst_vec_avx* down to take place after the regular descriptor enqueue, you can do it in one. The timestamp enqueues seem independent of the regular ones. > return nb_pkts; > } > diff --git a/drivers/net/intel/ice/ice_rxtx_vec_common.h b/drivers/net/intel/ice/ice_rxtx_vec_common.h > index 7933c26366..9166a0408a 100644 > --- a/drivers/net/intel/ice/ice_rxtx_vec_common.h > +++ b/drivers/net/intel/ice/ice_rxtx_vec_common.h > @@ -215,4 +215,21 @@ ice_txd_enable_offload(struct rte_mbuf *tx_pkt, > > *txd_hi |= ((uint64_t)td_cmd) << ICE_TXD_QW1_CMD_S; > } > + > +static inline uint32_t > +ice_get_ts_queue_desc(struct rte_mbuf *pkt, uint16_t tx_tail, > + uint16_t nb_tx_desc, int ts_offset) > +{ > + uint64_t txtime; > + uint32_t tstamp, ts_desc; > + > + tx_tail = (tx_tail > nb_tx_desc) ? (tx_tail - nb_tx_desc) : > + tx_tail; > + txtime = *RTE_MBUF_DYNFIELD(pkt, ts_offset, uint64_t *); > + tstamp = (uint32_t)(txtime % NS_PER_S) >> > + ICE_TXTIME_CTX_RESOLUTION_128NS; > + ts_desc = rte_cpu_to_le_32(FIELD_PREP(ICE_TXTIME_TX_DESC_IDX_M, > + (tx_tail)) | FIELD_PREP(ICE_TXTIME_STAMP_M, tstamp)); > + return ts_desc; > +} > #endif > -- > 2.43.0 >