From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E5E3454EF; Tue, 25 Jun 2024 13:25:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DAA694327E; Tue, 25 Jun 2024 13:18:42 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 6EACE40696 for ; Tue, 25 Jun 2024 13:17:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314240; x=1750850240; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MDL+O/8H8rmIKiJZqIQ/9JP9mw8IWi5vlHDoWdRuDrw=; b=nkO6ioiGtK0BQNM6KgO1jRDXjMd3nZ5iG4a1NJ04lF18v33nTT74yuZp cNxX5NOGozvg+TyVCIqNoO+5qrYHaiK3xXMBbMp4j3+ZOA/SVqCvQO8SF vH69maXX+DsdqugZsbZ4p7aDCvfjUk197VOFPqOheGN0TXFRerqGB8NRc QBCrlUEPG7LlAGI8WUJl4GG2W3qhckWD/d3K8hbXXufp/TiTUQJ+a5NN3 wdvlGFvqSZHjYbChSMHVfTZ2m8Zix8SBomBhd7sqlG6bZBgkifhEz2oWI 0ZFKObg+HkTDczl4xEeN1gaaB5ikSs5Km3qZjG/N1G5OcC/cWVFNlJwP0 Q==; X-CSE-ConnectionGUID: JblDAo3bQRir25tKl9s0uA== X-CSE-MsgGUID: PxrYviPJRzOy3k6ffmkVrw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080431" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080431" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:17:20 -0700 X-CSE-ConnectionGUID: /0pumaFbQ7mTMMSGQTMU2A== X-CSE-MsgGUID: xNx7kG9jTDGbM+9DQV7nXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719547" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:17:19 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Jacob Keller , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 088/129] net/ice/base: add function to read Tx timestamp status register Date: Tue, 25 Jun 2024 12:13:33 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jacob Keller Both e822 and eth56g based hardware have a register indicating the status of timestamps in the Tx timestamp memory bank. This register is used to indicate which timestamps are currently valid. This is important because the interrupt logic for these devices assumes that software will only read registers with the valid bit set. If software does not follow this practice, it can potentially cause hardware to stop reporting timestamp interrupts. Use of the status register value also allows software to avoid unnecessarily reading timestamps which haven't yet been captured. Add a helper function which reads the timestamp memory status registers for these devices. For e810, it is not clear if the hardware has an equivalent register. Instead, implement a stub which just reports that all timestamps are valid. This allows the timestamp tracking logic to use the same function for all current device variants. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 113 ++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 6 ++ 2 files changed, 119 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 1f7a8b593f..593a402c0f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2374,6 +2374,33 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) return 0; } +/** + * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register + * @hw: pointer to the HW struct + * @port: the PHY port to read from + * @tstamp_ready: contents of the Tx memory status register + * + * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in + * the PHY are ready. A set bit means the corresponding timestamp is valid and + * ready to be captured from the PHY timestamp block. + */ +static int +ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, + u64 *tstamp_ready) +{ + int err; + + err = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, + tstamp_ready); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", + port, err); + return err; + } + + return 0; +} + #define ICE_DEVID_MASK 0xFFF8 /** @@ -4617,6 +4644,41 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) return 0; } +/** + * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register + * @hw: pointer to the HW struct + * @quad: the timestamp quad to read from + * @tstamp_ready: contents of the Tx memory status register + * + * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in + * the PHY are ready. A set bit means the corresponding timestamp is valid and + * ready to be captured from the PHY timestamp block. + */ +static int +ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) +{ + u32 hi, lo; + int err; + + err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", + quad, err); + return err; + } + + err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", + quad, err); + return err; + } + + *tstamp_ready = (u64)hi << 32 | (u64)lo; + + return 0; +} + /** * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations * @hw: pointer to the HW struct @@ -5148,6 +5210,22 @@ int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, return 0; } +/** + * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register + * @hw: pointer to the HW struct + * @port: the PHY port to read + * @tstamp_ready: contents of the Tx memory status register + * + * E810 devices do not use a Tx memory status register. Instead simply + * indicate that all timestamps are currently ready. + */ +static int +ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) +{ + *tstamp_ready = 0xFFFFFFFFFFFFFFFF; + return 0; +} + /* E810T SMA functions * * The following functions operate specifically on E810T hardware and are used @@ -6163,6 +6241,41 @@ int ice_ptp_init_phc(struct ice_hw *hw) return err; } +/** + * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication + * @hw: pointer to the HW struct + * @block: the timestamp block to check + * @tstamp_ready: storage for the PHY Tx memory status information + * + * Check the PHY for Tx timestamp memory status. This reports a 64 bit value + * which indicates which timestamps in the block may be captured. A set bit + * means the timestamp can be read. An unset bit means the timestamp is not + * ready and software should avoid reading the register. + */ +int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) +{ + int err; + + switch (hw->phy_model) { + case ICE_PHY_ETH56G: + err = ice_get_phy_tx_tstamp_ready_eth56g(hw, block, + tstamp_ready); + break; + case ICE_PHY_E810: + err = ice_get_phy_tx_tstamp_ready_e810(hw, block, + tstamp_ready); + break; + case ICE_PHY_E822: + err = ice_get_phy_tx_tstamp_ready_e822(hw, block, + tstamp_ready); + break; + default: + err = ICE_ERR_NOT_SUPPORTED; + } + + return err; +} + /** * refsync_pin_id_valid * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 58aa45596a..4eff3919f4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -146,8 +146,14 @@ void ice_ptp_reset_ts_memory(struct ice_hw *hw); int ice_ptp_init_phc(struct ice_hw *hw); bool refsync_pin_id_valid(struct ice_hw *hw, u8 id); int +ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready); +int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq); +int +ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts); +int +ice_ptp_read_phy_incval(struct ice_hw *hw, u8 port, u64 *incval); /* E822 family functions */ int -- 2.43.0